| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| Tom Rini | a2ac2b9 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 2 | CONFIG_SKIP_LOWLEVEL_INIT=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 3 | CONFIG_ARCH_ROCKCHIP=y |
| 4 | CONFIG_SYS_TEXT_BASE=0x00a00000 |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 5 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 6 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 7 | CONFIG_NR_DRAM_BANKS=2 |
| 8 | CONFIG_ROCKCHIP_RK3568=y |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 9 | CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y |
| 10 | CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y |
| 11 | CONFIG_SPL_MMC=y |
| 12 | CONFIG_SPL_SERIAL=y |
| 13 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 14 | CONFIG_SPL_STACK_R_ADDR=0x600000 |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 15 | CONFIG_TARGET_EVB_RK3568=y |
| 16 | CONFIG_DEBUG_UART_BASE=0xFE660000 |
| 17 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 18 | CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 19 | CONFIG_DEBUG_UART=y |
| Tom Rini | 49c8ef0 | 2021-08-23 10:25:31 -0400 | [diff] [blame] | 20 | CONFIG_SYS_LOAD_ADDR=0xc00800 |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 21 | CONFIG_FIT=y |
| 22 | CONFIG_FIT_VERBOSE=y |
| 23 | CONFIG_SPL_LOAD_FIT=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 24 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" |
| 25 | # CONFIG_DISPLAY_CPUINFO is not set |
| 26 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 27 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
| 28 | CONFIG_SPL_STACK_R=y |
| 29 | CONFIG_SPL_SEPARATE_BSS=y |
| 30 | CONFIG_SPL_CRC32_SUPPORT=y |
| 31 | CONFIG_SPL_ATF=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 32 | CONFIG_CMD_GPT=y |
| 33 | CONFIG_CMD_MMC=y |
| 34 | # CONFIG_CMD_SETEXPR is not set |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 35 | # CONFIG_SPL_DOS_PARTITION is not set |
| 36 | CONFIG_SPL_OF_CONTROL=y |
| 37 | CONFIG_OF_LIVE=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 38 | CONFIG_NET_RANDOM_ETHADDR=y |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 39 | CONFIG_SPL_REGMAP=y |
| 40 | CONFIG_SPL_SYSCON=y |
| 41 | CONFIG_SPL_CLK=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 42 | CONFIG_ROCKCHIP_GPIO=y |
| 43 | CONFIG_SYS_I2C_ROCKCHIP=y |
| 44 | CONFIG_MISC=y |
| Tom Rini | d5bfef2 | 2021-12-11 14:55:53 -0500 | [diff] [blame] | 45 | CONFIG_SUPPORT_EMMC_RPMB=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 46 | CONFIG_MMC_DW=y |
| 47 | CONFIG_MMC_DW_ROCKCHIP=y |
| 48 | CONFIG_MMC_SDHCI=y |
| 49 | CONFIG_MMC_SDHCI_SDMA=y |
| 50 | CONFIG_MMC_SDHCI_ROCKCHIP=y |
| 51 | CONFIG_DM_ETH=y |
| 52 | CONFIG_ETH_DESIGNWARE=y |
| 53 | CONFIG_GMAC_ROCKCHIP=y |
| 54 | CONFIG_REGULATOR_PWM=y |
| 55 | CONFIG_PWM_ROCKCHIP=y |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 56 | CONFIG_SPL_RAM=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 57 | CONFIG_DM_RESET=y |
| 58 | CONFIG_BAUDRATE=1500000 |
| 59 | CONFIG_DEBUG_UART_SHIFT=2 |
| 60 | CONFIG_SYSRESET=y |
| 61 | CONFIG_ERRNO_STR=y |