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Stelian Pop6afcabf2008-02-07 16:37:54 +00001/*
2 * (C) Copyright 2007-2008
Stelian Pop567fb852008-05-08 22:52:09 +02003 * Stelian Pop <stelian.pop@leadtechdesign.com>
Stelian Pop6afcabf2008-02-07 16:37:54 +00004 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
Stelian Pop983c1db2008-03-26 20:52:32 +010026#include <asm/arch/at91cap9.h>
27#include <asm/arch/at91cap9_matrix.h>
Stelian Pop4f6c8102008-05-08 20:52:10 +020028#include <asm/arch/at91sam9_smc.h>
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010029#include <asm/arch/at91_common.h>
Stelian Pop983c1db2008-03-26 20:52:32 +010030#include <asm/arch/at91_pmc.h>
31#include <asm/arch/at91_rstc.h>
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020032#include <asm/arch/clk.h>
Stelian Pop983c1db2008-03-26 20:52:32 +010033#include <asm/arch/gpio.h>
34#include <asm/arch/io.h>
Ben Warren3ae071e2008-08-12 22:11:53 -070035#include <asm/arch/hardware.h>
Stelian Popc139b172008-05-08 14:52:29 +020036#include <lcd.h>
37#include <atmel_lcdc.h>
Jean-Christophe PLAGNIOL-VILLARD64d79202008-02-17 14:15:30 +010038#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
39#include <net.h>
40#endif
Ben Warren3ae071e2008-08-12 22:11:53 -070041#include <netdev.h>
Stelian Pop6afcabf2008-02-07 16:37:54 +000042
43#define MP_BLOCK_3_BASE 0xFDF00000
44
45DECLARE_GLOBAL_DATA_PTR;
46
47/* ------------------------------------------------------------------------- */
48/*
49 * Miscelaneous platform dependent initialisations
50 */
51
Stelian Pop19883ae2008-05-08 14:52:34 +020052static void at91cap9_slowclock_hw_init(void)
53{
54 /*
55 * On AT91CAP9 revC CPUs, the slow clock can be based on an
56 * internal impreciseRC oscillator or an external 32kHz oscillator.
57 * Switch to the latter.
58 */
59#define ARCH_ID_AT91CAP9_REVB 0x399
60#define ARCH_ID_AT91CAP9_REVC 0x601
61 if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
62 unsigned i, tmp = at91_sys_read(AT91_SCKCR);
63 if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
Stelian Pop19883ae2008-05-08 14:52:34 +020064 timer_init();
65 tmp |= AT91CAP9_SCKCR_OSC32EN;
66 at91_sys_write(AT91_SCKCR, tmp);
67 for (i = 0; i < 1200; i++)
68 udelay(1000);
69 tmp |= AT91CAP9_SCKCR_OSCSEL_32;
70 at91_sys_write(AT91_SCKCR, tmp);
71 udelay(200);
72 tmp &= ~AT91CAP9_SCKCR_RCEN;
73 at91_sys_write(AT91_SCKCR, tmp);
74 }
75 }
76}
77
Stelian Pop6afcabf2008-02-07 16:37:54 +000078static void at91cap9_nor_hw_init(void)
79{
Stelian Pop983c1db2008-03-26 20:52:32 +010080 unsigned long csa;
81
Stelian Pop6afcabf2008-02-07 16:37:54 +000082 /* Ensure EBI supply is 3.3V */
Stelian Pop983c1db2008-03-26 20:52:32 +010083 csa = at91_sys_read(AT91_MATRIX_EBICSA);
84 at91_sys_write(AT91_MATRIX_EBICSA,
85 csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
Stelian Pop6afcabf2008-02-07 16:37:54 +000086 /* Configure SMC CS0 for parallel flash */
Stelian Pop983c1db2008-03-26 20:52:32 +010087 at91_sys_write(AT91_SMC_SETUP(0),
88 AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
89 AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
90 at91_sys_write(AT91_SMC_PULSE(0),
91 AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
92 AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
93 at91_sys_write(AT91_SMC_CYCLE(0),
94 AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
95 at91_sys_write(AT91_SMC_MODE(0),
96 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
97 AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
98 AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
Stelian Pop6afcabf2008-02-07 16:37:54 +000099}
100
101#ifdef CONFIG_CMD_NAND
102static void at91cap9_nand_hw_init(void)
103{
Stelian Pop983c1db2008-03-26 20:52:32 +0100104 unsigned long csa;
105
Stelian Pop6afcabf2008-02-07 16:37:54 +0000106 /* Enable CS3 */
Stelian Pop983c1db2008-03-26 20:52:32 +0100107 csa = at91_sys_read(AT91_MATRIX_EBICSA);
108 at91_sys_write(AT91_MATRIX_EBICSA,
109 csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
110 AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
Stelian Pop6afcabf2008-02-07 16:37:54 +0000111
112 /* Configure SMC CS3 for NAND/SmartMedia */
Stelian Pop983c1db2008-03-26 20:52:32 +0100113 at91_sys_write(AT91_SMC_SETUP(3),
114 AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
115 AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
116 at91_sys_write(AT91_SMC_PULSE(3),
117 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
118 AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
119 at91_sys_write(AT91_SMC_CYCLE(3),
120 AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
121 at91_sys_write(AT91_SMC_MODE(3),
122 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
123 AT91_SMC_EXNWMODE_DISABLE |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#ifdef CONFIG_SYS_NAND_DBW_16
Stelian Pop1c90df32008-05-08 20:52:14 +0200125 AT91_SMC_DBW_16 |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#else /* CONFIG_SYS_NAND_DBW_8 */
Stelian Pop1c90df32008-05-08 20:52:14 +0200127 AT91_SMC_DBW_8 |
128#endif
129 AT91_SMC_TDF_(1));
Stelian Pop6afcabf2008-02-07 16:37:54 +0000130
Stelian Pop983c1db2008-03-26 20:52:32 +0100131 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
Stelian Pop6afcabf2008-02-07 16:37:54 +0000132
133 /* RDY/BSY is not connected */
134
135 /* Enable NandFlash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100136 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
Stelian Pop6afcabf2008-02-07 16:37:54 +0000137}
138#endif
139
Stelian Pop6afcabf2008-02-07 16:37:54 +0000140#ifdef CONFIG_MACB
141static void at91cap9_macb_hw_init(void)
142{
Stelian Pop6afcabf2008-02-07 16:37:54 +0000143 /* Enable clock */
Stelian Pop983c1db2008-03-26 20:52:32 +0100144 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
Stelian Pop6afcabf2008-02-07 16:37:54 +0000145
146 /*
147 * Disable pull-up on:
148 * RXDV (PB22) => PHY normal mode (not Test mode)
149 * ERX0 (PB25) => PHY ADDR0
150 * ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
151 *
152 * PHY has internal pull-down
153 */
Stelian Pop983c1db2008-03-26 20:52:32 +0100154 writel(pin_to_mask(AT91_PIN_PB22) |
155 pin_to_mask(AT91_PIN_PB25) |
156 pin_to_mask(AT91_PIN_PB26),
157 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
Stelian Pop6afcabf2008-02-07 16:37:54 +0000158
159 /* Need to reset PHY -> 500ms reset */
Stelian Pop983c1db2008-03-26 20:52:32 +0100160 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
Stelian Pop19bd6882008-05-22 00:15:40 +0200161 (AT91_RSTC_ERSTL & (0x0D << 8)) |
Stelian Pop983c1db2008-03-26 20:52:32 +0100162 AT91_RSTC_URSTEN);
163
164 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
Stelian Pop6afcabf2008-02-07 16:37:54 +0000165
166 /* Wait for end hardware reset */
Stelian Pop983c1db2008-03-26 20:52:32 +0100167 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
Stelian Pop6afcabf2008-02-07 16:37:54 +0000168
Stelian Pop19bd6882008-05-22 00:15:40 +0200169 /* Restore NRST value */
170 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
171 (AT91_RSTC_ERSTL & (0x0 << 8)) |
172 AT91_RSTC_URSTEN);
173
Stelian Pop6afcabf2008-02-07 16:37:54 +0000174 /* Re-enable pull-up */
Stelian Pop983c1db2008-03-26 20:52:32 +0100175 writel(pin_to_mask(AT91_PIN_PB22) |
176 pin_to_mask(AT91_PIN_PB25) |
177 pin_to_mask(AT91_PIN_PB26),
178 pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
Stelian Pop6afcabf2008-02-07 16:37:54 +0000179
Jean-Christophe PLAGNIOL-VILLARDe2c04762009-03-21 21:08:00 +0100180 at91_macb_hw_init();
Stelian Pop983c1db2008-03-26 20:52:32 +0100181
Stelian Pop6afcabf2008-02-07 16:37:54 +0000182 /* Unlock EMAC, 3 0 2 1 sequence */
183#define MP_MAC_KEY0 0x5969cb2a
184#define MP_MAC_KEY1 0xb4a1872e
185#define MP_MAC_KEY2 0x05683fbc
186#define MP_MAC_KEY3 0x3634fba4
187#define UNLOCK_MAC 0x00000008
Stelian Pop983c1db2008-03-26 20:52:32 +0100188 writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
189 writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
190 writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
191 writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
192 writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
Stelian Pop6afcabf2008-02-07 16:37:54 +0000193}
194#endif
195
196#ifdef CONFIG_USB_OHCI_NEW
197static void at91cap9_uhp_hw_init(void)
198{
199 /* Unlock USB OHCI, 3 2 0 1 sequence */
200#define MP_OHCI_KEY0 0x896c11ca
201#define MP_OHCI_KEY1 0x68ebca21
202#define MP_OHCI_KEY2 0x4823efbc
203#define MP_OHCI_KEY3 0x8651aae4
204#define UNLOCK_OHCI 0x00000010
Stelian Pop983c1db2008-03-26 20:52:32 +0100205 writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
206 writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
207 writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
208 writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
209 writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
Stelian Pop6afcabf2008-02-07 16:37:54 +0000210}
211#endif
212
Stelian Popc139b172008-05-08 14:52:29 +0200213#ifdef CONFIG_LCD
214vidinfo_t panel_info = {
215 vl_col: 240,
216 vl_row: 320,
217 vl_clk: 4965000,
218 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
219 ATMEL_LCDC_INVFRAME_INVERTED,
220 vl_bpix: 3,
221 vl_tft: 1,
222 vl_hsync_len: 5,
223 vl_left_margin: 1,
224 vl_right_margin:33,
225 vl_vsync_len: 1,
226 vl_upper_margin:1,
227 vl_lower_margin:0,
228 mmio: AT91CAP9_LCDC_BASE,
229};
230
231void lcd_enable(void)
232{
233 at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
234}
235
236void lcd_disable(void)
237{
238 at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
239}
240
241static void at91cap9_lcd_hw_init(void)
242{
243 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
244 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
245 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
246 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
247 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
248 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
249 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
250 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
251 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
252 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
253 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
254 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
255 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
256 at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
257 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
258 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
259 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
260 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
261 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
262 at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
263 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
264 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
265
266 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
267
268 gd->fb_base = 0;
269}
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200270
271#ifdef CONFIG_LCD_INFO
272#include <nand.h>
273#include <version.h>
274
275void lcd_show_board_info(void)
276{
277 ulong dram_size, nand_size;
278 int i;
279 char temp[32];
280
281 lcd_printf ("%s\n", U_BOOT_VERSION);
282 lcd_printf ("(C) 2008 ATMEL Corp\n");
283 lcd_printf ("at91support@atmel.com\n");
284 lcd_printf ("%s CPU at %s MHz\n",
Achim Ehrlich7c966a82010-02-24 10:29:16 +0100285 CONFIG_SYS_AT91_CPU_NAME,
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +0200286 strmhz(temp, get_cpu_clk_rate()));
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200287
288 dram_size = 0;
289 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
290 dram_size += gd->bd->bi_dram[i].size;
291 nand_size = 0;
292 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
293 nand_size += nand_info[i].size;
294 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
295 dram_size >> 20,
296 nand_size >> 20 );
297}
298#endif /* CONFIG_LCD_INFO */
Stelian Popc139b172008-05-08 14:52:29 +0200299#endif
300
Stelian Pop6afcabf2008-02-07 16:37:54 +0000301int board_init(void)
302{
303 /* Enable Ctrlc */
304 console_init_f();
305
306 /* arch number of AT91CAP9ADK-Board */
307 gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
308 /* adress of boot parameters */
309 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
310
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +0100311 at91_serial_hw_init();
Stelian Pop19883ae2008-05-08 14:52:34 +0200312 at91cap9_slowclock_hw_init();
Stelian Pop6afcabf2008-02-07 16:37:54 +0000313 at91cap9_nor_hw_init();
314#ifdef CONFIG_CMD_NAND
315 at91cap9_nand_hw_init();
316#endif
317#ifdef CONFIG_HAS_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +0100318 at91_spi0_hw_init(1 << 0);
Stelian Pop6afcabf2008-02-07 16:37:54 +0000319#endif
320#ifdef CONFIG_MACB
321 at91cap9_macb_hw_init();
322#endif
323#ifdef CONFIG_USB_OHCI_NEW
324 at91cap9_uhp_hw_init();
325#endif
Stelian Popc139b172008-05-08 14:52:29 +0200326#ifdef CONFIG_LCD
327 at91cap9_lcd_hw_init();
328#endif
Stelian Pop6afcabf2008-02-07 16:37:54 +0000329 return 0;
330}
331
332int dram_init(void)
333{
334 gd->bd->bi_dram[0].start = PHYS_SDRAM;
335 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
336 return 0;
337}
338
339#ifdef CONFIG_RESET_PHY_R
340void reset_phy(void)
341{
Stelian Pop6afcabf2008-02-07 16:37:54 +0000342}
343#endif
Ben Warren3ae071e2008-08-12 22:11:53 -0700344
345int board_eth_init(bd_t *bis)
346{
347 int rc = 0;
348#ifdef CONFIG_MACB
Stelian Popd8003fa2008-11-07 13:54:31 +0100349 rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00);
Ben Warren3ae071e2008-08-12 22:11:53 -0700350#endif
351 return rc;
352}