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Jon Loeligerd9b94f22005-07-25 14:05:07 -05001/*
Kumar Gala8b47d7e2011-01-04 17:57:59 -06002 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
Jon Loeligerd9b94f22005-07-25 14:05:07 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Jon Loeligerd9b94f22005-07-25 14:05:07 -05005 */
6
7/*
8 * mpc8548cds board configuration file
9 *
10 * Please refer to doc/README.mpc85xxcds for more info.
11 *
12 */
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
York Sun9ae14ca2015-08-18 12:35:52 -070016#define CONFIG_DISPLAY_BOARDINFO
17
chenhui zhaob76aef62011-10-13 13:41:00 +080018#ifdef CONFIG_36BIT
19#define CONFIG_PHYS_64BIT
20#endif
21
Jon Loeligerd9b94f22005-07-25 14:05:07 -050022/* High Level Configuration Options */
23#define CONFIG_BOOKE 1 /* BOOKE */
24#define CONFIG_E500 1 /* BOOKE e500 family */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050025#define CONFIG_MPC8548 1 /* MPC8548 specific */
26#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
27
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028#ifndef CONFIG_SYS_TEXT_BASE
29#define CONFIG_SYS_TEXT_BASE 0xfff80000
30#endif
31
Kumar Gala8b47d7e2011-01-04 17:57:59 -060032#define CONFIG_SYS_SRIO
33#define CONFIG_SRIO1 /* SRIO port 1 */
34
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050035#define CONFIG_PCI /* enable any pci type devices */
36#define CONFIG_PCI1 /* PCI controller 1 */
37#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050038#undef CONFIG_PCI2
39#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000040#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala8ff3de62007-12-07 12:17:34 -060041#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050042#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050043
44#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050045#define CONFIG_ENV_OVERWRITE
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050046#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060047#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050048
Jon Loeliger25eedb22008-03-19 15:02:07 -050049#define CONFIG_FSL_VIA
Jon Loeliger25eedb22008-03-19 15:02:07 -050050
Jon Loeligerd9b94f22005-07-25 14:05:07 -050051#ifndef __ASSEMBLY__
52extern unsigned long get_clock_freq(void);
53#endif
54#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
55
56/*
57 * These can be toggled for performance analysis, otherwise use default.
58 */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050059#define CONFIG_L2_CACHE /* toggle L2 cache */
60#define CONFIG_BTB /* toggle branch predition */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050061
62/*
63 * Only possible on E500 Version 2 or newer cores.
64 */
65#define CONFIG_ENABLE_36BIT_PHYS 1
66
chenhui zhaob76aef62011-10-13 13:41:00 +080067#ifdef CONFIG_PHYS_64BIT
68#define CONFIG_ADDR_MAP
69#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
70#endif
71
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
73#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeligerd9b94f22005-07-25 14:05:07 -050074
Timur Tabie46fedf2011-08-04 18:03:41 -050075#define CONFIG_SYS_CCSRBAR 0xe0000000
76#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Jon Loeligerd9b94f22005-07-25 14:05:07 -050077
Jon Loeligere31d2c12008-03-18 13:51:06 -050078/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070079#define CONFIG_SYS_FSL_DDR2
Jon Loeligere31d2c12008-03-18 13:51:06 -050080#undef CONFIG_FSL_DDR_INTERACTIVE
81#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
82#define CONFIG_DDR_SPD
Jon Loeligere31d2c12008-03-18 13:51:06 -050083
chenhui zhao867b06f2011-09-06 16:41:19 +000084#define CONFIG_DDR_ECC
Dave Liu9b0ad1b2008-10-28 17:53:38 +080085#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Jon Loeligere31d2c12008-03-18 13:51:06 -050086#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
87
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
89#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Jon Loeligerd9b94f22005-07-25 14:05:07 -050090
Jon Loeligere31d2c12008-03-18 13:51:06 -050091#define CONFIG_NUM_DDR_CONTROLLERS 1
92#define CONFIG_DIMM_SLOTS_PER_CTLR 1
93#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeligerd9b94f22005-07-25 14:05:07 -050094
Jon Loeligere31d2c12008-03-18 13:51:06 -050095/* I2C addresses of SPD EEPROMs */
96#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
97
98/* Make sure required options are set */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050099#ifndef CONFIG_SPD_EEPROM
100#error ("CONFIG_SPD_EEPROM is required")
101#endif
102
103#undef CONFIG_CLOCKS_IN_MHZ
chenhui zhaofff80972011-10-13 13:40:59 +0800104/*
105 * Physical Address Map
106 *
107 * 32bit:
108 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
109 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
110 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
111 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
112 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
113 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
114 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
115 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
116 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
117 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
118 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
119 *
chenhui zhaob76aef62011-10-13 13:41:00 +0800120 * 36bit:
121 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
122 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
123 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
124 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
125 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
126 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
127 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
128 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
129 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
130 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
131 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
132 *
chenhui zhaofff80972011-10-13 13:40:59 +0800133 */
134
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500135
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500136/*
137 * Local Bus Definitions
138 */
139
140/*
141 * FLASH on the Local Bus
142 * Two banks, 8M each, using the CFI driver.
143 * Boot from BR0/OR0 bank at 0xff00_0000
144 * Alternate BR1/OR1 bank at 0xff80_0000
145 *
146 * BR0, BR1:
147 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
148 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
149 * Port Size = 16 bits = BRx[19:20] = 10
150 * Use GPCM = BRx[24:26] = 000
151 * Valid = BRx[31] = 1
152 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500153 * 0 4 8 12 16 20 24 28
154 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
155 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500156 *
157 * OR0, OR1:
158 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
159 * Reserved ORx[17:18] = 11, confusion here?
160 * CSNT = ORx[20] = 1
161 * ACS = half cycle delay = ORx[21:22] = 11
162 * SCY = 6 = ORx[24:27] = 0110
163 * TRLX = use relaxed timing = ORx[29] = 1
164 * EAD = use external address latch delay = OR[31] = 1
165 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500166 * 0 4 8 12 16 20 24 28
167 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500168 */
169
chenhui zhaofff80972011-10-13 13:40:59 +0800170#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
chenhui zhaob76aef62011-10-13 13:41:00 +0800171#ifdef CONFIG_PHYS_64BIT
172#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
173#else
chenhui zhaofff80972011-10-13 13:40:59 +0800174#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
chenhui zhaob76aef62011-10-13 13:41:00 +0800175#endif
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500176
chenhui zhaofff80972011-10-13 13:40:59 +0800177#define CONFIG_SYS_BR0_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000178 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
chenhui zhaofff80972011-10-13 13:40:59 +0800179#define CONFIG_SYS_BR1_PRELIM \
180 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_OR0_PRELIM 0xff806e65
183#define CONFIG_SYS_OR1_PRELIM 0xff806e65
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500184
chenhui zhaofff80972011-10-13 13:40:59 +0800185#define CONFIG_SYS_FLASH_BANKS_LIST \
186 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
188#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
189#undef CONFIG_SYS_FLASH_CHECKSUM
190#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
191#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500192
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200193#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500194
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200195#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_CFI
197#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500198
chenhui zhao867b06f2011-09-06 16:41:19 +0000199#define CONFIG_HWCONFIG /* enable hwconfig */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500200
201/*
202 * SDRAM on the Local Bus
203 */
chenhui zhaofff80972011-10-13 13:40:59 +0800204#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
chenhui zhaob76aef62011-10-13 13:41:00 +0800205#ifdef CONFIG_PHYS_64BIT
206#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
207#else
chenhui zhaofff80972011-10-13 13:40:59 +0800208#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
chenhui zhaob76aef62011-10-13 13:41:00 +0800209#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500211
212/*
213 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500215 *
216 * For BR2, need:
217 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
218 * port-size = 32-bits = BR2[19:20] = 11
219 * no parity checking = BR2[21:22] = 00
220 * SDRAM for MSEL = BR2[24:26] = 011
221 * Valid = BR[31] = 1
222 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500223 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500224 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
225 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500227 * FIXME: the top 17 bits of BR2.
228 */
229
chenhui zhaofff80972011-10-13 13:40:59 +0800230#define CONFIG_SYS_BR2_PRELIM \
231 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
232 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500233
234/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500236 *
237 * For OR2, need:
238 * 64MB mask for AM, OR2[0:7] = 1111 1100
239 * XAM, OR2[17:18] = 11
240 * 9 columns OR2[19-21] = 010
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500241 * 13 rows OR2[23-25] = 100
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500242 * EAD set for extra time OR[31] = 1
243 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500244 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500245 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
246 */
247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_OR2_PRELIM 0xfc006901
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
251#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
252#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
253#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500254
255/*
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500256 * Common settings for all Local Bus SDRAM commands.
257 * At run time, either BSMA1516 (for CPU 1.1)
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500258 * or BSMA1617 (for CPU 1.0) (old)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500259 * is OR'ed in too.
260 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500261#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
262 | LSDMR_PRETOACT7 \
263 | LSDMR_ACTTORW7 \
264 | LSDMR_BL8 \
265 | LSDMR_WRC4 \
266 | LSDMR_CL3 \
267 | LSDMR_RFEN \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500268 )
269
270/*
271 * The CADMUS registers are connected to CS3 on CDS.
272 * The new memory map places CADMUS at 0xf8000000.
273 *
274 * For BR3, need:
275 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
276 * port-size = 8-bits = BR[19:20] = 01
277 * no parity checking = BR[21:22] = 00
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500278 * GPMC for MSEL = BR[24:26] = 000
279 * Valid = BR[31] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500280 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500281 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500282 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
283 *
284 * For OR3, need:
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500285 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500286 * disable buffer ctrl OR[19] = 0
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500287 * CSNT OR[20] = 1
288 * ACS OR[21:22] = 11
289 * XACS OR[23] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500290 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500291 * SETA OR[28] = 0
292 * TRLX OR[29] = 1
293 * EHTR OR[30] = 1
294 * EAD extra time OR[31] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500295 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500296 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500297 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
298 */
299
Jon Loeliger25eedb22008-03-19 15:02:07 -0500300#define CONFIG_FSL_CADMUS
301
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500302#define CADMUS_BASE_ADDR 0xf8000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800303#ifdef CONFIG_PHYS_64BIT
304#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
305#else
chenhui zhaofff80972011-10-13 13:40:59 +0800306#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
chenhui zhaob76aef62011-10-13 13:41:00 +0800307#endif
chenhui zhaofff80972011-10-13 13:40:59 +0800308#define CONFIG_SYS_BR3_PRELIM \
309 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500311
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_INIT_RAM_LOCK 1
313#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200314#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500315
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200316#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500318
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
chenhui zhao867b06f2011-09-06 16:41:19 +0000320#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500321
322/* Serial Port */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500323#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_NS16550
325#define CONFIG_SYS_NS16550_SERIAL
326#define CONFIG_SYS_NS16550_REG_SIZE 1
327#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500330 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
333#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500334
335/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_HUSH_PARSER
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500337
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500338/* pass open firmware flat tree */
Kumar Galab90d2542007-11-29 00:11:44 -0600339#define CONFIG_OF_LIBFDT 1
340#define CONFIG_OF_BOARD_SETUP 1
341#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500342
Jon Loeliger20476722006-10-20 15:50:15 -0500343/*
344 * I2C
345 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200346#define CONFIG_SYS_I2C
347#define CONFIG_SYS_I2C_FSL
348#define CONFIG_SYS_FSL_I2C_SPEED 400000
349#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
350#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
351#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500352
Timur Tabie8d18542008-07-18 16:52:23 +0200353/* EEPROM */
354#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_I2C_EEPROM_CCID
356#define CONFIG_SYS_ID_EEPROM
357#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
358#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200359
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500360/*
361 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300362 * Memory space is mapped 1-1, but I/O space must start from 0.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500363 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600364#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800365#ifdef CONFIG_PHYS_64BIT
366#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
367#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
368#else
Kumar Gala10795f42008-12-02 16:08:36 -0600369#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600370#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800371#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600373#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600374#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800375#ifdef CONFIG_PHYS_64BIT
376#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
377#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800379#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500381
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500382#ifdef CONFIG_PCIE1
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600383#define CONFIG_SYS_PCIE1_NAME "Slot"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600384#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800385#ifdef CONFIG_PHYS_64BIT
386#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
387#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
388#else
Kumar Gala10795f42008-12-02 16:08:36 -0600389#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600390#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800391#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600393#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600394#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800395#ifdef CONFIG_PHYS_64BIT
396#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
397#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800399#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500401#endif
Zang Roy-r6191141fb7e02006-12-14 14:14:55 +0800402
403/*
404 * RapidIO MMU
405 */
chenhui zhaofff80972011-10-13 13:40:59 +0800406#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800407#ifdef CONFIG_PHYS_64BIT
408#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
409#else
chenhui zhaofff80972011-10-13 13:40:59 +0800410#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800411#endif
Kumar Gala8b47d7e2011-01-04 17:57:59 -0600412#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500413
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700414#ifdef CONFIG_LEGACY
415#define BRIDGE_ID 17
416#define VIA_ID 2
417#else
418#define BRIDGE_ID 28
419#define VIA_ID 4
420#endif
421
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500422#if defined(CONFIG_PCI)
423
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500424#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500425
426#undef CONFIG_EEPRO100
427#undef CONFIG_TULIP
428
chenhui zhao867b06f2011-09-06 16:41:19 +0000429#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500430
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500431#endif /* CONFIG_PCI */
432
433
434#if defined(CONFIG_TSEC_ENET)
435
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500436#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500437#define CONFIG_TSEC1 1
438#define CONFIG_TSEC1_NAME "eTSEC0"
439#define CONFIG_TSEC2 1
440#define CONFIG_TSEC2_NAME "eTSEC1"
441#define CONFIG_TSEC3 1
442#define CONFIG_TSEC3_NAME "eTSEC2"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500443#define CONFIG_TSEC4
Kim Phillips255a35772007-05-16 16:52:19 -0500444#define CONFIG_TSEC4_NAME "eTSEC3"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500445#undef CONFIG_MPC85XX_FEC
446
chenhui zhaod3701222011-09-06 16:41:18 +0000447#define CONFIG_PHY_MARVELL
448
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500449#define TSEC1_PHY_ADDR 0
450#define TSEC2_PHY_ADDR 1
451#define TSEC3_PHY_ADDR 2
452#define TSEC4_PHY_ADDR 3
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500453
454#define TSEC1_PHYIDX 0
455#define TSEC2_PHYIDX 0
456#define TSEC3_PHYIDX 0
457#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500458#define TSEC1_FLAGS TSEC_GIGABIT
459#define TSEC2_FLAGS TSEC_GIGABIT
460#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
461#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500462
463/* Options are: eTSEC[0-3] */
464#define CONFIG_ETHPRIME "eTSEC0"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500465#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500466#endif /* CONFIG_TSEC_ENET */
467
468/*
469 * Environment
470 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200471#define CONFIG_ENV_IS_IN_FLASH 1
chenhui zhao867b06f2011-09-06 16:41:19 +0000472#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
473#define CONFIG_ENV_ADDR 0xfff80000
474#else
475#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
476#endif
477#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200478#define CONFIG_ENV_SIZE 0x2000
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500479
480#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500482
Jon Loeliger2835e512007-06-13 13:22:08 -0500483/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500484 * BOOTP options
485 */
486#define CONFIG_BOOTP_BOOTFILESIZE
487#define CONFIG_BOOTP_BOOTPATH
488#define CONFIG_BOOTP_GATEWAY
489#define CONFIG_BOOTP_HOSTNAME
490
491
492/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500493 * Command line configuration.
494 */
Jon Loeliger2835e512007-06-13 13:22:08 -0500495#define CONFIG_CMD_PING
496#define CONFIG_CMD_I2C
497#define CONFIG_CMD_MII
Kumar Gala1c9aa762008-09-22 23:40:42 -0500498#define CONFIG_CMD_IRQ
Becky Bruce199e2622010-06-17 11:37:25 -0500499#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500500
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500501#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500502 #define CONFIG_CMD_PCI
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500503#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500504
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500505
506#undef CONFIG_WATCHDOG /* watchdog disabled */
507
508/*
509 * Miscellaneous configurable options
510 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500512#define CONFIG_CMDLINE_EDITING /* Command-line editing */
513#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeliger2835e512007-06-13 13:22:08 -0500515#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200516#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500517#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500519#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
521#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
522#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500523
524/*
525 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500526 * have to be in the first 64 MB of memory, since this is
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500527 * the maximum mapped by the Linux kernel during initialization.
528 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500529#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
530#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500531
Jon Loeliger2835e512007-06-13 13:22:08 -0500532#if defined(CONFIG_CMD_KGDB)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500533#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500534#endif
535
536/*
537 * Environment Configuration
538 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500539#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500540#define CONFIG_HAS_ETH0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500541#define CONFIG_HAS_ETH1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500542#define CONFIG_HAS_ETH2
Andy Fleming09f3e092006-09-13 10:34:18 -0500543#define CONFIG_HAS_ETH3
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500544#endif
545
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500546#define CONFIG_IPADDR 192.168.1.253
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500547
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500548#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000549#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000550#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500551#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500552
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500553#define CONFIG_SERVERIP 192.168.1.1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500554#define CONFIG_GATEWAYIP 192.168.1.1
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500555#define CONFIG_NETMASK 255.255.255.0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500556
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500557#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500558
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500559#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
560#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500561
562#define CONFIG_BAUDRATE 115200
563
chenhui zhao867b06f2011-09-06 16:41:19 +0000564#define CONFIG_EXTRA_ENV_SETTINGS \
565 "hwconfig=fsl_ddr:ecc=off\0" \
566 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200567 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
chenhui zhao867b06f2011-09-06 16:41:19 +0000568 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200569 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
570 " +$filesize; " \
571 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
572 " +$filesize; " \
573 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
574 " $filesize; " \
575 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
576 " +$filesize; " \
577 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
578 " $filesize\0" \
chenhui zhao867b06f2011-09-06 16:41:19 +0000579 "consoledev=ttyS1\0" \
580 "ramdiskaddr=2000000\0" \
581 "ramdiskfile=ramdisk.uboot\0" \
582 "fdtaddr=c00000\0" \
583 "fdtfile=mpc8548cds.dtb\0"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500584
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500585#define CONFIG_NFSBOOTCOMMAND \
586 "setenv bootargs root=/dev/nfs rw " \
587 "nfsroot=$serverip:$rootpath " \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500588 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500589 "console=$consoledev,$baudrate $othbootargs;" \
590 "tftp $loadaddr $bootfile;" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500591 "tftp $fdtaddr $fdtfile;" \
592 "bootm $loadaddr - $fdtaddr"
Andy Fleming8272dc22006-09-13 10:33:35 -0500593
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500594
595#define CONFIG_RAMBOOTCOMMAND \
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500596 "setenv bootargs root=/dev/ram rw " \
597 "console=$consoledev,$baudrate $othbootargs;" \
598 "tftp $ramdiskaddr $ramdiskfile;" \
599 "tftp $loadaddr $bootfile;" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500600 "tftp $fdtaddr $fdtfile;" \
601 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500602
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500603#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500604
605#endif /* __CONFIG_H */