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Stefan Roese887e2ec2006-09-07 11:51:23 +02001/*
Stefan Roese5a5958b2007-10-15 11:29:33 +02002 * (C) Copyright 2006-2007
Stefan Roese887e2ec2006-09-07 11:51:23 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
Wolfgang Denk865f0f92008-01-23 14:31:17 +01007 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
Stefan Roese887e2ec2006-09-07 11:51:23 +02008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
Stefan Roese13628882007-12-13 14:52:53 +010026#include <libfdt.h>
27#include <fdt_support.h>
Stefan Roese4fb25a32008-06-25 10:59:22 +020028#include <ppc4xx.h>
Lawrence R. Johnsonb05e8bf2008-01-04 02:11:56 -050029#include <asm/gpio.h>
Stefan Roese887e2ec2006-09-07 11:51:23 +020030#include <asm/processor.h>
Stefan Roese5a5958b2007-10-15 11:29:33 +020031#include <asm/io.h>
Matthias Fuchs83a49c82008-01-16 10:33:46 +010032#include <asm/bitops.h>
Stefan Roese887e2ec2006-09-07 11:51:23 +020033
34DECLARE_GLOBAL_DATA_PTR;
35
Matthias Fuchs83a49c82008-01-16 10:33:46 +010036extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
Stefan Roese887e2ec2006-09-07 11:51:23 +020037
Stefan Roese1b3c3602006-12-22 14:29:40 +010038ulong flash_get_size (ulong base, int banknum);
39
Stefan Roese887e2ec2006-09-07 11:51:23 +020040int board_early_init_f(void)
41{
Stefan Roesea78bc442007-01-05 10:40:36 +010042 u32 sdr0_cust0;
43 u32 sdr0_pfc1, sdr0_pfc2;
44 u32 reg;
Stefan Roese887e2ec2006-09-07 11:51:23 +020045
46 mtdcr(ebccfga, xbcfg);
47 mtdcr(ebccfgd, 0xb8400000);
48
Matthias Fuchs83a49c82008-01-16 10:33:46 +010049 /*
Stefan Roese887e2ec2006-09-07 11:51:23 +020050 * Setup the interrupt controller polarities, triggers, etc.
Matthias Fuchs83a49c82008-01-16 10:33:46 +010051 */
Stefan Roese887e2ec2006-09-07 11:51:23 +020052 mtdcr(uic0sr, 0xffffffff); /* clear all */
53 mtdcr(uic0er, 0x00000000); /* disable all */
54 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
55 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
56 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
57 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
58 mtdcr(uic0sr, 0xffffffff); /* clear all */
59
60 mtdcr(uic1sr, 0xffffffff); /* clear all */
61 mtdcr(uic1er, 0x00000000); /* disable all */
62 mtdcr(uic1cr, 0x00000000); /* all non-critical */
63 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
64 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
65 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
66 mtdcr(uic1sr, 0xffffffff); /* clear all */
67
68 mtdcr(uic2sr, 0xffffffff); /* clear all */
69 mtdcr(uic2er, 0x00000000); /* disable all */
70 mtdcr(uic2cr, 0x00000000); /* all non-critical */
71 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
72 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
73 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
74 mtdcr(uic2sr, 0xffffffff); /* clear all */
75
76 /* 50MHz tmrclk */
Larry Johnsond3471172007-12-22 15:34:39 -050077 out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
Stefan Roese887e2ec2006-09-07 11:51:23 +020078
79 /* clear write protects */
Larry Johnsond3471172007-12-22 15:34:39 -050080 out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
Stefan Roese887e2ec2006-09-07 11:51:23 +020081
82 /* enable Ethernet */
Larry Johnsond3471172007-12-22 15:34:39 -050083 out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
Stefan Roese887e2ec2006-09-07 11:51:23 +020084
85 /* enable USB device */
Larry Johnsond3471172007-12-22 15:34:39 -050086 out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
Stefan Roese887e2ec2006-09-07 11:51:23 +020087
Mike Nussb7386542008-02-06 11:10:11 -050088 /* select Ethernet (and optionally IIC1) pins */
Stefan Roese887e2ec2006-09-07 11:51:23 +020089 mfsdr(SDR0_PFC1, sdr0_pfc1);
Matthias Fuchs83a49c82008-01-16 10:33:46 +010090 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
91 SDR0_PFC1_SELECT_CONFIG_4;
Mike Nussb7386542008-02-06 11:10:11 -050092#ifdef CONFIG_I2C_MULTI_BUS
93 sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
94#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +020095 mfsdr(SDR0_PFC2, sdr0_pfc2);
Matthias Fuchs83a49c82008-01-16 10:33:46 +010096 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
97 SDR0_PFC2_SELECT_CONFIG_4;
Stefan Roese887e2ec2006-09-07 11:51:23 +020098 mtsdr(SDR0_PFC2, sdr0_pfc2);
99 mtsdr(SDR0_PFC1, sdr0_pfc1);
100
101 /* PCI arbiter enabled */
102 mfsdr(sdr_pci0, reg);
103 mtsdr(sdr_pci0, 0x80000000 | reg);
104
105 /* setup NAND FLASH */
106 mfsdr(SDR0_CUST0, sdr0_cust0);
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200107 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
Stefan Roese887e2ec2006-09-07 11:51:23 +0200108 SDR0_CUST0_NDFC_ENABLE |
109 SDR0_CUST0_NDFC_BW_8_BIT |
110 SDR0_CUST0_NDFC_ARE_MASK |
111 (0x80000000 >> (28 + CFG_NAND_CS));
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200112 mtsdr(SDR0_CUST0, sdr0_cust0);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200113
114 return 0;
115}
116
Stefan Roese887e2ec2006-09-07 11:51:23 +0200117int misc_init_r(void)
118{
119 uint pbcr;
120 int size_val = 0;
Stefan Roesea78bc442007-01-05 10:40:36 +0100121 u32 reg;
Stefan Roese854bc8d2006-09-13 13:51:58 +0200122#ifdef CONFIG_440EPX
Stefan Roese887e2ec2006-09-07 11:51:23 +0200123 unsigned long usb2d0cr = 0;
124 unsigned long usb2phy0cr, usb2h0cr = 0;
125 unsigned long sdr0_pfc1;
126 char *act = getenv("usbact");
Stefan Roese854bc8d2006-09-13 13:51:58 +0200127#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200128
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100129 /* Re-do flash sizing to get full correct info */
Stefan Roese1b3c3602006-12-22 14:29:40 +0100130
131 /* adjust flash start and offset */
132 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
133 gd->bd->bi_flashoffset = 0;
134
Stefan Roese887e2ec2006-09-07 11:51:23 +0200135#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
136 mtdcr(ebccfga, pb3cr);
137#else
138 mtdcr(ebccfga, pb0cr);
139#endif
140 pbcr = mfdcr(ebccfgd);
Wolfgang Denk865f0f92008-01-23 14:31:17 +0100141 size_val = ffs(gd->bd->bi_flashsize) - 21;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200142 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
143#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
144 mtdcr(ebccfga, pb3cr);
145#else
146 mtdcr(ebccfga, pb0cr);
147#endif
148 mtdcr(ebccfgd, pbcr);
149
Stefan Roese1b3c3602006-12-22 14:29:40 +0100150 /*
151 * Re-check to get correct base address
152 */
153 flash_get_size(gd->bd->bi_flashstart, 0);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200154
155#ifdef CFG_ENV_IS_IN_FLASH
156 /* Monitor protection ON by default */
157 (void)flash_protect(FLAG_PROTECT_SET,
158 -CFG_MONITOR_LEN,
159 0xffffffff,
160 &flash_info[0]);
161
162 /* Env protection ON by default */
163 (void)flash_protect(FLAG_PROTECT_SET,
164 CFG_ENV_ADDR_REDUND,
165 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
166 &flash_info[0]);
167#endif
168
169 /*
170 * USB suff...
171 */
Stefan Roese854bc8d2006-09-13 13:51:58 +0200172#ifdef CONFIG_440EPX
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100173 if (act == NULL || strcmp(act, "hostdev") == 0) {
Stefan Roese887e2ec2006-09-07 11:51:23 +0200174 /* SDR Setting */
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200175 mfsdr(SDR0_PFC1, sdr0_pfc1);
Niklaus Gigerf780b832007-06-27 18:11:38 +0200176 mfsdr(SDR0_USB2D0CR, usb2d0cr);
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200177 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
178 mfsdr(SDR0_USB2H0CR, usb2h0cr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200179
180 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100181 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200182 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100183 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200184 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100185 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200186 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100187 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200188 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100189 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200190
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100191 /*
192 * An 8-bit/60MHz interface is the only possible alternative
193 * when connecting the Device to the PHY
194 */
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200195 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100196 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200197
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100198 /*
199 * To enable the USB 2.0 Device function
200 * through the UTMI interface
201 */
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200202 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100203 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200204
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200205 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100206 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200207
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200208 mtsdr(SDR0_PFC1, sdr0_pfc1);
Niklaus Gigerf780b832007-06-27 18:11:38 +0200209 mtsdr(SDR0_USB2D0CR, usb2d0cr);
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200210 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
211 mtsdr(SDR0_USB2H0CR, usb2h0cr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200212
213 /*clear resets*/
214 udelay (1000);
215 mtsdr(SDR0_SRST1, 0x00000000);
216 udelay (1000);
217 mtsdr(SDR0_SRST0, 0x00000000);
218
219 printf("USB: Host(int phy) Device(ext phy)\n");
220
221 } else if (strcmp(act, "dev") == 0) {
222 /*-------------------PATCH-------------------------------*/
223 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
224
225 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100226 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200227 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100228 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200229 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100230 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200231 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100232 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200233 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
234
235 udelay (1000);
236 mtsdr(SDR0_SRST1, 0x672c6000);
237
238 udelay (1000);
239 mtsdr(SDR0_SRST0, 0x00000080);
240
241 udelay (1000);
242 mtsdr(SDR0_SRST1, 0x60206000);
243
244 *(unsigned int *)(0xe0000350) = 0x00000001;
245
246 udelay (1000);
247 mtsdr(SDR0_SRST1, 0x60306000);
248 /*-------------------PATCH-------------------------------*/
249
250 /* SDR Setting */
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200251 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200252 mfsdr(SDR0_USB2H0CR, usb2h0cr);
Niklaus Gigerf780b832007-06-27 18:11:38 +0200253 mfsdr(SDR0_USB2D0CR, usb2d0cr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200254 mfsdr(SDR0_PFC1, sdr0_pfc1);
255
256 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100257 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200258 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100259 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200260 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100261 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200262 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100263 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200264 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100265 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200266
267 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100268 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200269
270 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100271 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200272
273 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100274 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200275
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200276 mtsdr(SDR0_USB2H0CR, usb2h0cr);
277 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
Niklaus Gigerf780b832007-06-27 18:11:38 +0200278 mtsdr(SDR0_USB2D0CR, usb2d0cr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200279 mtsdr(SDR0_PFC1, sdr0_pfc1);
280
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100281 /* clear resets */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200282 udelay (1000);
283 mtsdr(SDR0_SRST1, 0x00000000);
284 udelay (1000);
285 mtsdr(SDR0_SRST0, 0x00000000);
286
287 printf("USB: Device(int phy)\n");
288 }
Stefan Roese854bc8d2006-09-13 13:51:58 +0200289#endif /* CONFIG_440EPX */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200290
John Otken john@softadvances.com8ce16f52007-03-08 09:39:48 -0600291 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
292 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
293 mtsdr(SDR0_SRST1, reg);
294
Stefan Roesea78bc442007-01-05 10:40:36 +0100295 /*
296 * Clear PLB4A0_ACR[WRP]
297 * This fix will make the MAL burst disabling patch for the Linux
298 * EMAC driver obsolete.
299 */
300 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
301 mtdcr(plb4_acr, reg);
302
Stefan Roese887e2ec2006-09-07 11:51:23 +0200303 return 0;
304}
305
306int checkboard(void)
307{
308 char *s = getenv("serial#");
Stefan Roesee0b9ea82007-01-13 07:57:51 +0100309 u8 rev;
310 u8 val;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200311
Stefan Roese854bc8d2006-09-13 13:51:58 +0200312#ifdef CONFIG_440EPX
Stefan Roese887e2ec2006-09-07 11:51:23 +0200313 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
Stefan Roese854bc8d2006-09-13 13:51:58 +0200314#else
315 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
316#endif
Stefan Roesee0b9ea82007-01-13 07:57:51 +0100317
Stefan Roese5a5958b2007-10-15 11:29:33 +0200318 rev = in_8((void *)(CFG_BCSR_BASE + 0));
319 val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
Stefan Roesee0b9ea82007-01-13 07:57:51 +0100320 printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
321
Stefan Roese887e2ec2006-09-07 11:51:23 +0200322 if (s != NULL) {
323 puts(", serial# ");
324 puts(s);
325 }
326 putc('\n');
327
328 return (0);
329}
330
Matthias Fuchs1f840212008-01-08 15:40:09 +0100331#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
332/*
333 * Assign interrupts to PCI devices.
334 */
335void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
336{
337 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
338}
339#endif
340
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100341/*
342 * pci_pre_init
Stefan Roese887e2ec2006-09-07 11:51:23 +0200343 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100344 * This routine is called just prior to registering the hose and gives
345 * the board the opportunity to check things. Returning a value of zero
346 * indicates that things are bad & PCI initialization should be aborted.
Stefan Roese887e2ec2006-09-07 11:51:23 +0200347 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100348 * Different boards may wish to customize the pci controller structure
349 * (add regions, override default access routines, etc) or perform
350 * certain pre-initialization actions.
351 */
Stefan Roese466fff12007-06-25 15:57:39 +0200352#if defined(CONFIG_PCI)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200353int pci_pre_init(struct pci_controller *hose)
354{
355 unsigned long addr;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200356
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100357 /*
358 * Set priority for all PLB3 devices to 0.
359 * Set PLB3 arbiter to fair mode.
360 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200361 mfsdr(sdr_amp1, addr);
362 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
363 addr = mfdcr(plb3_acr);
364 mtdcr(plb3_acr, addr | 0x80000000);
365
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100366 /*
367 * Set priority for all PLB4 devices to 0.
368 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200369 mfsdr(sdr_amp0, addr);
370 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
371 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
372 mtdcr(plb4_acr, addr);
373
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100374 /*
375 * Set Nebula PLB4 arbiter to fair mode.
376 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200377 /* Segment0 */
378 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
379 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
380 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
381 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
382 mtdcr(plb0_acr, addr);
383
384 /* Segment1 */
385 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
386 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
387 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
388 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
389 mtdcr(plb1_acr, addr);
390
Matthias Fuchs1f840212008-01-08 15:40:09 +0100391#ifdef CONFIG_PCI_PNP
392 hose->fixup_irq = sequoia_pci_fixup_irq;
393#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200394 return 1;
395}
Stefan Roese466fff12007-06-25 15:57:39 +0200396#endif /* defined(CONFIG_PCI) */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200397
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100398/*
399 * pci_target_init
Stefan Roese887e2ec2006-09-07 11:51:23 +0200400 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100401 * The bootstrap configuration provides default settings for the pci
402 * inbound map (PIM). But the bootstrap config choices are limited and
403 * may not be sufficient for a given board.
404 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200405#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
406void pci_target_init(struct pci_controller *hose)
407{
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100408 /*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200409 * Set up Direct MMIO registers
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100410 */
411 /*
412 * PowerPC440EPX PCI Master configuration.
413 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
414 * PLB address 0xA0000000-0xDFFFFFFF
415 * ==> PCI address 0xA0000000-0xDFFFFFFF
416 * Use byte reversed out routines to handle endianess.
417 * Make this region non-prefetchable.
418 */
419 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
420 /* - disabled b4 setting */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200421 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100422 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200423 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100424 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
425 /* and enable region */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200426
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100427 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
428 /* - disabled b4 setting */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200429 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100430 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200431 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100432 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
433 /* and enable region */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200434
435 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100436 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
437 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
438 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200439
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100440 /*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200441 * Set up Configuration registers
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100442 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200443
444 /* Program the board's subsystem id/vendor id */
445 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
446 CFG_PCI_SUBSYS_VENDORID);
447 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
448
449 /* Configure command register as bus master */
450 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
451
452 /* 240nS PCI clock */
453 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
454
455 /* No error reporting */
456 pci_write_config_word(0, PCI_ERREN, 0);
457
458 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
459
460}
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100461#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200462
Stefan Roese887e2ec2006-09-07 11:51:23 +0200463#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
464void pci_master_init(struct pci_controller *hose)
465{
466 unsigned short temp_short;
467
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100468 /*
469 * Write the PowerPC440 EP PCI Configuration regs.
470 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
471 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
472 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200473 pci_read_config_word(0, PCI_COMMAND, &temp_short);
474 pci_write_config_word(0, PCI_COMMAND,
475 temp_short | PCI_COMMAND_MASTER |
476 PCI_COMMAND_MEMORY);
477}
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100478#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200479
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100480/*
481 * is_pci_host
Stefan Roese887e2ec2006-09-07 11:51:23 +0200482 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100483 * This routine is called to determine if a pci scan should be
484 * performed. With various hardware environments (especially cPCI and
485 * PPMC) it's insufficient to depend on the state of the arbiter enable
486 * bit in the strap register, or generic host/adapter assumptions.
Stefan Roese887e2ec2006-09-07 11:51:23 +0200487 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100488 * Rather than hard-code a bad assumption in the general 440 code, the
489 * 440 pci code requires the board to decide at runtime.
Stefan Roese887e2ec2006-09-07 11:51:23 +0200490 *
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100491 * Return 0 for adapter mode, non-zero for host (monarch) mode.
492 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200493#if defined(CONFIG_PCI)
494int is_pci_host(struct pci_controller *hose)
495{
496 /* Cactus is always configured as host. */
497 return (1);
498}
Matthias Fuchs83a49c82008-01-16 10:33:46 +0100499#endif /* defined(CONFIG_PCI) */
500
Igor Lisitsina11e0692007-03-28 19:06:19 +0400501#if defined(CONFIG_POST)
502/*
503 * Returns 1 if keys pressed to start the power-on long-running tests
504 * Called from board_init_f().
505 */
506int post_hotkeys_pressed(void)
507{
508 return 0; /* No hotkeys supported */
509}
510#endif /* CONFIG_POST */