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wdenkfe8c2802002-11-03 00:38:21 +00001/*------------------------------------------------------------------------
2 . smc91111.c
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
4 .
5 . (C) Copyright 2002
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
8 .
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
wdenk42dfe7a2004-03-14 22:25:36 +000010 . Developed by Simple Network Magic Corporation (SNMC)
wdenkfe8c2802002-11-03 00:38:21 +000011 . Copyright (C) 1996 by Erik Stahlman (ES)
12 .
Wolfgang Denk1a459662013-07-08 09:37:19 +020013 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +000014 .
15 . Information contained in this file was obtained from the LAN91C111
16 . manual from SMC. To get a copy, if you really want one, you can find
17 . information under www.smsc.com.
18 .
19 .
20 . "Features" of the SMC chip:
21 . Integrated PHY/MAC for 10/100BaseT Operation
22 . Supports internal and external MII
23 . Integrated 8K packet memory
24 . EEPROM interface for configuration
25 .
26 . Arguments:
wdenk42dfe7a2004-03-14 22:25:36 +000027 . io = for the base address
wdenkfe8c2802002-11-03 00:38:21 +000028 . irq = for the IRQ
29 .
30 . author:
wdenk42dfe7a2004-03-14 22:25:36 +000031 . Erik Stahlman ( erik@vt.edu )
32 . Daris A Nevil ( dnevil@snmc.com )
wdenkfe8c2802002-11-03 00:38:21 +000033 .
34 .
35 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
36 .
37 . Sources:
wdenk42dfe7a2004-03-14 22:25:36 +000038 . o SMSC LAN91C111 databook (www.smsc.com)
39 . o smc9194.c by Erik Stahlman
40 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
wdenkfe8c2802002-11-03 00:38:21 +000041 .
42 . History:
wdenk42dfe7a2004-03-14 22:25:36 +000043 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
wdenkfe8c2802002-11-03 00:38:21 +000044 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
wdenk42dfe7a2004-03-14 22:25:36 +000045 . 07/25/01 Woojung Huh Modify for ADS Bitsy
46 . 04/25/01 Daris A Nevil Initial public release through SMSC
47 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
wdenkfe8c2802002-11-03 00:38:21 +000048 ----------------------------------------------------------------------------*/
49
50#include <common.h>
51#include <command.h>
wdenkf39748a2004-06-09 13:37:52 +000052#include <config.h>
Ben Warren7194ab82009-10-04 22:37:03 -070053#include <malloc.h>
wdenkfe8c2802002-11-03 00:38:21 +000054#include "smc91111.h"
55#include <net.h>
56
wdenkfe8c2802002-11-03 00:38:21 +000057/* Use power-down feature of the chip */
58#define POWER_DOWN 0
59
60#define NO_AUTOPROBE
61
Wolfgang Denk0be248f2006-03-07 00:22:36 +010062#define SMC_DEBUG 0
wdenk8bf3b002003-12-06 23:20:41 +000063
64#if SMC_DEBUG > 1
wdenkfe8c2802002-11-03 00:38:21 +000065static const char version[] =
66 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
wdenk8bf3b002003-12-06 23:20:41 +000067#endif
wdenkfe8c2802002-11-03 00:38:21 +000068
wdenkf39748a2004-06-09 13:37:52 +000069/* Autonegotiation timeout in seconds */
70#ifndef CONFIG_SMC_AUTONEG_TIMEOUT
71#define CONFIG_SMC_AUTONEG_TIMEOUT 10
72#endif
73
wdenkfe8c2802002-11-03 00:38:21 +000074/*------------------------------------------------------------------------
75 .
76 . Configuration options, for the experienced user to change.
77 .
78 -------------------------------------------------------------------------*/
79
80/*
81 . Wait time for memory to be free. This probably shouldn't be
82 . tuned that much, as waiting for this means nothing else happens
83 . in the system
84*/
85#define MEMORY_WAIT_TIME 16
86
87
88#if (SMC_DEBUG > 2 )
89#define PRINTK3(args...) printf(args)
90#else
91#define PRINTK3(args...)
92#endif
93
94#if SMC_DEBUG > 1
95#define PRINTK2(args...) printf(args)
96#else
97#define PRINTK2(args...)
98#endif
99
100#ifdef SMC_DEBUG
101#define PRINTK(args...) printf(args)
102#else
103#define PRINTK(args...)
104#endif
105
106
107/*------------------------------------------------------------------------
108 .
wdenk42dfe7a2004-03-14 22:25:36 +0000109 . The internal workings of the driver. If you are changing anything
wdenkfe8c2802002-11-03 00:38:21 +0000110 . here with the SMC stuff, you should have the datasheet and know
111 . what you are doing.
112 .
113 -------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000114
115/* Memory sizing constant */
116#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
117
118#ifndef CONFIG_SMC91111_BASE
Ben Warren7194ab82009-10-04 22:37:03 -0700119#error "SMC91111 Base address must be passed to initialization funciton"
120/* #define CONFIG_SMC91111_BASE 0x20000300 */
wdenkfe8c2802002-11-03 00:38:21 +0000121#endif
122
wdenkfe8c2802002-11-03 00:38:21 +0000123#define SMC_DEV_NAME "SMC91111"
124#define SMC_PHY_ADDR 0x0000
125#define SMC_ALLOC_MAX_TRY 5
126#define SMC_TX_TIMEOUT 30
127
128#define SMC_PHY_CLOCK_DELAY 1000
129
130#define ETH_ZLEN 60
131
wdenk42dfe7a2004-03-14 22:25:36 +0000132#ifdef CONFIG_SMC_USE_32_BIT
wdenkfe8c2802002-11-03 00:38:21 +0000133#define USE_32_BIT 1
134#else
135#undef USE_32_BIT
136#endif
wdenkfe8c2802002-11-03 00:38:21 +0000137
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100138#ifdef SHARED_RESOURCES
Ben Warren7194ab82009-10-04 22:37:03 -0700139extern void swap_to(int device_id);
140#else
141# define swap_to(x)
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100142#endif
wdenkfe8c2802002-11-03 00:38:21 +0000143
wdenkfe8c2802002-11-03 00:38:21 +0000144#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700145static void smc_phy_configure(struct eth_device *dev);
wdenkfe8c2802002-11-03 00:38:21 +0000146#endif /* !CONFIG_SMC91111_EXT_PHY */
147
148/*
wdenkfe8c2802002-11-03 00:38:21 +0000149 ------------------------------------------------------------
150 .
151 . Internal routines
152 .
153 ------------------------------------------------------------
154*/
155
wdenkc3c7f862004-06-09 14:47:54 +0000156#ifdef CONFIG_SMC_USE_IOFUNCS
157/*
158 * input and output functions
159 *
160 * Implemented due to inx,outx macros accessing the device improperly
161 * and putting the device into an unkown state.
162 *
163 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
164 * could not be free'd (hence the alloc failures), duplicate packets,
165 * packets being corrupt (shifted) on the wire, etc. Switching to the
166 * inx,outx functions fixed this problem.
167 */
wdenkc3c7f862004-06-09 14:47:54 +0000168
Ben Warren7194ab82009-10-04 22:37:03 -0700169static inline word SMC_inw(struct eth_device *dev, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000170{
171 word v;
Ben Warren7194ab82009-10-04 22:37:03 -0700172 v = *((volatile word*)(dev->iobase + offset));
wdenkc3c7f862004-06-09 14:47:54 +0000173 barrier(); *(volatile u32*)(0xc0000000);
174 return v;
175}
176
Ben Warren7194ab82009-10-04 22:37:03 -0700177static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000178{
Ben Warren7194ab82009-10-04 22:37:03 -0700179 *((volatile word*)(dev->iobase + offset)) = value;
wdenkc3c7f862004-06-09 14:47:54 +0000180 barrier(); *(volatile u32*)(0xc0000000);
181}
182
Ben Warren7194ab82009-10-04 22:37:03 -0700183static inline byte SMC_inb(struct eth_device *dev, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000184{
185 word _w;
186
Ben Warren7194ab82009-10-04 22:37:03 -0700187 _w = SMC_inw(dev, offset & ~((dword)1));
wdenkc3c7f862004-06-09 14:47:54 +0000188 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
189}
190
Ben Warren7194ab82009-10-04 22:37:03 -0700191static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000192{
193 word _w;
194
Ben Warren7194ab82009-10-04 22:37:03 -0700195 _w = SMC_inw(dev, offset & ~((dword)1));
wdenkc3c7f862004-06-09 14:47:54 +0000196 if (offset & 1)
Ben Warren7194ab82009-10-04 22:37:03 -0700197 *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
198 (value<<8) | (_w & 0x00ff);
wdenkc3c7f862004-06-09 14:47:54 +0000199 else
Ben Warren7194ab82009-10-04 22:37:03 -0700200 *((volatile word*)(dev->iobase + offset)) =
201 value | (_w & 0xff00);
wdenkc3c7f862004-06-09 14:47:54 +0000202}
203
Ben Warren7194ab82009-10-04 22:37:03 -0700204static inline void SMC_insw(struct eth_device *dev, dword offset,
205 volatile uchar* buf, dword len)
wdenkc3c7f862004-06-09 14:47:54 +0000206{
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100207 volatile word *p = (volatile word *)buf;
208
wdenkc3c7f862004-06-09 14:47:54 +0000209 while (len-- > 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700210 *p++ = SMC_inw(dev, offset);
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100211 barrier();
212 *((volatile u32*)(0xc0000000));
wdenkc3c7f862004-06-09 14:47:54 +0000213 }
214}
215
Ben Warren7194ab82009-10-04 22:37:03 -0700216static inline void SMC_outsw(struct eth_device *dev, dword offset,
217 uchar* buf, dword len)
wdenkc3c7f862004-06-09 14:47:54 +0000218{
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100219 volatile word *p = (volatile word *)buf;
220
wdenkc3c7f862004-06-09 14:47:54 +0000221 while (len-- > 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700222 SMC_outw(dev, *p++, offset);
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100223 barrier();
224 *(volatile u32*)(0xc0000000);
wdenkc3c7f862004-06-09 14:47:54 +0000225 }
226}
227#endif /* CONFIG_SMC_USE_IOFUNCS */
228
wdenkfe8c2802002-11-03 00:38:21 +0000229/*
230 . A rather simple routine to print out a packet for debugging purposes.
231*/
232#if SMC_DEBUG > 2
233static void print_packet( byte *, int );
234#endif
235
236#define tx_done(dev) 1
237
Ben Warren7194ab82009-10-04 22:37:03 -0700238static int poll4int (struct eth_device *dev, byte mask, int timeout)
wdenkb56ddc62003-09-15 21:14:37 +0000239{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240 int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
wdenkb56ddc62003-09-15 21:14:37 +0000241 int is_timeout = 0;
Ben Warren7194ab82009-10-04 22:37:03 -0700242 word old_bank = SMC_inw (dev, BSR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000243
wdenkb56ddc62003-09-15 21:14:37 +0000244 PRINTK2 ("Polling...\n");
Ben Warren7194ab82009-10-04 22:37:03 -0700245 SMC_SELECT_BANK (dev, 2);
246 while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
wdenkb56ddc62003-09-15 21:14:37 +0000247 if (get_timer (0) >= tmo) {
248 is_timeout = 1;
249 break;
250 }
wdenkfe8c2802002-11-03 00:38:21 +0000251 }
wdenkfe8c2802002-11-03 00:38:21 +0000252
wdenkb56ddc62003-09-15 21:14:37 +0000253 /* restore old bank selection */
Ben Warren7194ab82009-10-04 22:37:03 -0700254 SMC_SELECT_BANK (dev, old_bank);
wdenkfe8c2802002-11-03 00:38:21 +0000255
wdenkb56ddc62003-09-15 21:14:37 +0000256 if (is_timeout)
257 return 1;
258 else
259 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000260}
261
wdenk487778b2003-06-06 11:20:01 +0000262/* Only one release command at a time, please */
Ben Warren7194ab82009-10-04 22:37:03 -0700263static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
wdenk487778b2003-06-06 11:20:01 +0000264{
265 int count = 0;
wdenkb56ddc62003-09-15 21:14:37 +0000266
wdenk487778b2003-06-06 11:20:01 +0000267 /* assume bank 2 selected */
Ben Warren7194ab82009-10-04 22:37:03 -0700268 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
wdenkb56ddc62003-09-15 21:14:37 +0000269 udelay (1); /* Wait until not busy */
270 if (++count > 200)
271 break;
wdenk487778b2003-06-06 11:20:01 +0000272 }
273}
274
wdenkfe8c2802002-11-03 00:38:21 +0000275/*
276 . Function: smc_reset( void )
277 . Purpose:
wdenk42dfe7a2004-03-14 22:25:36 +0000278 . This sets the SMC91111 chip to its normal state, hopefully from whatever
279 . mess that any other DOS driver has put it in.
wdenkfe8c2802002-11-03 00:38:21 +0000280 .
281 . Maybe I should reset more registers to defaults in here? SOFTRST should
282 . do that for me.
283 .
284 . Method:
285 . 1. send a SOFT RESET
286 . 2. wait for it to finish
287 . 3. enable autorelease mode
288 . 4. reset the memory management unit
289 . 5. clear all interrupts
290 .
291*/
Ben Warren7194ab82009-10-04 22:37:03 -0700292static void smc_reset (struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000293{
wdenkf39748a2004-06-09 13:37:52 +0000294 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000295
296 /* This resets the registers mostly to defaults, but doesn't
297 affect EEPROM. That seems unnecessary */
Ben Warren7194ab82009-10-04 22:37:03 -0700298 SMC_SELECT_BANK (dev, 0);
299 SMC_outw (dev, RCR_SOFTRST, RCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000300
301 /* Setup the Configuration Register */
302 /* This is necessary because the CONFIG_REG is not affected */
303 /* by a soft reset */
304
Ben Warren7194ab82009-10-04 22:37:03 -0700305 SMC_SELECT_BANK (dev, 1);
wdenkfe8c2802002-11-03 00:38:21 +0000306#if defined(CONFIG_SMC91111_EXT_PHY)
Ben Warren7194ab82009-10-04 22:37:03 -0700307 SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000308#else
Ben Warren7194ab82009-10-04 22:37:03 -0700309 SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000310#endif
311
312
313 /* Release from possible power-down state */
314 /* Configuration register is not affected by Soft Reset */
Ben Warren7194ab82009-10-04 22:37:03 -0700315 SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
316 CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000317
Ben Warren7194ab82009-10-04 22:37:03 -0700318 SMC_SELECT_BANK (dev, 0);
wdenkfe8c2802002-11-03 00:38:21 +0000319
320 /* this should pause enough for the chip to be happy */
wdenkb56ddc62003-09-15 21:14:37 +0000321 udelay (10);
wdenkfe8c2802002-11-03 00:38:21 +0000322
323 /* Disable transmit and receive functionality */
Ben Warren7194ab82009-10-04 22:37:03 -0700324 SMC_outw (dev, RCR_CLEAR, RCR_REG);
325 SMC_outw (dev, TCR_CLEAR, TCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000326
327 /* set the control register */
Ben Warren7194ab82009-10-04 22:37:03 -0700328 SMC_SELECT_BANK (dev, 1);
329 SMC_outw (dev, CTL_DEFAULT, CTL_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000330
331 /* Reset the MMU */
Ben Warren7194ab82009-10-04 22:37:03 -0700332 SMC_SELECT_BANK (dev, 2);
333 smc_wait_mmu_release_complete (dev);
334 SMC_outw (dev, MC_RESET, MMU_CMD_REG);
335 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
wdenkb56ddc62003-09-15 21:14:37 +0000336 udelay (1); /* Wait until not busy */
wdenkfe8c2802002-11-03 00:38:21 +0000337
338 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
339 but this is a place where future chipsets _COULD_ break. Be wary
wdenk8bde7f72003-06-27 21:31:46 +0000340 of issuing another MMU command right after this */
wdenkfe8c2802002-11-03 00:38:21 +0000341
342 /* Disable all interrupts */
Ben Warren7194ab82009-10-04 22:37:03 -0700343 SMC_outb (dev, 0, IM_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000344}
345
346/*
347 . Function: smc_enable
348 . Purpose: let the chip talk to the outside work
349 . Method:
350 . 1. Enable the transmitter
351 . 2. Enable the receiver
352 . 3. Enable interrupts
353*/
Ben Warren7194ab82009-10-04 22:37:03 -0700354static void smc_enable(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000355{
wdenkf39748a2004-06-09 13:37:52 +0000356 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
Ben Warren7194ab82009-10-04 22:37:03 -0700357 SMC_SELECT_BANK( dev, 0 );
wdenkfe8c2802002-11-03 00:38:21 +0000358 /* see the header file for options in TCR/RCR DEFAULT*/
Ben Warren7194ab82009-10-04 22:37:03 -0700359 SMC_outw( dev, TCR_DEFAULT, TCR_REG );
360 SMC_outw( dev, RCR_DEFAULT, RCR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000361
362 /* clear MII_DIS */
363/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
364}
365
366/*
Ben Warren7194ab82009-10-04 22:37:03 -0700367 . Function: smc_halt
wdenkfe8c2802002-11-03 00:38:21 +0000368 . Purpose: closes down the SMC91xxx chip.
369 . Method:
370 . 1. zero the interrupt mask
371 . 2. clear the enable receive flag
372 . 3. clear the enable xmit flags
373 .
374 . TODO:
375 . (1) maybe utilize power down mode.
376 . Why not yet? Because while the chip will go into power down mode,
377 . the manual says that it will wake up in response to any I/O requests
wdenk42dfe7a2004-03-14 22:25:36 +0000378 . in the register space. Empirical results do not show this working.
wdenkfe8c2802002-11-03 00:38:21 +0000379*/
Ben Warren7194ab82009-10-04 22:37:03 -0700380static void smc_halt(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000381{
Ben Warren7194ab82009-10-04 22:37:03 -0700382 PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000383
384 /* no more interrupts for me */
Ben Warren7194ab82009-10-04 22:37:03 -0700385 SMC_SELECT_BANK( dev, 2 );
386 SMC_outb( dev, 0, IM_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000387
388 /* and tell the card to stay away from that nasty outside world */
Ben Warren7194ab82009-10-04 22:37:03 -0700389 SMC_SELECT_BANK( dev, 0 );
390 SMC_outb( dev, RCR_CLEAR, RCR_REG );
391 SMC_outb( dev, TCR_CLEAR, TCR_REG );
392
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100393 swap_to(FLASH);
wdenkfe8c2802002-11-03 00:38:21 +0000394}
395
396
397/*
Ben Warren7194ab82009-10-04 22:37:03 -0700398 . Function: smc_send(struct net_device * )
wdenkfe8c2802002-11-03 00:38:21 +0000399 . Purpose:
400 . This sends the actual packet to the SMC9xxx chip.
401 .
402 . Algorithm:
wdenk42dfe7a2004-03-14 22:25:36 +0000403 . First, see if a saved_skb is available.
wdenkfe8c2802002-11-03 00:38:21 +0000404 . ( this should NOT be called if there is no 'saved_skb'
405 . Now, find the packet number that the chip allocated
406 . Point the data pointers at it in memory
407 . Set the length word in the chip's memory
408 . Dump the packet to chip memory
409 . Check if a last byte is needed ( odd length packet )
410 . if so, set the control flag right
wdenk42dfe7a2004-03-14 22:25:36 +0000411 . Tell the card to send it
wdenkfe8c2802002-11-03 00:38:21 +0000412 . Enable the transmit interrupt, so I know if it failed
wdenk42dfe7a2004-03-14 22:25:36 +0000413 . Free the kernel data if I actually sent it.
wdenkfe8c2802002-11-03 00:38:21 +0000414*/
Joe Hershberger9f098642012-05-21 14:45:32 +0000415static int smc_send(struct eth_device *dev, void *packet, int packet_length)
wdenkfe8c2802002-11-03 00:38:21 +0000416{
wdenkb56ddc62003-09-15 21:14:37 +0000417 byte packet_no;
wdenkb56ddc62003-09-15 21:14:37 +0000418 byte *buf;
419 int length;
420 int numPages;
421 int try = 0;
422 int time_out;
423 byte status;
wdenk518e2e12004-03-25 14:59:05 +0000424 byte saved_pnr;
425 word saved_ptr;
wdenkfe8c2802002-11-03 00:38:21 +0000426
wdenk518e2e12004-03-25 14:59:05 +0000427 /* save PTR and PNR registers before manipulation */
Ben Warren7194ab82009-10-04 22:37:03 -0700428 SMC_SELECT_BANK (dev, 2);
429 saved_pnr = SMC_inb( dev, PN_REG );
430 saved_ptr = SMC_inw( dev, PTR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000431
wdenkf39748a2004-06-09 13:37:52 +0000432 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000433
434 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
435
436 /* allocate memory
wdenkb56ddc62003-09-15 21:14:37 +0000437 ** The MMU wants the number of pages to be the number of 256 bytes
438 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
439 **
440 ** The 91C111 ignores the size bits, but the code is left intact
441 ** for backwards and future compatibility.
442 **
443 ** Pkt size for allocating is data length +6 (for additional status
444 ** words, length and ctl!)
445 **
446 ** If odd size then last byte is included in this header.
447 */
448 numPages = ((length & 0xfffe) + 6);
449 numPages >>= 8; /* Divide by 256 */
wdenkfe8c2802002-11-03 00:38:21 +0000450
wdenkb56ddc62003-09-15 21:14:37 +0000451 if (numPages > 7) {
452 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000453 return 0;
454 }
455
456 /* now, try to allocate the memory */
Ben Warren7194ab82009-10-04 22:37:03 -0700457 SMC_SELECT_BANK (dev, 2);
458 SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000459
wdenkdc7c9a12003-03-26 06:55:25 +0000460 /* FIXME: the ALLOC_INT bit never gets set *
wdenk42dfe7a2004-03-14 22:25:36 +0000461 * so the following will always give a *
462 * memory allocation error. *
463 * same code works in armboot though *
wdenkdc7c9a12003-03-26 06:55:25 +0000464 * -ro
465 */
466
wdenkfe8c2802002-11-03 00:38:21 +0000467again:
468 try++;
469 time_out = MEMORY_WAIT_TIME;
470 do {
Ben Warren7194ab82009-10-04 22:37:03 -0700471 status = SMC_inb (dev, SMC91111_INT_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000472 if (status & IM_ALLOC_INT) {
wdenkfe8c2802002-11-03 00:38:21 +0000473 /* acknowledge the interrupt */
Ben Warren7194ab82009-10-04 22:37:03 -0700474 SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
wdenk8bde7f72003-06-27 21:31:46 +0000475 break;
wdenkfe8c2802002-11-03 00:38:21 +0000476 }
wdenkb56ddc62003-09-15 21:14:37 +0000477 } while (--time_out);
wdenkfe8c2802002-11-03 00:38:21 +0000478
wdenkb56ddc62003-09-15 21:14:37 +0000479 if (!time_out) {
480 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
481 SMC_DEV_NAME, try);
482 if (try < SMC_ALLOC_MAX_TRY)
483 goto again;
484 else
485 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000486 }
487
wdenkb56ddc62003-09-15 21:14:37 +0000488 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
489 SMC_DEV_NAME, try);
wdenkfe8c2802002-11-03 00:38:21 +0000490
wdenkb56ddc62003-09-15 21:14:37 +0000491 buf = (byte *) packet;
wdenkfe8c2802002-11-03 00:38:21 +0000492
493 /* If I get here, I _know_ there is a packet slot waiting for me */
Ben Warren7194ab82009-10-04 22:37:03 -0700494 packet_no = SMC_inb (dev, AR_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000495 if (packet_no & AR_FAILED) {
wdenkfe8c2802002-11-03 00:38:21 +0000496 /* or isn't there? BAD CHIP! */
wdenkb56ddc62003-09-15 21:14:37 +0000497 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000498 return 0;
499 }
500
501 /* we have a packet address, so tell the card to use it */
wdenk1f6d4252004-11-02 13:00:33 +0000502#ifndef CONFIG_XAENIAX
Ben Warren7194ab82009-10-04 22:37:03 -0700503 SMC_outb (dev, packet_no, PN_REG);
wdenk1f6d4252004-11-02 13:00:33 +0000504#else
505 /* On Xaeniax board, we can't use SMC_outb here because that way
506 * the Allocate MMU command will end up written to the command register
507 * as well, which will lead to a problem.
508 */
Ben Warren7194ab82009-10-04 22:37:03 -0700509 SMC_outl (dev, packet_no << 16, 0);
wdenk1f6d4252004-11-02 13:00:33 +0000510#endif
wdenkb79a11c2004-03-25 15:14:43 +0000511 /* do not write new ptr value if Write data fifo not empty */
512 while ( saved_ptr & PTR_NOTEMPTY )
wdenk518e2e12004-03-25 14:59:05 +0000513 printf ("Write data fifo not empty!\n");
514
wdenkfe8c2802002-11-03 00:38:21 +0000515 /* point to the beginning of the packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700516 SMC_outw (dev, PTR_AUTOINC, PTR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000517
wdenkb56ddc62003-09-15 21:14:37 +0000518 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
519 SMC_DEV_NAME, length);
wdenkfe8c2802002-11-03 00:38:21 +0000520
521#if SMC_DEBUG > 2
wdenkb56ddc62003-09-15 21:14:37 +0000522 printf ("Transmitting Packet\n");
523 print_packet (buf, length);
wdenkfe8c2802002-11-03 00:38:21 +0000524#endif
525
526 /* send the packet length ( +6 for status, length and ctl byte )
wdenk8bde7f72003-06-27 21:31:46 +0000527 and the status word ( set to zeros ) */
wdenkfe8c2802002-11-03 00:38:21 +0000528#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700529 SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000530#else
Ben Warren7194ab82009-10-04 22:37:03 -0700531 SMC_outw (dev, 0, SMC91111_DATA_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000532 /* send the packet length ( +6 for status words, length, and ctl */
Ben Warren7194ab82009-10-04 22:37:03 -0700533 SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000534#endif
535
536 /* send the actual data
wdenkb56ddc62003-09-15 21:14:37 +0000537 . I _think_ it's faster to send the longs first, and then
538 . mop up by sending the last word. It depends heavily
wdenk42dfe7a2004-03-14 22:25:36 +0000539 . on alignment, at least on the 486. Maybe it would be
wdenkb56ddc62003-09-15 21:14:37 +0000540 . a good idea to check which is optimal? But that could take
541 . almost as much time as is saved?
542 */
wdenkfe8c2802002-11-03 00:38:21 +0000543#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700544 SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
wdenkbb310d42004-11-22 22:20:07 +0000545#ifndef CONFIG_XAENIAX
wdenkb56ddc62003-09-15 21:14:37 +0000546 if (length & 0x2)
Ben Warren7194ab82009-10-04 22:37:03 -0700547 SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
wdenkb56ddc62003-09-15 21:14:37 +0000548 SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000549#else
wdenkbb310d42004-11-22 22:20:07 +0000550 /* On XANEIAX, we can only use 32-bit writes, so we need to handle
551 * unaligned tail part specially. The standard code doesn't work.
552 */
553 if ((length & 3) == 3) {
554 u16 * ptr = (u16*) &buf[length-3];
Ben Warren7194ab82009-10-04 22:37:03 -0700555 SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16),
wdenkbb310d42004-11-22 22:20:07 +0000556 SMC91111_DATA_REG);
557 } else if ((length & 2) == 2) {
558 u16 * ptr = (u16*) &buf[length-2];
Ben Warren7194ab82009-10-04 22:37:03 -0700559 SMC_outl(dev, *ptr, SMC91111_DATA_REG);
wdenkbb310d42004-11-22 22:20:07 +0000560 } else if (length & 1) {
Ben Warren7194ab82009-10-04 22:37:03 -0700561 SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG);
wdenkbb310d42004-11-22 22:20:07 +0000562 } else {
Ben Warren7194ab82009-10-04 22:37:03 -0700563 SMC_outl(dev, 0, SMC91111_DATA_REG);
wdenkbb310d42004-11-22 22:20:07 +0000564 }
565#endif
566#else
Ben Warren7194ab82009-10-04 22:37:03 -0700567 SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
wdenkfe8c2802002-11-03 00:38:21 +0000568#endif /* USE_32_BIT */
569
wdenkbb310d42004-11-22 22:20:07 +0000570#ifndef CONFIG_XAENIAX
wdenk42dfe7a2004-03-14 22:25:36 +0000571 /* Send the last byte, if there is one. */
wdenkb56ddc62003-09-15 21:14:37 +0000572 if ((length & 1) == 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700573 SMC_outw (dev, 0, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000574 } else {
Ben Warren7194ab82009-10-04 22:37:03 -0700575 SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000576 }
wdenkbb310d42004-11-22 22:20:07 +0000577#endif
wdenkfe8c2802002-11-03 00:38:21 +0000578
579 /* and let the chipset deal with it */
Ben Warren7194ab82009-10-04 22:37:03 -0700580 SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000581
582 /* poll for TX INT */
Ben Warren7194ab82009-10-04 22:37:03 -0700583 /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
wdenk518e2e12004-03-25 14:59:05 +0000584 /* poll for TX_EMPTY INT - autorelease enabled */
Ben Warren7194ab82009-10-04 22:37:03 -0700585 if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
wdenkfe8c2802002-11-03 00:38:21 +0000586 /* sending failed */
wdenkb56ddc62003-09-15 21:14:37 +0000587 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000588
589 /* release packet */
wdenk518e2e12004-03-25 14:59:05 +0000590 /* no need to release, MMU does that now */
wdenk1f6d4252004-11-02 13:00:33 +0000591#ifdef CONFIG_XAENIAX
Ben Warren7194ab82009-10-04 22:37:03 -0700592 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
wdenk1f6d4252004-11-02 13:00:33 +0000593#endif
wdenkfe8c2802002-11-03 00:38:21 +0000594
wdenk8bde7f72003-06-27 21:31:46 +0000595 /* wait for MMU getting ready (low) */
Ben Warren7194ab82009-10-04 22:37:03 -0700596 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
wdenkb56ddc62003-09-15 21:14:37 +0000597 udelay (10);
wdenk8bde7f72003-06-27 21:31:46 +0000598 }
wdenkfe8c2802002-11-03 00:38:21 +0000599
wdenkb56ddc62003-09-15 21:14:37 +0000600 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000601
602
603 return 0;
604 } else {
605 /* ack. int */
Ben Warren7194ab82009-10-04 22:37:03 -0700606 SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
wdenk518e2e12004-03-25 14:59:05 +0000607 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
wdenkb56ddc62003-09-15 21:14:37 +0000608 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
609 length);
wdenkfe8c2802002-11-03 00:38:21 +0000610
611 /* release packet */
wdenk518e2e12004-03-25 14:59:05 +0000612 /* no need to release, MMU does that now */
wdenk1f6d4252004-11-02 13:00:33 +0000613#ifdef CONFIG_XAENIAX
Ben Warren7194ab82009-10-04 22:37:03 -0700614 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
wdenk1f6d4252004-11-02 13:00:33 +0000615#endif
wdenkfe8c2802002-11-03 00:38:21 +0000616
wdenk8bde7f72003-06-27 21:31:46 +0000617 /* wait for MMU getting ready (low) */
Ben Warren7194ab82009-10-04 22:37:03 -0700618 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
wdenkb56ddc62003-09-15 21:14:37 +0000619 udelay (10);
wdenk8bde7f72003-06-27 21:31:46 +0000620 }
wdenkfe8c2802002-11-03 00:38:21 +0000621
wdenkb56ddc62003-09-15 21:14:37 +0000622 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000623
624
625 }
626
wdenk518e2e12004-03-25 14:59:05 +0000627 /* restore previously saved registers */
wdenk1f6d4252004-11-02 13:00:33 +0000628#ifndef CONFIG_XAENIAX
Ben Warren7194ab82009-10-04 22:37:03 -0700629 SMC_outb( dev, saved_pnr, PN_REG );
wdenk1f6d4252004-11-02 13:00:33 +0000630#else
631 /* On Xaeniax board, we can't use SMC_outb here because that way
632 * the Allocate MMU command will end up written to the command register
633 * as well, which will lead to a problem.
634 */
Ben Warren7194ab82009-10-04 22:37:03 -0700635 SMC_outl(dev, saved_pnr << 16, 0);
wdenk1f6d4252004-11-02 13:00:33 +0000636#endif
Ben Warren7194ab82009-10-04 22:37:03 -0700637 SMC_outw( dev, saved_ptr, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000638
wdenkfe8c2802002-11-03 00:38:21 +0000639 return length;
640}
641
Thomas Chou1ca6d0d2010-10-06 09:16:10 +0800642static int smc_write_hwaddr(struct eth_device *dev)
643{
644 int i;
645
646 swap_to(ETHERNET);
647 SMC_SELECT_BANK (dev, 1);
648#ifdef USE_32_BIT
649 for (i = 0; i < 6; i += 2) {
650 word address;
651
652 address = dev->enetaddr[i + 1] << 8;
653 address |= dev->enetaddr[i];
654 SMC_outw(dev, address, (ADDR0_REG + i));
655 }
656#else
657 for (i = 0; i < 6; i++)
658 SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
659#endif
660 swap_to(FLASH);
661 return 0;
662}
663
wdenkfe8c2802002-11-03 00:38:21 +0000664/*
665 * Open and Initialize the board
666 *
667 * Set up everything, reset the card, etc ..
668 *
669 */
Ben Warren7194ab82009-10-04 22:37:03 -0700670static int smc_init(struct eth_device *dev, bd_t *bd)
wdenkfe8c2802002-11-03 00:38:21 +0000671{
Ben Warren7194ab82009-10-04 22:37:03 -0700672 swap_to(ETHERNET);
673
674 PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000675
676 /* reset the hardware */
Ben Warren7194ab82009-10-04 22:37:03 -0700677 smc_reset (dev);
678 smc_enable (dev);
wdenkfe8c2802002-11-03 00:38:21 +0000679
680 /* Configure the PHY */
681#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700682 smc_phy_configure (dev);
wdenkfe8c2802002-11-03 00:38:21 +0000683#endif
684
wdenkfe8c2802002-11-03 00:38:21 +0000685 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
Ben Warren7194ab82009-10-04 22:37:03 -0700686/* SMC_SELECT_BANK(dev, 0); */
687/* SMC_outw(dev, 0, RPC_REG); */
wdenkfe8c2802002-11-03 00:38:21 +0000688
Ben Warren7194ab82009-10-04 22:37:03 -0700689 printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
690
wdenkfe8c2802002-11-03 00:38:21 +0000691 return 0;
692}
693
wdenkfe8c2802002-11-03 00:38:21 +0000694/*-------------------------------------------------------------
695 .
696 . smc_rcv - receive a packet from the card
697 .
698 . There is ( at least ) a packet waiting to be read from
699 . chip-memory.
700 .
701 . o Read the status
702 . o If an error, record it
703 . o otherwise, read in the packet
704 --------------------------------------------------------------
705*/
Ben Warren7194ab82009-10-04 22:37:03 -0700706static int smc_rcv(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000707{
wdenk42dfe7a2004-03-14 22:25:36 +0000708 int packet_number;
wdenkfe8c2802002-11-03 00:38:21 +0000709 word status;
710 word packet_length;
wdenk42dfe7a2004-03-14 22:25:36 +0000711 int is_error = 0;
wdenkfe8c2802002-11-03 00:38:21 +0000712#ifdef USE_32_BIT
713 dword stat_len;
714#endif
wdenk518e2e12004-03-25 14:59:05 +0000715 byte saved_pnr;
716 word saved_ptr;
wdenkfe8c2802002-11-03 00:38:21 +0000717
Ben Warren7194ab82009-10-04 22:37:03 -0700718 SMC_SELECT_BANK(dev, 2);
wdenk518e2e12004-03-25 14:59:05 +0000719 /* save PTR and PTR registers */
Ben Warren7194ab82009-10-04 22:37:03 -0700720 saved_pnr = SMC_inb( dev, PN_REG );
721 saved_ptr = SMC_inw( dev, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000722
Ben Warren7194ab82009-10-04 22:37:03 -0700723 packet_number = SMC_inw( dev, RXFIFO_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000724
725 if ( packet_number & RXFIFO_REMPTY ) {
726
727 return 0;
728 }
729
wdenkf39748a2004-06-09 13:37:52 +0000730 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000731 /* start reading from the start of the packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700732 SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000733
734 /* First two words are status and packet_length */
735#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700736 stat_len = SMC_inl(dev, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000737 status = stat_len & 0xffff;
738 packet_length = stat_len >> 16;
739#else
Ben Warren7194ab82009-10-04 22:37:03 -0700740 status = SMC_inw( dev, SMC91111_DATA_REG );
741 packet_length = SMC_inw( dev, SMC91111_DATA_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000742#endif
743
744 packet_length &= 0x07ff; /* mask off top bits */
745
746 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
747
748 if ( !(status & RS_ERRORS ) ){
749 /* Adjust for having already read the first two words */
750 packet_length -= 4; /*4; */
751
752
wdenkfe8c2802002-11-03 00:38:21 +0000753 /* set odd length for bug in LAN91C111, */
754 /* which never sets RS_ODDFRAME */
755 /* TODO ? */
756
757
758#ifdef USE_32_BIT
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500759 PRINTK3(" Reading %d dwords (and %d bytes)\n",
wdenkfe8c2802002-11-03 00:38:21 +0000760 packet_length >> 2, packet_length & 3 );
761 /* QUESTION: Like in the TX routine, do I want
762 to send the DWORDs or the bytes first, or some
763 mixture. A mixture might improve already slow PIO
wdenk42dfe7a2004-03-14 22:25:36 +0000764 performance */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500765 SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0],
766 packet_length >> 2);
wdenkfe8c2802002-11-03 00:38:21 +0000767 /* read the left over bytes */
768 if (packet_length & 3) {
769 int i;
770
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500771 byte *tail = (byte *)(net_rx_packets[0] +
Ben Warren7194ab82009-10-04 22:37:03 -0700772 (packet_length & ~3));
773 dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000774 for (i=0; i<(packet_length & 3); i++)
775 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
776 }
777#else
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500778 PRINTK3(" Reading %d words and %d byte(s)\n",
wdenkfe8c2802002-11-03 00:38:21 +0000779 (packet_length >> 1 ), packet_length & 1 );
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500780 SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0],
781 packet_length >> 1);
wdenkfe8c2802002-11-03 00:38:21 +0000782
783#endif /* USE_32_BIT */
784
785#if SMC_DEBUG > 2
786 printf("Receiving Packet\n");
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500787 print_packet(net_rx_packets[0], packet_length);
wdenkfe8c2802002-11-03 00:38:21 +0000788#endif
789 } else {
790 /* error ... */
791 /* TODO ? */
792 is_error = 1;
793 }
794
Ben Warren7194ab82009-10-04 22:37:03 -0700795 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
wdenkfe8c2802002-11-03 00:38:21 +0000796 udelay(1); /* Wait until not busy */
797
798 /* error or good, tell the card to get rid of this packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700799 SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000800
Ben Warren7194ab82009-10-04 22:37:03 -0700801 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
wdenkfe8c2802002-11-03 00:38:21 +0000802 udelay(1); /* Wait until not busy */
803
wdenk518e2e12004-03-25 14:59:05 +0000804 /* restore saved registers */
wdenk1f6d4252004-11-02 13:00:33 +0000805#ifndef CONFIG_XAENIAX
Ben Warren7194ab82009-10-04 22:37:03 -0700806 SMC_outb( dev, saved_pnr, PN_REG );
wdenk1f6d4252004-11-02 13:00:33 +0000807#else
808 /* On Xaeniax board, we can't use SMC_outb here because that way
809 * the Allocate MMU command will end up written to the command register
810 * as well, which will lead to a problem.
811 */
Ben Warren7194ab82009-10-04 22:37:03 -0700812 SMC_outl( dev, saved_pnr << 16, 0);
wdenk1f6d4252004-11-02 13:00:33 +0000813#endif
Ben Warren7194ab82009-10-04 22:37:03 -0700814 SMC_outw( dev, saved_ptr, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000815
wdenkfe8c2802002-11-03 00:38:21 +0000816 if (!is_error) {
817 /* Pass the packet up to the protocol layers. */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500818 net_process_received_packet(net_rx_packets[0], packet_length);
wdenkfe8c2802002-11-03 00:38:21 +0000819 return packet_length;
820 } else {
821 return 0;
822 }
823
824}
825
826
wdenkfe8c2802002-11-03 00:38:21 +0000827#if 0
828/*------------------------------------------------------------
829 . Modify a bit in the LAN91C111 register set
830 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700831static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
wdenkfe8c2802002-11-03 00:38:21 +0000832 unsigned int bit, int val)
833{
834 word regval;
835
Ben Warren7194ab82009-10-04 22:37:03 -0700836 SMC_SELECT_BANK( dev, bank );
wdenkfe8c2802002-11-03 00:38:21 +0000837
Ben Warren7194ab82009-10-04 22:37:03 -0700838 regval = SMC_inw( dev, reg );
wdenkfe8c2802002-11-03 00:38:21 +0000839 if (val)
840 regval |= bit;
841 else
842 regval &= ~bit;
843
Ben Warren7194ab82009-10-04 22:37:03 -0700844 SMC_outw( dev, regval, 0 );
wdenkfe8c2802002-11-03 00:38:21 +0000845 return(regval);
846}
847
848
849/*------------------------------------------------------------
850 . Retrieve a bit in the LAN91C111 register set
851 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700852static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
wdenkfe8c2802002-11-03 00:38:21 +0000853{
Ben Warren7194ab82009-10-04 22:37:03 -0700854 SMC_SELECT_BANK( dev, bank );
855 if ( SMC_inw( dev, reg ) & bit)
wdenkfe8c2802002-11-03 00:38:21 +0000856 return(1);
857 else
858 return(0);
859}
860
861
862/*------------------------------------------------------------
863 . Modify a LAN91C111 register (word access only)
864 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700865static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
wdenkfe8c2802002-11-03 00:38:21 +0000866{
Ben Warren7194ab82009-10-04 22:37:03 -0700867 SMC_SELECT_BANK( dev, bank );
868 SMC_outw( dev, val, reg );
wdenkfe8c2802002-11-03 00:38:21 +0000869}
870
871
872/*------------------------------------------------------------
873 . Retrieve a LAN91C111 register (word access only)
874 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700875static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
wdenkfe8c2802002-11-03 00:38:21 +0000876{
Ben Warren7194ab82009-10-04 22:37:03 -0700877 SMC_SELECT_BANK( dev, bank );
878 return(SMC_inw( dev, reg ));
wdenkfe8c2802002-11-03 00:38:21 +0000879}
880
881#endif /* 0 */
882
883/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
884
885#if (SMC_DEBUG > 2 )
886
887/*------------------------------------------------------------
888 . Debugging function for viewing MII Management serial bitstream
889 .-------------------------------------------------------------*/
wdenkb56ddc62003-09-15 21:14:37 +0000890static void smc_dump_mii_stream (byte * bits, int size)
wdenkfe8c2802002-11-03 00:38:21 +0000891{
892 int i;
893
wdenkb56ddc62003-09-15 21:14:37 +0000894 printf ("BIT#:");
895 for (i = 0; i < size; ++i) {
896 printf ("%d", i % 10);
897 }
wdenkfe8c2802002-11-03 00:38:21 +0000898
wdenkb56ddc62003-09-15 21:14:37 +0000899 printf ("\nMDOE:");
900 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000901 if (bits[i] & MII_MDOE)
wdenkb56ddc62003-09-15 21:14:37 +0000902 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000903 else
wdenkb56ddc62003-09-15 21:14:37 +0000904 printf ("0");
905 }
wdenkfe8c2802002-11-03 00:38:21 +0000906
wdenkb56ddc62003-09-15 21:14:37 +0000907 printf ("\nMDO :");
908 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000909 if (bits[i] & MII_MDO)
wdenkb56ddc62003-09-15 21:14:37 +0000910 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000911 else
wdenkb56ddc62003-09-15 21:14:37 +0000912 printf ("0");
913 }
wdenkfe8c2802002-11-03 00:38:21 +0000914
wdenkb56ddc62003-09-15 21:14:37 +0000915 printf ("\nMDI :");
916 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000917 if (bits[i] & MII_MDI)
wdenkb56ddc62003-09-15 21:14:37 +0000918 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000919 else
wdenkb56ddc62003-09-15 21:14:37 +0000920 printf ("0");
921 }
wdenkfe8c2802002-11-03 00:38:21 +0000922
wdenkb56ddc62003-09-15 21:14:37 +0000923 printf ("\n");
wdenkfe8c2802002-11-03 00:38:21 +0000924}
925#endif
926
927/*------------------------------------------------------------
928 . Reads a register from the MII Management serial interface
929 .-------------------------------------------------------------*/
930#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700931static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
wdenkfe8c2802002-11-03 00:38:21 +0000932{
933 int oldBank;
934 int i;
935 byte mask;
936 word mii_reg;
937 byte bits[64];
938 int clk_idx = 0;
939 int input_idx;
940 word phydata;
941 byte phyaddr = SMC_PHY_ADDR;
942
943 /* 32 consecutive ones on MDO to establish sync */
944 for (i = 0; i < 32; ++i)
945 bits[clk_idx++] = MII_MDOE | MII_MDO;
946
947 /* Start code <01> */
948 bits[clk_idx++] = MII_MDOE;
949 bits[clk_idx++] = MII_MDOE | MII_MDO;
950
951 /* Read command <10> */
952 bits[clk_idx++] = MII_MDOE | MII_MDO;
953 bits[clk_idx++] = MII_MDOE;
954
955 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +0000956 mask = (byte) 0x10;
957 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000958 if (phyaddr & mask)
959 bits[clk_idx++] = MII_MDOE | MII_MDO;
960 else
961 bits[clk_idx++] = MII_MDOE;
962
963 /* Shift to next lowest bit */
964 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +0000965 }
wdenkfe8c2802002-11-03 00:38:21 +0000966
967 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +0000968 mask = (byte) 0x10;
969 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000970 if (phyreg & mask)
971 bits[clk_idx++] = MII_MDOE | MII_MDO;
972 else
973 bits[clk_idx++] = MII_MDOE;
974
975 /* Shift to next lowest bit */
976 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +0000977 }
wdenkfe8c2802002-11-03 00:38:21 +0000978
979 /* Tristate and turnaround (2 bit times) */
980 bits[clk_idx++] = 0;
981 /*bits[clk_idx++] = 0; */
982
983 /* Input starts at this bit time */
984 input_idx = clk_idx;
985
986 /* Will input 16 bits */
987 for (i = 0; i < 16; ++i)
988 bits[clk_idx++] = 0;
989
990 /* Final clock bit */
991 bits[clk_idx++] = 0;
992
993 /* Save the current bank */
Ben Warren7194ab82009-10-04 22:37:03 -0700994 oldBank = SMC_inw (dev, BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +0000995
996 /* Select bank 3 */
Ben Warren7194ab82009-10-04 22:37:03 -0700997 SMC_SELECT_BANK (dev, 3);
wdenkfe8c2802002-11-03 00:38:21 +0000998
999 /* Get the current MII register value */
Ben Warren7194ab82009-10-04 22:37:03 -07001000 mii_reg = SMC_inw (dev, MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001001
1002 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +00001003 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +00001004
1005 /* Clock all 64 cycles */
wdenkb56ddc62003-09-15 21:14:37 +00001006 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001007 /* Clock Low - output data */
Ben Warren7194ab82009-10-04 22:37:03 -07001008 SMC_outw (dev, mii_reg | bits[i], MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001009 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001010
1011
1012 /* Clock Hi - input data */
Ben Warren7194ab82009-10-04 22:37:03 -07001013 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001014 udelay (SMC_PHY_CLOCK_DELAY);
Ben Warren7194ab82009-10-04 22:37:03 -07001015 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
wdenkb56ddc62003-09-15 21:14:37 +00001016 }
wdenkfe8c2802002-11-03 00:38:21 +00001017
1018 /* Return to idle state */
1019 /* Set clock to low, data to low, and output tristated */
Ben Warren7194ab82009-10-04 22:37:03 -07001020 SMC_outw (dev, mii_reg, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001021 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001022
1023 /* Restore original bank select */
Ben Warren7194ab82009-10-04 22:37:03 -07001024 SMC_SELECT_BANK (dev, oldBank);
wdenkfe8c2802002-11-03 00:38:21 +00001025
1026 /* Recover input data */
1027 phydata = 0;
wdenkb56ddc62003-09-15 21:14:37 +00001028 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001029 phydata <<= 1;
1030
1031 if (bits[input_idx++] & MII_MDI)
1032 phydata |= 0x0001;
wdenkb56ddc62003-09-15 21:14:37 +00001033 }
wdenkfe8c2802002-11-03 00:38:21 +00001034
1035#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +00001036 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +00001037 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +00001038 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +00001039#endif
1040
wdenkb56ddc62003-09-15 21:14:37 +00001041 return (phydata);
wdenkfe8c2802002-11-03 00:38:21 +00001042}
1043
1044
1045/*------------------------------------------------------------
1046 . Writes a register to the MII Management serial interface
1047 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -07001048static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
1049 word phydata)
wdenkfe8c2802002-11-03 00:38:21 +00001050{
1051 int oldBank;
1052 int i;
1053 word mask;
1054 word mii_reg;
1055 byte bits[65];
1056 int clk_idx = 0;
1057 byte phyaddr = SMC_PHY_ADDR;
1058
1059 /* 32 consecutive ones on MDO to establish sync */
1060 for (i = 0; i < 32; ++i)
1061 bits[clk_idx++] = MII_MDOE | MII_MDO;
1062
1063 /* Start code <01> */
1064 bits[clk_idx++] = MII_MDOE;
1065 bits[clk_idx++] = MII_MDOE | MII_MDO;
1066
1067 /* Write command <01> */
1068 bits[clk_idx++] = MII_MDOE;
1069 bits[clk_idx++] = MII_MDOE | MII_MDO;
1070
1071 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001072 mask = (byte) 0x10;
1073 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001074 if (phyaddr & mask)
1075 bits[clk_idx++] = MII_MDOE | MII_MDO;
1076 else
1077 bits[clk_idx++] = MII_MDOE;
1078
1079 /* Shift to next lowest bit */
1080 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001081 }
wdenkfe8c2802002-11-03 00:38:21 +00001082
1083 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001084 mask = (byte) 0x10;
1085 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001086 if (phyreg & mask)
1087 bits[clk_idx++] = MII_MDOE | MII_MDO;
1088 else
1089 bits[clk_idx++] = MII_MDOE;
1090
1091 /* Shift to next lowest bit */
1092 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001093 }
wdenkfe8c2802002-11-03 00:38:21 +00001094
1095 /* Tristate and turnaround (2 bit times) */
1096 bits[clk_idx++] = 0;
1097 bits[clk_idx++] = 0;
1098
1099 /* Write out 16 bits of data, msb first */
1100 mask = 0x8000;
wdenkb56ddc62003-09-15 21:14:37 +00001101 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001102 if (phydata & mask)
1103 bits[clk_idx++] = MII_MDOE | MII_MDO;
1104 else
1105 bits[clk_idx++] = MII_MDOE;
1106
1107 /* Shift to next lowest bit */
1108 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001109 }
wdenkfe8c2802002-11-03 00:38:21 +00001110
1111 /* Final clock bit (tristate) */
1112 bits[clk_idx++] = 0;
1113
1114 /* Save the current bank */
Ben Warren7194ab82009-10-04 22:37:03 -07001115 oldBank = SMC_inw (dev, BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +00001116
1117 /* Select bank 3 */
Ben Warren7194ab82009-10-04 22:37:03 -07001118 SMC_SELECT_BANK (dev, 3);
wdenkfe8c2802002-11-03 00:38:21 +00001119
1120 /* Get the current MII register value */
Ben Warren7194ab82009-10-04 22:37:03 -07001121 mii_reg = SMC_inw (dev, MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001122
1123 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +00001124 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +00001125
1126 /* Clock all cycles */
wdenkb56ddc62003-09-15 21:14:37 +00001127 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001128 /* Clock Low - output data */
Ben Warren7194ab82009-10-04 22:37:03 -07001129 SMC_outw (dev, mii_reg | bits[i], MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001130 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001131
1132
1133 /* Clock Hi - input data */
Ben Warren7194ab82009-10-04 22:37:03 -07001134 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001135 udelay (SMC_PHY_CLOCK_DELAY);
Ben Warren7194ab82009-10-04 22:37:03 -07001136 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
wdenkb56ddc62003-09-15 21:14:37 +00001137 }
wdenkfe8c2802002-11-03 00:38:21 +00001138
1139 /* Return to idle state */
1140 /* Set clock to low, data to low, and output tristated */
Ben Warren7194ab82009-10-04 22:37:03 -07001141 SMC_outw (dev, mii_reg, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001142 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001143
1144 /* Restore original bank select */
Ben Warren7194ab82009-10-04 22:37:03 -07001145 SMC_SELECT_BANK (dev, oldBank);
wdenkfe8c2802002-11-03 00:38:21 +00001146
1147#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +00001148 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +00001149 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +00001150 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +00001151#endif
1152}
1153#endif /* !CONFIG_SMC91111_EXT_PHY */
1154
1155
wdenkfe8c2802002-11-03 00:38:21 +00001156/*------------------------------------------------------------
wdenkfe8c2802002-11-03 00:38:21 +00001157 . Configures the specified PHY using Autonegotiation. Calls
1158 . smc_phy_fixed() if the user has requested a certain config.
1159 .-------------------------------------------------------------*/
1160#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -07001161static void smc_phy_configure (struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +00001162{
1163 int timeout;
wdenkb56ddc62003-09-15 21:14:37 +00001164 word my_phy_caps; /* My PHY capabilities */
1165 word my_ad_caps; /* My Advertised capabilities */
1166 word status = 0; /*;my status = 0 */
wdenkfe8c2802002-11-03 00:38:21 +00001167
wdenkf39748a2004-06-09 13:37:52 +00001168 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001169
wdenkfe8c2802002-11-03 00:38:21 +00001170 /* Reset the PHY, setting all other bits to zero */
Ben Warren7194ab82009-10-04 22:37:03 -07001171 smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001172
1173 /* Wait for the reset to complete, or time out */
wdenkb56ddc62003-09-15 21:14:37 +00001174 timeout = 6; /* Wait up to 3 seconds */
1175 while (timeout--) {
Ben Warren7194ab82009-10-04 22:37:03 -07001176 if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
wdenkb56ddc62003-09-15 21:14:37 +00001177 & PHY_CNTL_RST)) {
wdenkfe8c2802002-11-03 00:38:21 +00001178 /* reset complete */
1179 break;
wdenkfe8c2802002-11-03 00:38:21 +00001180 }
1181
Mike Frysinger65029492012-03-05 13:46:51 +00001182 mdelay(500); /* wait 500 millisecs */
wdenkb56ddc62003-09-15 21:14:37 +00001183 }
1184
1185 if (timeout < 1) {
1186 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001187 goto smc_phy_configure_exit;
wdenkb56ddc62003-09-15 21:14:37 +00001188 }
wdenkfe8c2802002-11-03 00:38:21 +00001189
1190 /* Read PHY Register 18, Status Output */
1191 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1192
1193 /* Enable PHY Interrupts (for register 18) */
1194 /* Interrupts listed here are disabled */
Ben Warren7194ab82009-10-04 22:37:03 -07001195 smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
wdenkfe8c2802002-11-03 00:38:21 +00001196
1197 /* Configure the Receive/Phy Control register */
Ben Warren7194ab82009-10-04 22:37:03 -07001198 SMC_SELECT_BANK (dev, 0);
1199 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001200
1201 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
Ben Warren7194ab82009-10-04 22:37:03 -07001202 my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001203 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
wdenkfe8c2802002-11-03 00:38:21 +00001204
1205 if (my_phy_caps & PHY_STAT_CAP_T4)
1206 my_ad_caps |= PHY_AD_T4;
1207
1208 if (my_phy_caps & PHY_STAT_CAP_TXF)
1209 my_ad_caps |= PHY_AD_TX_FDX;
1210
1211 if (my_phy_caps & PHY_STAT_CAP_TXH)
1212 my_ad_caps |= PHY_AD_TX_HDX;
1213
1214 if (my_phy_caps & PHY_STAT_CAP_TF)
1215 my_ad_caps |= PHY_AD_10_FDX;
1216
1217 if (my_phy_caps & PHY_STAT_CAP_TH)
1218 my_ad_caps |= PHY_AD_10_HDX;
1219
1220 /* Update our Auto-Neg Advertisement Register */
Ben Warren7194ab82009-10-04 22:37:03 -07001221 smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001222
wdenk518e2e12004-03-25 14:59:05 +00001223 /* Read the register back. Without this, it appears that when */
1224 /* auto-negotiation is restarted, sometimes it isn't ready and */
1225 /* the link does not come up. */
Ben Warren7194ab82009-10-04 22:37:03 -07001226 smc_read_phy_register(dev, PHY_AD_REG);
wdenk518e2e12004-03-25 14:59:05 +00001227
wdenkf39748a2004-06-09 13:37:52 +00001228 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1229 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001230
1231 /* Restart auto-negotiation process in order to advertise my caps */
Ben Warren7194ab82009-10-04 22:37:03 -07001232 smc_write_phy_register (dev, PHY_CNTL_REG,
wdenkb56ddc62003-09-15 21:14:37 +00001233 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001234
1235 /* Wait for the auto-negotiation to complete. This may take from */
1236 /* 2 to 3 seconds. */
1237 /* Wait for the reset to complete, or time out */
wdenkf39748a2004-06-09 13:37:52 +00001238 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
wdenkb56ddc62003-09-15 21:14:37 +00001239 while (timeout--) {
wdenkf39748a2004-06-09 13:37:52 +00001240
Ben Warren7194ab82009-10-04 22:37:03 -07001241 status = smc_read_phy_register (dev, PHY_STAT_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001242 if (status & PHY_STAT_ANEG_ACK) {
wdenkfe8c2802002-11-03 00:38:21 +00001243 /* auto-negotiate complete */
1244 break;
wdenkb56ddc62003-09-15 21:14:37 +00001245 }
wdenkfe8c2802002-11-03 00:38:21 +00001246
Mike Frysinger65029492012-03-05 13:46:51 +00001247 mdelay(500); /* wait 500 millisecs */
wdenkfe8c2802002-11-03 00:38:21 +00001248
1249 /* Restart auto-negotiation if remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001250 if (status & PHY_STAT_REM_FLT) {
wdenkf39748a2004-06-09 13:37:52 +00001251 printf ("%s: PHY remote fault detected\n",
wdenkb56ddc62003-09-15 21:14:37 +00001252 SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001253
1254 /* Restart auto-negotiation */
wdenkf39748a2004-06-09 13:37:52 +00001255 printf ("%s: PHY restarting auto-negotiation\n",
wdenkfe8c2802002-11-03 00:38:21 +00001256 SMC_DEV_NAME);
Ben Warren7194ab82009-10-04 22:37:03 -07001257 smc_write_phy_register (dev, PHY_CNTL_REG,
wdenkb56ddc62003-09-15 21:14:37 +00001258 PHY_CNTL_ANEG_EN |
1259 PHY_CNTL_ANEG_RST |
1260 PHY_CNTL_SPEED |
1261 PHY_CNTL_DPLX);
wdenkfe8c2802002-11-03 00:38:21 +00001262 }
wdenkb56ddc62003-09-15 21:14:37 +00001263 }
wdenkfe8c2802002-11-03 00:38:21 +00001264
wdenkb56ddc62003-09-15 21:14:37 +00001265 if (timeout < 1) {
wdenkf39748a2004-06-09 13:37:52 +00001266 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
wdenkb56ddc62003-09-15 21:14:37 +00001267 }
wdenkfe8c2802002-11-03 00:38:21 +00001268
1269 /* Fail if we detected an auto-negotiate remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001270 if (status & PHY_STAT_REM_FLT) {
wdenkf39748a2004-06-09 13:37:52 +00001271 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
wdenkb56ddc62003-09-15 21:14:37 +00001272 }
wdenkfe8c2802002-11-03 00:38:21 +00001273
1274 /* Re-Configure the Receive/Phy Control register */
Ben Warren7194ab82009-10-04 22:37:03 -07001275 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001276
wdenk26238132004-07-09 22:51:01 +00001277smc_phy_configure_exit: ;
wdenkfe8c2802002-11-03 00:38:21 +00001278
1279}
1280#endif /* !CONFIG_SMC91111_EXT_PHY */
1281
1282
1283#if SMC_DEBUG > 2
1284static void print_packet( byte * buf, int length )
1285{
wdenk8bde7f72003-06-27 21:31:46 +00001286 int i;
1287 int remainder;
1288 int lines;
wdenkfe8c2802002-11-03 00:38:21 +00001289
wdenk8bde7f72003-06-27 21:31:46 +00001290 printf("Packet of length %d \n", length );
wdenkfe8c2802002-11-03 00:38:21 +00001291
1292#if SMC_DEBUG > 3
wdenk8bde7f72003-06-27 21:31:46 +00001293 lines = length / 16;
1294 remainder = length % 16;
wdenkfe8c2802002-11-03 00:38:21 +00001295
wdenk8bde7f72003-06-27 21:31:46 +00001296 for ( i = 0; i < lines ; i ++ ) {
1297 int cur;
wdenkfe8c2802002-11-03 00:38:21 +00001298
wdenk8bde7f72003-06-27 21:31:46 +00001299 for ( cur = 0; cur < 8; cur ++ ) {
1300 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001301
wdenk8bde7f72003-06-27 21:31:46 +00001302 a = *(buf ++ );
1303 b = *(buf ++ );
1304 printf("%02x%02x ", a, b );
1305 }
1306 printf("\n");
1307 }
1308 for ( i = 0; i < remainder/2 ; i++ ) {
1309 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001310
wdenk8bde7f72003-06-27 21:31:46 +00001311 a = *(buf ++ );
1312 b = *(buf ++ );
1313 printf("%02x%02x ", a, b );
1314 }
1315 printf("\n");
wdenkfe8c2802002-11-03 00:38:21 +00001316#endif
wdenkfe8c2802002-11-03 00:38:21 +00001317}
1318#endif
1319
Ben Warren7194ab82009-10-04 22:37:03 -07001320int smc91111_initialize(u8 dev_num, int base_addr)
wdenk0b97ab12003-06-19 23:58:30 +00001321{
Ben Warren7194ab82009-10-04 22:37:03 -07001322 struct smc91111_priv *priv;
1323 struct eth_device *dev;
wdenk3d3befa2004-03-14 15:06:13 +00001324 int i;
wdenkf39748a2004-06-09 13:37:52 +00001325
Ben Warren7194ab82009-10-04 22:37:03 -07001326 priv = malloc(sizeof(*priv));
1327 if (!priv)
1328 return 0;
1329 dev = malloc(sizeof(*dev));
1330 if (!dev) {
1331 free(priv);
1332 return 0;
wdenkb56ddc62003-09-15 21:14:37 +00001333 }
wdenkf39748a2004-06-09 13:37:52 +00001334
Thomas Chou1ca6d0d2010-10-06 09:16:10 +08001335 memset(dev, 0, sizeof(*dev));
Ben Warren7194ab82009-10-04 22:37:03 -07001336 priv->dev_num = dev_num;
1337 dev->priv = priv;
1338 dev->iobase = base_addr;
1339
1340 swap_to(ETHERNET);
1341 SMC_SELECT_BANK(dev, 1);
1342 for (i = 0; i < 6; ++i)
1343 dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
1344 swap_to(FLASH);
1345
1346 dev->init = smc_init;
1347 dev->halt = smc_halt;
1348 dev->send = smc_send;
1349 dev->recv = smc_rcv;
Thomas Chou1ca6d0d2010-10-06 09:16:10 +08001350 dev->write_hwaddr = smc_write_hwaddr;
Ben Warren7194ab82009-10-04 22:37:03 -07001351 sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
1352
1353 eth_register(dev);
1354 return 0;
wdenk0b97ab12003-06-19 23:58:30 +00001355}