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wdenke63c8ee2004-06-09 21:04:48 +00001/*
2 * (C) Copyright 2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * board/config.h - configuration options, board specific
27 */
28
29/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
30 * U-BOOT port on RPXlite board
31 */
32
33/*
34 * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
35 * U-BOOT port on RPXlite DW version board--RPXlite_DW
36 * June 8 ,2004
37 */
38
39#ifndef __CONFIG_H
40#define __CONFIG_H
41
42/*
43 * High Level Configuration Options
44 * (easy to change)
45 */
46
47/* #define DEBUG 1 */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010048/* #define DEPLOYMENT 1 */
wdenke63c8ee2004-06-09 21:04:48 +000049
50#undef CONFIG_MPC860
51#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */
52#define CONFIG_RPXLITE 1 /* RPXlite DW version board */
53
54#ifdef CONFIG_LCD /* with LCD controller ? */
55#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
56#endif
57
58#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
59#undef CONFIG_8xx_CONS_SMC2
60#undef CONFIG_8xx_CONS_NONE
61#define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */
62
wdenk6225c5d2005-01-09 23:33:49 +000063#ifdef DEBUG
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010064#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
wdenke63c8ee2004-06-09 21:04:48 +000065#else
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010066#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */
wdenk6225c5d2005-01-09 23:33:49 +000067
68#ifdef DEPLOYMENT
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010069#define CONFIG_BOOT_RETRY_TIME -1
wdenk6225c5d2005-01-09 23:33:49 +000070#define CONFIG_AUTOBOOT_KEYED
Stefan Roesef2302d42008-08-06 14:05:38 +020071#define CONFIG_AUTOBOOT_PROMPT \
72 "autoboot in %d seconds (stop with 'st')...\n", bootdelay
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010073#define CONFIG_AUTOBOOT_STOP_STR "st"
wdenk6225c5d2005-01-09 23:33:49 +000074#define CONFIG_ZERO_BOOTDELAY_CHECK
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010075#define CONFIG_RESET_TO_RETRY 1
76#define CONFIG_BOOT_RETRY_MIN 1
wdenkc3d2b4b2005-01-22 18:13:04 +000077#endif /* DEPLOYMENT */
78#endif /* DEBUG */
wdenk6225c5d2005-01-09 23:33:49 +000079
80/* pre-boot commands */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010081#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial"
wdenke63c8ee2004-06-09 21:04:48 +000082
83#undef CONFIG_BOOTARGS
84#define CONFIG_EXTRA_ENV_SETTINGS \
85 "netdev=eth0\0" \
wdenk6225c5d2005-01-09 23:33:49 +000086 "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010087 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
wdenk6225c5d2005-01-09 23:33:49 +000088 "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010089 "addip=setenv bootargs ${bootargs} " \
90 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
91 ":${hostname}:${netdev}:off panic=1\0" \
wdenke63c8ee2004-06-09 21:04:48 +000092 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010093 "bootm ${kernel_addr}\0" \
wdenke63c8ee2004-06-09 21:04:48 +000094 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010095 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
96 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenke63c8ee2004-06-09 21:04:48 +000097 "gatewayip=172.16.115.254\0" \
98 "netmask=255.255.255.0\0" \
wdenk6225c5d2005-01-09 23:33:49 +000099 "kernel_addr=ff040000\0" \
100 "ramdisk_addr=ff200000\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100101 "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \
102 "${filesize};md ${kernel_addr};" \
wdenk6225c5d2005-01-09 23:33:49 +0000103 "echo kernel updating finished\0" \
104 "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100105 "${filesize};md ff000000;" \
wdenk6225c5d2005-01-09 23:33:49 +0000106 "echo u-boot updating finished\0" \
107 "eu=protect off 1:6;era 1:6;reset\0" \
108 "lcd=setenv stdout lcd;setenv stdin lcd\0" \
109 "ser=setenv stdout serial;setenv stdin serial\0" \
110 "verify=no"
wdenk082acfd2005-01-10 00:01:04 +0000111
wdenke63c8ee2004-06-09 21:04:48 +0000112#define CONFIG_BOOTCOMMAND "run flash_self"
113
114#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenke63c8ee2004-06-09 21:04:48 +0000116#undef CONFIG_WATCHDOG /* watchdog disabled */
117#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */
118
Jon Loeliger18225e82007-07-09 21:31:24 -0500119/*
120 * BOOTP options
121 */
122#define CONFIG_BOOTP_SUBNETMASK
123#define CONFIG_BOOTP_GATEWAY
124#define CONFIG_BOOTP_HOSTNAME
125#define CONFIG_BOOTP_BOOTPATH
126#define CONFIG_BOOTP_BOOTFILESIZE
127
wdenke63c8ee2004-06-09 21:04:48 +0000128
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100129#if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you
130 don't want the advanced function */
Wolfgang Denk0a3471f2006-03-12 16:57:35 +0100131
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500132
133/*
134 * Command line configuration.
135 */
136#include <config_cmd_default.h>
137
138#define CONFIG_CMD_ASKENV
139#define CONFIG_CMD_JFFS2
140#define CONFIG_CMD_PING
141#define CONFIG_CMD_ELF
142#define CONFIG_CMD_REGINFO
143#define CONFIG_CMD_DHCP
144
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100145#ifdef CONFIG_SPLASH_SCREEN
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500146#define CONFIG_CMD_BMP
147#endif
148
Wolfgang Denk0a3471f2006-03-12 16:57:35 +0100149
150/* test-only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
152#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
Wolfgang Denk0a3471f2006-03-12 16:57:35 +0100153
154#define CONFIG_NETCONSOLE
155
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100156#endif /* 1 */
Wolfgang Denk0a3471f2006-03-12 16:57:35 +0100157
wdenke63c8ee2004-06-09 21:04:48 +0000158/*
159 * Miscellaneous configurable options
160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_LONGHELP /* undef to save memory */
162#define CONFIG_SYS_PROMPT "u-boot>" /* Monitor Command Prompt */
wdenke63c8ee2004-06-09 21:04:48 +0000163
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500164#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke63c8ee2004-06-09 21:04:48 +0000166#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke63c8ee2004-06-09 21:04:48 +0000168#endif
wdenkc3d2b4b2005-01-22 18:13:04 +0000169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
171#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
172#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke63c8ee2004-06-09 21:04:48 +0000173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */
175#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
176#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenke63c8ee2004-06-09 21:04:48 +0000177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
179#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke63c8ee2004-06-09 21:04:48 +0000180
181/*
182 * Low Level Configuration Settings
183 * (address mappings, register initial values, etc.)
184 * You should know what you are doing if you make changes here.
185 */
186/*-----------------------------------------------------------------------
187 * Internal Memory Mapped Register
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_IMMR 0xFA200000
wdenke63c8ee2004-06-09 21:04:48 +0000190
191/*-----------------------------------------------------------------------
192 * Definitions for initial stack pointer and data area (in DPRAM)
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
195#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
196#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
197#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
198#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke63c8ee2004-06-09 21:04:48 +0000199
200/*-----------------------------------------------------------------------
201 * Start addresses for the final memory configuration
202 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke63c8ee2004-06-09 21:04:48 +0000204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_SDRAM_BASE 0x00000000
206#define CONFIG_SYS_FLASH_BASE 0xFF000000
wdenke63c8ee2004-06-09 21:04:48 +0000207
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500208#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenke63c8ee2004-06-09 21:04:48 +0000210#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
wdenke63c8ee2004-06-09 21:04:48 +0000212#endif
wdenkc3d2b4b2005-01-22 18:13:04 +0000213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_MONITOR_BASE 0xFF000000
215#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke63c8ee2004-06-09 21:04:48 +0000216
217/*
218 * For booting Linux, the board info and command line data
219 * have to be in the first 8 MB of memory, since this is
220 * the maximum mapped by the Linux kernel during initialization.
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke63c8ee2004-06-09 21:04:48 +0000223
224/*-----------------------------------------------------------------------
225 * FLASH organization
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
228#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
229#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
230#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenke63c8ee2004-06-09 21:04:48 +0000231
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200232#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200233#define CONFIG_ENV_ADDR 0xFA000100
234#define CONFIG_ENV_SIZE 0x1000
wdenke63c8ee2004-06-09 21:04:48 +0000235#else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200236#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200237#define CONFIG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
238#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200239#endif /* CONFIG_ENV_IS_IN_NVRAM */
wdenke63c8ee2004-06-09 21:04:48 +0000240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
wdenk082acfd2005-01-10 00:01:04 +0000242
wdenke63c8ee2004-06-09 21:04:48 +0000243/*-----------------------------------------------------------------------
244 * Cache Configuration
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500247#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenke63c8ee2004-06-09 21:04:48 +0000249#endif
250
251/*-----------------------------------------------------------------------
252 * SYPCR - System Protection Control 32-bit 12-35
253 * SYPCR can only be written once after reset!
254 *-----------------------------------------------------------------------
255 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
256 */
257#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenke63c8ee2004-06-09 21:04:48 +0000259 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
260#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenke63c8ee2004-06-09 21:04:48 +0000262#endif /* We can get SYPCR: 0xFFFF0689. */
263
264/*-----------------------------------------------------------------------
265 * SIUMCR - SIU Module Configuration 32-bit 12-30
266 *-----------------------------------------------------------------------
267 * PCMCIA config., multi-function pin tri-state
268 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */
wdenke63c8ee2004-06-09 21:04:48 +0000270
271/*---------------------------------------------------------------------
272 * TBSCR - Time Base Status and Control 16-bit 12-16
273 *---------------------------------------------------------------------
274 * Clear Reference Interrupt Status, Timebase freezing enabled
275 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
wdenke63c8ee2004-06-09 21:04:48 +0000277/* TBSCR: 0x00C3 [SAM] */
278
279/*-----------------------------------------------------------------------
280 * RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18
281 *-----------------------------------------------------------------------
282 * [RTC enabled but not stopped on FRZ]
283 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */
wdenke63c8ee2004-06-09 21:04:48 +0000285
286/*-----------------------------------------------------------------------
287 * PISCR - Periodic Interrupt Status and Control 16-bit 12-23
288 *-----------------------------------------------------------------------
289 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
290 * [Periodic timer enabled,Periodic timer interrupt disable. ]
291 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */
wdenke63c8ee2004-06-09 21:04:48 +0000293
294/*-----------------------------------------------------------------------
295 * PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7
296 *-----------------------------------------------------------------------
297 * Reset PLL lock status sticky bit, timer expired status bit and timer
298 * interrupt status bit
299 */
300/* up to 64 MHz we use a 1:2 clock */
301#if defined(RPXlite_64MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */
wdenke63c8ee2004-06-09 21:04:48 +0000303#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
wdenke63c8ee2004-06-09 21:04:48 +0000305#endif
306
307/*-----------------------------------------------------------------------
308 * SCCR - System Clock and reset Control Register 5-3
309 *-----------------------------------------------------------------------
310 * Set clock output, timebase and RTC source and divider,
311 * power management and some other internal clocks
312 */
313#define SCCR_MASK SCCR_EBDF00
wdenk30d56fa2004-10-09 22:44:59 +0000314/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */
315#if defined(RPXlite_64MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */
wdenk6225c5d2005-01-09 23:33:49 +0000317#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */
wdenk6225c5d2005-01-09 23:33:49 +0000319#endif
wdenke63c8ee2004-06-09 21:04:48 +0000320
wdenke63c8ee2004-06-09 21:04:48 +0000321/*-----------------------------------------------------------------------
322 * PCMCIA stuff
323 *-----------------------------------------------------------------------
324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
326#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
327#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
328#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
329#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
330#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
331#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
332#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenke63c8ee2004-06-09 21:04:48 +0000333
334/*-----------------------------------------------------------------------
335 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
336 *-----------------------------------------------------------------------
337 */
338#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
339
340#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
341#undef CONFIG_IDE_LED /* LED for ide not supported */
342#undef CONFIG_IDE_RESET /* reset for ide not supported */
343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
345#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenke63c8ee2004-06-09 21:04:48 +0000346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
348#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenke63c8ee2004-06-09 21:04:48 +0000349
350/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenke63c8ee2004-06-09 21:04:48 +0000352
353/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenke63c8ee2004-06-09 21:04:48 +0000355
356/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenke63c8ee2004-06-09 21:04:48 +0000358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_DER 0
wdenke63c8ee2004-06-09 21:04:48 +0000360
361/*
362 * Init Memory Controller:
363 *
364 * BR0 and OR0 (FLASH)
365 */
366#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_PRELIM_OR_AM 0xFC000000 /* OR addr mask */
wdenke63c8ee2004-06-09 21:04:48 +0000368
369/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
371#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
372#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
wdenke63c8ee2004-06-09 21:04:48 +0000373
374/*
375 * BR1 and OR1 (SDRAM)
376 *
377 */
378#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
379#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */
380
381/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
383#define CONFIG_SYS_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK))
384#define CONFIG_SYS_OR1_PRELIM ( CONFIG_SYS_OR_AM_SDRAM | CONFIG_SYS_OR_TIMING_SDRAM )
385#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke63c8ee2004-06-09 21:04:48 +0000386
387/* RPXlite mem setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */
389#define CONFIG_SYS_OR3_PRELIM 0xFF7F8900
390#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
391#define CONFIG_SYS_OR4_PRELIM 0xFFFE0040
wdenke63c8ee2004-06-09 21:04:48 +0000392
393/*
394 * Memory Periodic Timer Prescaler
395 */
396/* periodic timer for refresh */
397#if defined(RPXlite_64MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_MAMR_PTA 32
wdenke63c8ee2004-06-09 21:04:48 +0000399#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_MAMR_PTA 20
wdenke63c8ee2004-06-09 21:04:48 +0000401#endif
402
403/*
404 * Refresh clock Prescalar
405 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2
wdenke63c8ee2004-06-09 21:04:48 +0000407
408/*
409 * MAMR settings for SDRAM
410 */
411
412/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenke63c8ee2004-06-09 21:04:48 +0000414 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415/* CONFIG_SYS_MAMR_9COL:0x20904000 @ 64MHz */
wdenke63c8ee2004-06-09 21:04:48 +0000416
417/*
418 * Internal Definitions
419 *
420 * Boot Flags
421 */
422#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
423#define BOOTFLAG_WARM 0x02 /* Software reboot */
424
425/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
426/* Configuration variable added by yooth. */
427/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
428/*
429 * BCSRx
430 *
431 * Board Status and Control Registers
432 *
433 */
434#define BCSR0 0xFA400000
435#define BCSR1 0xFA400001
436#define BCSR2 0xFA400002
437#define BCSR3 0xFA400003
438
439#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
440#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
441#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
442#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
443#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
444#define BCSR0_COLTEST 0x20
445#define BCSR0_ETHLPBK 0x40
446#define BCSR0_ETHEN 0x80
447
448#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
449#define BCSR1_PCVCTL6 0x02
450#define BCSR1_PCVCTL5 0x04
451#define BCSR1_PCVCTL4 0x08
452#define BCSR1_IPB5SEL 0x10
453
454#define BCSR1_SMC1CTS 0x40 /* Added by SAM. */
455#define BCSR1_SMC1TRS 0x80 /* Added by SAM. */
456
457#define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */
458#define BCSR2_ENBRG1 0x04 /* Added by SAM. */
459
460#define BCSR2_ENPA5HDR 0x08 /* USB Control */
461#define BCSR2_ENUSBCLK 0x10
462#define BCSR2_USBPWREN 0x20
463#define BCSR2_USBSPD 0x40
464#define BCSR2_USBSUSP 0x80
465
466#define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */
467#define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */
468#define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */
469#define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */
470
471#define BCSR3_D27 0x10 /* Dip Switch settings */
472#define BCSR3_D26 0x20
473#define BCSR3_D25 0x40
474#define BCSR3_D24 0x80
475
476/*
477 * Environment setting
478 */
479#define CONFIG_ETHADDR 00:10:EC:00:37:5B
480#define CONFIG_IPADDR 172.16.115.7
481#define CONFIG_SERVERIP 172.16.115.6
482#define CONFIG_ROOTPATH /workspace/myfilesystem/target/
483#define CONFIG_BOOTFILE uImage.rpxusb
Wolfgang Denk0a3471f2006-03-12 16:57:35 +0100484#define CONFIG_HOSTNAME LITE_H1_DW
wdenke63c8ee2004-06-09 21:04:48 +0000485
486#endif /* __CONFIG_H */