Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 2 | /* |
3 | * (C) Copyright 2011 | ||||
4 | * Graeme Russ, <graeme.russ@gmail.com> | ||||
Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 5 | */ |
Bin Meng | c17ca6b | 2015-08-13 00:29:10 -0700 | [diff] [blame] | 6 | |
Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 7 | #include <common.h> |
Masahiro Yamada | 1221ce4 | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 8 | #include <linux/errno.h> |
Simon Glass | db55bd7 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 9 | #include <asm/mtrr.h> |
Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 10 | |
11 | DECLARE_GLOBAL_DATA_PTR; | ||||
12 | |||||
Simon Glass | 5e98947 | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 13 | /* Get the top of usable RAM */ |
14 | __weak ulong board_get_usable_ram_top(ulong total_size) | ||||
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 15 | { |
Simon Glass | 5e98947 | 2013-02-28 19:26:10 +0000 | [diff] [blame] | 16 | return gd->ram_size; |
17 | } | ||||
18 | |||||
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 19 | int init_cache_f_r(void) |
20 | { | ||||
Simon Glass | 2eff989 | 2017-01-16 07:03:46 -0700 | [diff] [blame] | 21 | #if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) |
Simon Glass | db55bd7 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 22 | int ret; |
23 | |||||
24 | ret = mtrr_commit(false); | ||||
Bin Meng | 3b621cc | 2015-01-22 11:29:41 +0800 | [diff] [blame] | 25 | /* If MTRR MSR is not implemented by the processor, just ignore it */ |
26 | if (ret && ret != -ENOSYS) | ||||
Simon Glass | db55bd7 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 27 | return ret; |
28 | #endif | ||||
Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 29 | /* Initialise the CPU cache(s) */ |
30 | return init_cache(); | ||||
31 | } |