blob: 3ed4bab9e376e2885dc03a5ac36e76dee29c8703 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001# SPDX-License-Identifier: GPL-2.0+
Max Filippovb25732c2016-08-07 08:53:00 +03002#
3# (C) Copyright 2016 Cadence Design Systems Inc.
Max Filippovb25732c2016-08-07 08:53:00 +03004
Kever Yang09259fc2019-04-02 20:41:25 +08005obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o
Mario Six76fdad12018-08-06 10:23:35 +02006obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
7obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
8obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
9obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
Michal Simek0d832b32018-07-13 11:04:56 +020010obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
Rasmus Villemoes875669d2019-12-13 15:47:58 +000011obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
Michal Simekcae39ae2018-07-13 17:00:13 +020012obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
Masahiro Yamada573a3812017-04-14 11:10:24 +090013obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
Simon Goldschmidt1f166882019-07-15 21:47:53 +020014obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
Simon Goldschmidt690c1292019-07-15 21:47:54 +020015obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
Andreas Dannenberg694b0522018-08-27 15:57:46 +053016obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
Álvaro Fernández Rojase3889692017-04-25 00:39:14 +020017obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
Álvaro Fernández Rojas17a0c142017-05-16 18:29:13 +020018obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
Weijie Gaocaf70922020-04-21 09:28:29 +020019obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
Simon Glassff7abb82019-09-25 08:11:24 -060020obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
Chris Zankel7e270ec2016-08-10 18:36:48 +030021obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o