Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 513bbe1b1720682e6de0aba2d9db5e60f3a428bb / . / cpu / mcf5445x / start.S
blob: d2d44391513bae6269780cb4a37a9dda4ec60cc7 [file] [log] [blame]
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
Peter Tyser561858e2008-11-03 09:30:59 -0600[diff] [blame]25#include <timestamp.h>
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]26#include "version.h"
27
28#ifndef CONFIG_IDENT_STRING
29#define CONFIG_IDENT_STRING ""
30#endif
31
32/* last three long word reserved for cache status */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]33#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
34#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
35#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]36
37#define _START _start
38#define _FAULT _fault
39
40#define SAVE_ALL \
41 move.w #0x2700,%sr; /* disable intrs */ \
42 subl #60,%sp; /* space for 15 regs */ \
43 moveml %d0-%d7/%a0-%a6,%sp@;
44
45#define RESTORE_ALL \
46 moveml %sp@,%d0-%d7/%a0-%a6; \
47 addl #60,%sp; /* space for 15 regs */ \
48 rte;
49
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]50#if defined(CONFIG_CF_SBF)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]51#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
52#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]53#endif
54
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]55.text
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]56
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]57/*
58 * Vector table. This is used for initial platform startup.
59 * These vectors are to catch any un-intended traps.
60 */
61_vectors:
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]62#if defined(CONFIG_CF_SBF)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]63
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]64INITSP: .long 0 /* Initial SP */
65INITPC: .long ASM_DRAMINIT /* Initial PC */
66
67#else
68
69INITSP: .long 0 /* Initial SP */
70INITPC: .long _START /* Initial PC */
71
72#endif
73
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]74vector02: .long _FAULT /* Access Error */
75vector03: .long _FAULT /* Address Error */
76vector04: .long _FAULT /* Illegal Instruction */
77vector05: .long _FAULT /* Reserved */
78vector06: .long _FAULT /* Reserved */
79vector07: .long _FAULT /* Reserved */
80vector08: .long _FAULT /* Privilege Violation */
81vector09: .long _FAULT /* Trace */
82vector0A: .long _FAULT /* Unimplemented A-Line */
83vector0B: .long _FAULT /* Unimplemented F-Line */
84vector0C: .long _FAULT /* Debug Interrupt */
85vector0D: .long _FAULT /* Reserved */
86vector0E: .long _FAULT /* Format Error */
87vector0F: .long _FAULT /* Unitialized Int. */
88
89/* Reserved */
90vector10_17:
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92
93vector18: .long _FAULT /* Spurious Interrupt */
94vector19: .long _FAULT /* Autovector Level 1 */
95vector1A: .long _FAULT /* Autovector Level 2 */
96vector1B: .long _FAULT /* Autovector Level 3 */
97vector1C: .long _FAULT /* Autovector Level 4 */
98vector1D: .long _FAULT /* Autovector Level 5 */
99vector1E: .long _FAULT /* Autovector Level 6 */
100vector1F: .long _FAULT /* Autovector Level 7 */
101
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]102#if !defined(CONFIG_CF_SBF)
103
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]104/* TRAP #0 - #15 */
105vector20_2F:
106.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108
109/* Reserved */
110vector30_3F:
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113
114vector64_127:
115.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
116.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
117.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
119.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
120.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
121.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
122.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
123
124vector128_191:
125.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
126.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
127.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
128.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
129.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
130.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
131.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
132.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
133
134vector192_255:
135.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
136.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
137.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
138.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
139.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
140.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
141.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
142.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]143#endif
144
145#if defined(CONFIG_CF_SBF)
146 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
147asm_sbf_img_hdr:
148 .long 0x00000000 /* checksum, not yet implemented */
149 .long 0x00030000 /* image length */
150 .long TEXT_BASE /* image to be relocated at */
151
152asm_dram_init:
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]153 move.w #0x2700,%sr /* Mask off Interrupt */
154
155 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
156 movec %d0, %VBR
157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]158 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]159 movec %d0, %RAMBAR1
160
161 /* initialize general use internal ram */
162 move.l #0, %d0
163 move.l #(CACR_STATUS), %a1 /* CACR */
164 move.l #(ICACHE_STATUS), %a2 /* icache */
165 move.l #(DCACHE_STATUS), %a3 /* dcache */
166 move.l %d0, (%a1)
167 move.l %d0, (%a2)
168 move.l %d0, (%a3)
169
170 /* invalidate and disable cache */
171 move.l #0x01004100, %d0 /* Invalidate cache cmd */
172 movec %d0, %CACR /* Invalidate cache */
173 move.l #0, %d0
174 movec %d0, %ACR0
175 movec %d0, %ACR1
176 movec %d0, %ACR2
177 movec %d0, %ACR3
178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]179 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]180 clr.l %sp@-
181
182 /* Must disable global address */
183 move.l #0xFC008000, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]184 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]185 move.l #0xFC008008, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]186 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]187 move.l #0xFC008004, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]188 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]189
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]190 /* Dram Initialization a1, a2, and d0 */
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]191 /* mscr sdram */
192 move.l #0xFC0A4074, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]193 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]194 nop
195
196 /* SDRAM Chip 0 and 1 */
197 move.l #0xFC0B8110, %a1
198 move.l #0xFC0B8114, %a2
199
200 /* calculate the size */
201 move.l #0x13, %d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]202 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
203#ifdef CONFIG_SYS_SDRAM_BASE1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]204 lsr.l #1, %d2
205#endif
206
207dramsz_loop:
208 lsr.l #1, %d2
209 add.l #1, %d1
210 cmp.l #1, %d2
211 bne dramsz_loop
212
213 /* SDRAM Chip 0 and 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]214 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]215 or.l %d1, (%a1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]216#ifdef CONFIG_SYS_SDRAM_BASE1
217 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]218 or.l %d1, (%a2)
219#endif
220 nop
221
222 /* dram cfg1 and cfg2 */
223 move.l #0xFC0B8008, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]224 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]225 nop
226 move.l #0xFC0B800C, %a2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]227 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]228 nop
229
230 move.l #0xFC0B8000, %a1 /* Mode */
231 move.l #0xFC0B8004, %a2 /* Ctrl */
232
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]233 /* Issue PALL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]234 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]235 nop
236
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]237#ifdef CONFIG_M54455EVB
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]238 /* Issue LEMR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]239 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]240 nop
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]241 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]242 nop
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]243#endif
244
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]245 move.l #1000, %d1
246 jsr asm_delay
247
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]248 /* Issue PALL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]249 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]250 nop
251
252 /* Perform two refresh cycles */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]253 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]254 nop
255 move.l %d0, (%a2)
256 move.l %d0, (%a2)
257 nop
258
259#ifdef CONFIG_M54455EVB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]260 move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]261 nop
262#elif defined(CONFIG_M54451EVB)
263 /* Issue LEMR */
TsiChung Liewc3a9e632009-02-18 11:49:31 +0000[diff] [blame]264 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]265 nop
TsiChung Liewc3a9e632009-02-18 11:49:31 +0000[diff] [blame]266 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]267#endif
268
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]269 move.l #500, %d1
270 jsr asm_delay
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]271
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]272 move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
273 and.l #0x7FFFFFFF, %d1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]274#ifdef CONFIG_M54455EVB
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]275 or.l #0x10000C00, %d1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]276#elif defined(CONFIG_M54451EVB)
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]277 or.l #0x10000C00, %d1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]278#endif
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]279 move.l %d1, (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]280 nop
281
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]282 move.l #2000, %d1
283 jsr asm_delay
284
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]285 /*
286 * DSPI Initialization
287 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
288 * a1 - dspi status
289 * a2 - dtfr
290 * a3 - drfr
291 * a4 - Dst addr
292 */
293 /* Enable pins for DSPI mode - chip-selects are enabled later */
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]294asm_dspi_init:
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]295 move.l #0xFC0A4063, %a0
296 move.b #0x7F, (%a0)
297
298 /* Configure DSPI module */
299 move.l #0xFC05C000, %a0
300 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
301
302 move.l #0xFC05C00C, %a0
303 move.l #0x3E000011, (%a0)
304
305 move.l #0xFC05C034, %a2 /* dtfr */
306 move.l #0xFC05C03B, %a3 /* drfr */
307
308 move.l #(ASM_SBF_IMG_HDR + 4), %a1
309 move.l (%a1)+, %d5
310 move.l (%a1), %a4
311
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]312 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
313 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]314
315 move.l #0xFC05C02C, %a1 /* dspi status */
316
317 /* Issue commands and address */
318 move.l #0x8002000B, %d2 /* Fast Read Cmd */
319 jsr asm_dspi_wr_status
320 jsr asm_dspi_rd_status
321
322 move.l #0x80020000, %d2 /* Address byte 2 */
323 jsr asm_dspi_wr_status
324 jsr asm_dspi_rd_status
325
326 move.l #0x80020000, %d2 /* Address byte 1 */
327 jsr asm_dspi_wr_status
328 jsr asm_dspi_rd_status
329
330 move.l #0x80020000, %d2 /* Address byte 0 */
331 jsr asm_dspi_wr_status
332 jsr asm_dspi_rd_status
333
334 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
335 jsr asm_dspi_wr_status
336 jsr asm_dspi_rd_status
337
338 /* Transfer serial boot header to sram */
339asm_dspi_rd_loop1:
340 move.l #0x80020000, %d2
341 jsr asm_dspi_wr_status
342 jsr asm_dspi_rd_status
343
344 move.b %d1, (%a0) /* read, copy to dst */
345
346 add.l #1, %a0 /* inc dst by 1 */
347 sub.l #1, %d4 /* dec cnt by 1 */
348 bne asm_dspi_rd_loop1
349
350 /* Transfer u-boot from serial flash to memory */
351asm_dspi_rd_loop2:
352 move.l #0x80020000, %d2
353 jsr asm_dspi_wr_status
354 jsr asm_dspi_rd_status
355
356 move.b %d1, (%a4) /* read, copy to dst */
357
358 add.l #1, %a4 /* inc dst by 1 */
359 sub.l #1, %d5 /* dec cnt by 1 */
360 bne asm_dspi_rd_loop2
361
362 move.l #0x00020000, %d2 /* Terminate */
363 jsr asm_dspi_wr_status
364 jsr asm_dspi_rd_status
365
366 /* jump to memory and execute */
367 move.l #(TEXT_BASE + 0x400), %a0
368 jmp (%a0)
369
370asm_dspi_wr_status:
371 move.l (%a1), %d0 /* status */
372 and.l #0x0000F000, %d0
373 cmp.l #0x00003000, %d0
374 bgt asm_dspi_wr_status
375
376 move.l %d2, (%a2)
377 rts
378
379asm_dspi_rd_status:
380 move.l (%a1), %d0 /* status */
381 and.l #0x000000F0, %d0
382 lsr.l #4, %d0
383 cmp.l #0, %d0
384 beq asm_dspi_rd_status
385
386 move.b (%a3), %d1
387 rts
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]388
389asm_delay:
390 nop
391 subq.l #1, %d1
392 bne asm_delay
393 rts
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]394#endif /* CONFIG_CF_SBF */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]395
396 .text
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]397 . = 0x400
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]398 .globl _start
399_start:
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]400#if !defined(CONFIG_CF_SBF)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]401 nop
402 nop
403 move.w #0x2700,%sr /* Mask off Interrupt */
404
405 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]406 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]407 movec %d0, %VBR
408
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]409 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew225a24b2007-11-07 18:00:54 -0600[diff] [blame]410 movec %d0, %RAMBAR1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]411
412 /* initialize general use internal ram */
413 move.l #0, %d0
414 move.l #(CACR_STATUS), %a1 /* CACR */
415 move.l #(ICACHE_STATUS), %a2 /* icache */
416 move.l #(DCACHE_STATUS), %a3 /* dcache */
417 move.l %d0, (%a1)
418 move.l %d0, (%a2)
419 move.l %d0, (%a3)
420
421 /* invalidate and disable cache */
422 move.l #0x01004100, %d0 /* Invalidate cache cmd */
423 movec %d0, %CACR /* Invalidate cache */
424 move.l #0, %d0
425 movec %d0, %ACR0
426 movec %d0, %ACR1
427 movec %d0, %ACR2
428 movec %d0, %ACR3
429
430 /* set stackpointer to end of internal ram to get some stackspace for
431 the first c-code */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]432 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]433 clr.l %sp@-
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]434#endif
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]435
436 move.l #__got_start, %a5 /* put relocation table address to a5 */
437
438 bsr cpu_init_f /* run low-level CPU init code (from flash) */
439 bsr board_init_f /* run low-level board init code (from flash) */
440
441 /* board_init_f() does not return */
442
443/*------------------------------------------------------------------------------*/
444
445/*
446 * void relocate_code (addr_sp, gd, addr_moni)
447 *
448 * This "function" does not return, instead it continues in RAM
449 * after relocating the monitor code.
450 *
451 * r3 = dest
452 * r4 = src
453 * r5 = length in bytes
454 * r6 = cachelinesize
455 */
456 .globl relocate_code
457relocate_code:
458 link.w %a6,#0
459 move.l 8(%a6), %sp /* set new stack pointer */
460
461 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
462 move.l 16(%a6), %a0 /* Save copy of Destination Address */
463
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]464 move.l #CONFIG_SYS_MONITOR_BASE, %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]465 move.l #__init_end, %a2
466 move.l %a0, %a3
467
468 /* copy the code to RAM */
4691:
470 move.l (%a1)+, (%a3)+
471 cmp.l %a1,%a2
472 bgt.s 1b
473
474/*
475 * We are done. Do not return, instead branch to second part of board
476 * initialization, now running from RAM.
477 */
478 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]479 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]480 jmp (%a1)
481
482in_ram:
483
484clear_bss:
485 /*
486 * Now clear BSS segment
487 */
488 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]489 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]490 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]491 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]4926:
493 clr.l (%a1)+
494 cmp.l %a1,%d1
495 bgt.s 6b
496
497 /*
498 * fix got table in RAM
499 */
500 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]501 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]502 move.l %a1,%a5 /* * fix got pointer register a5 */
503
504 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]505 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]506
5077:
508 move.l (%a1),%d1
509 sub.l #_start,%d1
510 add.l %a0,%d1
511 move.l %d1,(%a1)+
512 cmp.l %a2, %a1
513 bne 7b
514
515 /* calculate relative jump to board_init_r in ram */
516 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]517 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]518
519 /* set parameters for board_init_r */
520 move.l %a0,-(%sp) /* dest_addr */
521 move.l %d0,-(%sp) /* gd */
522 jsr (%a1)
523
524/*------------------------------------------------------------------------------*/
525/* exception code */
526 .globl _fault
527_fault:
TsiChung Liew3b1e8ac2008-06-18 19:12:13 -0500[diff] [blame]528 bra _fault
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]529 .globl _exc_handler
530
531_exc_handler:
532 SAVE_ALL
533 movel %sp,%sp@-
534 bsr exc_handler
535 addql #4,%sp
536 RESTORE_ALL
537
538 .globl _int_handler
539_int_handler:
540 SAVE_ALL
541 movel %sp,%sp@-
542 bsr int_handler
543 addql #4,%sp
544 RESTORE_ALL
545
546/*------------------------------------------------------------------------------*/
547/* cache functions */
548 .globl icache_enable
549icache_enable:
550 move.l #(CACR_STATUS), %a1 /* read CACR Status */
551 move.l (%a1), %d1
552
553 move.l #0x00040100, %d0 /* Invalidate icache */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]554 movec %d0, %CACR
555
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]556 move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup icache */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]557 movec %d0, %ACR2
558
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]559 move.l #0x04088020, %d0 /* Enable bcache and icache */
560 movec %d0, %CACR
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]561
562 move.l #(ICACHE_STATUS), %a1
563 moveq #1, %d0
564 move.l %d0, (%a1)
565 rts
566
567 .globl icache_disable
568icache_disable:
569 move.l #(CACR_STATUS), %a1 /* read CACR Status */
570 move.l (%a1), %d0
571
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]572 move.l #0xFFF77BFF, %d0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]573 or.l #0x00040100, %d0 /* Setup cache mask */
574 movec %d0, %CACR /* Invalidate icache */
575 clr.l %d0
576 movec %d0, %ACR2
577 movec %d0, %ACR3
578
579 move.l #(ICACHE_STATUS), %a1
580 moveq #0, %d0
581 move.l %d0, (%a1)
582 rts
583
584 .globl icache_status
585icache_status:
586 move.l #(ICACHE_STATUS), %a1
587 move.l (%a1), %d0
588 rts
589
590 .globl icache_invalid
591icache_invalid:
592 move.l #(CACR_STATUS), %a1 /* read CACR Status */
593 move.l (%a1), %d0
594
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]595 move.l #0x00040100, %d0 /* Invalidate icache */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]596 movec %d0, %CACR /* Enable and invalidate cache */
597 rts
598
599 .globl dcache_enable
600dcache_enable:
601 move.l #(CACR_STATUS), %a1 /* read CACR Status */
602 move.l (%a1), %d1
603
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]604 move.l #0x01040100, %d0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]605 movec %d0, %CACR /* Invalidate dcache */
606
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]607 move.l #0x80088020, %d0 /* Enable bcache and icache */
608 movec %d0, %CACR
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]609
610 move.l #(DCACHE_STATUS), %a1
611 moveq #1, %d0
612 move.l %d0, (%a1)
613 rts
614
615 .globl dcache_disable
616dcache_disable:
617 move.l #(CACR_STATUS), %a1 /* read CACR Status */
618 move.l (%a1), %d0
619
620 and.l #0x7FFFFFFF, %d0
621 or.l #0x01000000, %d0 /* Setup cache mask */
622 movec %d0, %CACR /* Disable dcache */
623 clr.l %d0
624 movec %d0, %ACR0
625 movec %d0, %ACR1
626
627 move.l #(DCACHE_STATUS), %a1
628 moveq #0, %d0
629 move.l %d0, (%a1)
630 rts
631
632 .globl dcache_invalid
633dcache_invalid:
634 move.l #(CACR_STATUS), %a1 /* read CACR Status */
635 move.l (%a1), %d0
636
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]637 move.l #0x81088020, %d0 /* Setup cache mask */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]638 movec %d0, %CACR /* Enable and invalidate cache */
639 rts
640
641 .globl dcache_status
642dcache_status:
643 move.l #(DCACHE_STATUS), %a1
644 move.l (%a1), %d0
645 rts
646
647/*------------------------------------------------------------------------------*/
648
649 .globl version_string
650version_string:
651 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -0600[diff] [blame]652 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]653 .ascii CONFIG_IDENT_STRING, "\0"
TsiChung Liew9b464322008-03-28 08:47:45 -0500[diff] [blame]654 .align 4