blob: 91d03951dbbebc604d121871bf930b8be667ebd0 [file] [log] [blame]
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +01001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <common.h>
7#include <asm/io.h>
8#include <asm/addrspace.h>
9#include <asm/types.h>
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +010010#include <spi.h>
Lars Povlsen4deb0962019-01-02 09:52:26 +010011#include <led.h>
Gregory CLEMENT2f8d0672019-01-17 17:07:14 +010012#include <wait_bit.h>
Horatiu Vultur06d270c2019-04-24 11:27:58 +020013#include <miiphy.h>
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +010014
15DECLARE_GLOBAL_DATA_PTR;
16
Lars Povlsene9f14922018-12-20 09:56:05 +010017enum {
18 BOARD_TYPE_PCB120 = 0xAABBCC00,
19 BOARD_TYPE_PCB123,
20};
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +010021
Gregory CLEMENT2f8d0672019-01-17 17:07:14 +010022void mscc_switch_reset(bool enter)
23{
24 /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
25 mscc_gpio_set_alternate(19, 2);
26
27 debug("applying SwC reset\n");
28
29 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
30 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
31
32 if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
33 PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
34 pr_err("Tiemout while waiting for switch reset\n");
35
36 /*
37 * Reset GPIO19 mode back as regular GPIO, output, high (DDR
38 * not reset) (Order is important)
39 */
40 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
41 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
42 mscc_gpio_set_alternate(19, 0);
43}
44
Horatiu Vultur06d270c2019-04-24 11:27:58 +020045int board_phy_config(struct phy_device *phydev)
46{
47 if (gd->board_type == BOARD_TYPE_PCB123)
48 return 0;
49
50 phy_write(phydev, 0, 31, 0x10);
51 phy_write(phydev, 0, 18, 0x80F0);
52 while (phy_read(phydev, 0, 18) & 0x8000)
53 ;
54 phy_write(phydev, 0, 31, 0);
55
56 return 0;
57}
58
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +010059void board_debug_uart_init(void)
60{
61 /* too early for the pinctrl driver, so configure the UART pins here */
Lars Povlsene9f14922018-12-20 09:56:05 +010062 mscc_gpio_set_alternate(6, 1);
63 mscc_gpio_set_alternate(7, 1);
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +010064}
65
66int board_early_init_r(void)
67{
68 /* Prepare SPI controller to be used in master mode */
69 writel(0, BASE_CFG + ICPU_SW_MODE);
70 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
71 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
72 ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
73
74 /* Address of boot parameters */
75 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
Lars Povlsen4deb0962019-01-02 09:52:26 +010076
77 /* LED setup */
78 if (IS_ENABLED(CONFIG_LED))
79 led_default_state();
80
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +010081 return 0;
82}
Lars Povlsene9f14922018-12-20 09:56:05 +010083
84static void do_board_detect(void)
85{
86 u16 dummy = 0;
87
88 /* Enable MIIM */
89 mscc_gpio_set_alternate(14, 1);
90 mscc_gpio_set_alternate(15, 1);
91 if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
92 gd->board_type = BOARD_TYPE_PCB120;
93 else
94 gd->board_type = BOARD_TYPE_PCB123;
95}
96
97#if defined(CONFIG_MULTI_DTB_FIT)
98int board_fit_config_name_match(const char *name)
99{
100 if (gd->board_type == BOARD_TYPE_PCB120 &&
101 strcmp(name, "ocelot_pcb120") == 0)
102 return 0;
103
104 if (gd->board_type == BOARD_TYPE_PCB123 &&
105 strcmp(name, "ocelot_pcb123") == 0)
106 return 0;
107
108 return -1;
109}
110#endif
111
112#if defined(CONFIG_DTB_RESELECT)
113int embedded_dtb_select(void)
114{
115 do_board_detect();
116 fdtdec_setup();
117
118 return 0;
119}
120#endif