Bin Meng | 117a433 | 2018-09-26 06:55:06 -0700 | [diff] [blame] | 1 | menu "RISC-V architecture" |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 2 | depends on RISCV |
3 | |||||
4 | config SYS_ARCH | ||||
5 | default "riscv" | ||||
6 | |||||
7 | choice | ||||
8 | prompt "Target select" | ||||
9 | optional | ||||
10 | |||||
Rick Chen | 6f4dd62 | 2018-05-29 09:54:40 +0800 | [diff] [blame] | 11 | config TARGET_AX25_AE350 |
12 | bool "Support ax25-ae350" | ||||
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 13 | |
Bin Meng | 510e379 | 2018-09-26 06:55:21 -0700 | [diff] [blame] | 14 | config TARGET_QEMU_VIRT |
15 | bool "Support QEMU Virt Board" | ||||
16 | |||||
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 17 | endchoice |
18 | |||||
Rick Chen | 52923c6 | 2018-11-07 09:34:06 +0800 | [diff] [blame^] | 19 | # board-specific options below |
Rick Chen | 6f4dd62 | 2018-05-29 09:54:40 +0800 | [diff] [blame] | 20 | source "board/AndesTech/ax25-ae350/Kconfig" |
Bin Meng | 510e379 | 2018-09-26 06:55:21 -0700 | [diff] [blame] | 21 | source "board/emulation/qemu-riscv/Kconfig" |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 22 | |
Rick Chen | 52923c6 | 2018-11-07 09:34:06 +0800 | [diff] [blame^] | 23 | # platform-specific options below |
24 | source "arch/riscv/cpu/ax25/Kconfig" | ||||
25 | |||||
26 | # architecture-specific options below | ||||
27 | |||||
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 28 | choice |
Lukas Auer | 862e2e7 | 2018-11-22 11:26:12 +0100 | [diff] [blame] | 29 | prompt "Base ISA" |
30 | default ARCH_RV32I | ||||
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 31 | |
Lukas Auer | 862e2e7 | 2018-11-22 11:26:12 +0100 | [diff] [blame] | 32 | config ARCH_RV32I |
33 | bool "RV32I" | ||||
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 34 | select 32BIT |
35 | help | ||||
Lukas Auer | 862e2e7 | 2018-11-22 11:26:12 +0100 | [diff] [blame] | 36 | Choose this option to target the RV32I base integer instruction set. |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 37 | |
Lukas Auer | 862e2e7 | 2018-11-22 11:26:12 +0100 | [diff] [blame] | 38 | config ARCH_RV64I |
39 | bool "RV64I" | ||||
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 40 | select 64BIT |
Lukas Auer | 7115856 | 2018-11-22 11:26:13 +0100 | [diff] [blame] | 41 | select PHYS_64BIT |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 42 | help |
Lukas Auer | 862e2e7 | 2018-11-22 11:26:12 +0100 | [diff] [blame] | 43 | Choose this option to target the RV64I base integer instruction set. |
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 44 | |
45 | endchoice | ||||
46 | |||||
Lukas Auer | d57ffa6 | 2018-11-22 11:26:14 +0100 | [diff] [blame] | 47 | config RISCV_ISA_C |
48 | bool "Emit compressed instructions" | ||||
49 | default y | ||||
50 | help | ||||
51 | Adds "C" to the ISA subsets that the toolchain is allowed to emit | ||||
52 | when building U-Boot, which results in compressed instructions in the | ||||
53 | U-Boot binary. | ||||
54 | |||||
55 | config RISCV_ISA_A | ||||
56 | def_bool y | ||||
57 | |||||
Rick Chen | f94c44e | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 58 | config 32BIT |
59 | bool | ||||
60 | |||||
61 | config 64BIT | ||||
62 | bool | ||||
63 | |||||
64 | endmenu |