Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 1 | /* |
| 2 | * National Semiconductor PHY drivers |
| 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 5 | * |
| 6 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
| 7 | * author Andy Fleming |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 8 | */ |
| 9 | #include <phy.h> |
| 10 | |
Heiko Schocher | 96d0b9e | 2013-06-04 10:58:09 +0200 | [diff] [blame] | 11 | /* NatSemi DP83630 */ |
| 12 | |
| 13 | #define DP83630_PHY_PAGESEL_REG 0x13 |
| 14 | #define DP83630_PHY_PTP_COC_REG 0x14 |
| 15 | #define DP83630_PHY_PTP_CLKOUT_EN (1<<15) |
| 16 | #define DP83630_PHY_RBR_REG 0x17 |
| 17 | |
| 18 | static int dp83630_config(struct phy_device *phydev) |
| 19 | { |
| 20 | int ptp_coc_reg; |
| 21 | |
| 22 | phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); |
| 23 | phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6); |
| 24 | ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, |
| 25 | DP83630_PHY_PTP_COC_REG); |
| 26 | ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN; |
| 27 | phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG, |
| 28 | ptp_coc_reg); |
| 29 | phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0); |
| 30 | |
| 31 | genphy_config_aneg(phydev); |
| 32 | |
| 33 | return 0; |
| 34 | } |
| 35 | |
| 36 | static struct phy_driver DP83630_driver = { |
| 37 | .name = "NatSemi DP83630", |
| 38 | .uid = 0x20005ce1, |
| 39 | .mask = 0xfffffff0, |
| 40 | .features = PHY_BASIC_FEATURES, |
| 41 | .config = &dp83630_config, |
| 42 | .startup = &genphy_startup, |
| 43 | .shutdown = &genphy_shutdown, |
| 44 | }; |
| 45 | |
| 46 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 47 | /* DP83865 Link and Auto-Neg Status Register */ |
| 48 | #define MIIM_DP83865_LANR 0x11 |
| 49 | #define MIIM_DP83865_SPD_MASK 0x0018 |
| 50 | #define MIIM_DP83865_SPD_1000 0x0010 |
| 51 | #define MIIM_DP83865_SPD_100 0x0008 |
| 52 | #define MIIM_DP83865_DPX_FULL 0x0002 |
| 53 | |
| 54 | |
| 55 | /* NatSemi DP83865 */ |
| 56 | static int dp83865_config(struct phy_device *phydev) |
| 57 | { |
| 58 | phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); |
| 59 | genphy_config_aneg(phydev); |
| 60 | |
| 61 | return 0; |
| 62 | } |
| 63 | |
| 64 | static int dp83865_parse_status(struct phy_device *phydev) |
| 65 | { |
| 66 | int mii_reg; |
| 67 | |
| 68 | mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR); |
| 69 | |
| 70 | switch (mii_reg & MIIM_DP83865_SPD_MASK) { |
| 71 | |
| 72 | case MIIM_DP83865_SPD_1000: |
| 73 | phydev->speed = SPEED_1000; |
| 74 | break; |
| 75 | |
| 76 | case MIIM_DP83865_SPD_100: |
| 77 | phydev->speed = SPEED_100; |
| 78 | break; |
| 79 | |
| 80 | default: |
| 81 | phydev->speed = SPEED_10; |
| 82 | break; |
| 83 | |
| 84 | } |
| 85 | |
| 86 | if (mii_reg & MIIM_DP83865_DPX_FULL) |
| 87 | phydev->duplex = DUPLEX_FULL; |
| 88 | else |
| 89 | phydev->duplex = DUPLEX_HALF; |
| 90 | |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | static int dp83865_startup(struct phy_device *phydev) |
| 95 | { |
| 96 | genphy_update_link(phydev); |
| 97 | dp83865_parse_status(phydev); |
| 98 | |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | |
| 103 | static struct phy_driver DP83865_driver = { |
| 104 | .name = "NatSemi DP83865", |
| 105 | .uid = 0x20005c70, |
| 106 | .mask = 0xfffffff0, |
| 107 | .features = PHY_GBIT_FEATURES, |
| 108 | .config = &dp83865_config, |
| 109 | .startup = &dp83865_startup, |
| 110 | .shutdown = &genphy_shutdown, |
| 111 | }; |
| 112 | |
| 113 | int phy_natsemi_init(void) |
| 114 | { |
Heiko Schocher | 96d0b9e | 2013-06-04 10:58:09 +0200 | [diff] [blame] | 115 | phy_register(&DP83630_driver); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 116 | phy_register(&DP83865_driver); |
| 117 | |
| 118 | return 0; |
| 119 | } |