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Stefano Babicf8f8acd2010-07-06 19:32:09 +02001/*
2 * (C) Copyright 2010
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/io.h>
28#include <asm/arch/imx-regs.h>
Jason Liuff9f4752010-10-18 11:09:26 +080029#include <asm/arch/mx5x_pins.h>
Stefano Babicf8f8acd2010-07-06 19:32:09 +020030#include <asm/arch/crm_regs.h>
31#include <asm/arch/iomux.h>
Stefano Babic4c0443c2011-08-21 10:57:53 +020032#include <asm/gpio.h>
Stefano Babicf8f8acd2010-07-06 19:32:09 +020033#include <asm/arch/sys_proto.h>
Stefano Babicf8f8acd2010-07-06 19:32:09 +020034#include <i2c.h>
35#include <mmc.h>
Stefano Babicbac395e2011-10-02 12:58:03 +020036#include <pmic.h>
Stefano Babicf8f8acd2010-07-06 19:32:09 +020037#include <fsl_esdhc.h>
38#include <fsl_pmic.h>
39#include <mc13892.h>
Stefano Babica0152c42010-10-21 10:34:39 +020040#include <linux/fb.h>
Stefano Babicf8f8acd2010-07-06 19:32:09 +020041
Marek Vasut02ae1a12011-10-06 00:25:03 +020042#include <ipu_pixfmt.h>
43
Stefano Babicf8f8acd2010-07-06 19:32:09 +020044DECLARE_GLOBAL_DATA_PTR;
45
Stefano Babica0152c42010-10-21 10:34:39 +020046static struct fb_videomode nec_nl6448bc26_09c = {
47 "NEC_NL6448BC26-09C",
48 60, /* Refresh */
49 640, /* xres */
50 480, /* yres */
51 37650, /* pixclock = 26.56Mhz */
52 48, /* left margin */
53 16, /* right margin */
54 31, /* upper margin */
55 12, /* lower margin */
56 96, /* hsync-len */
57 2, /* vsync-len */
58 0, /* sync */
59 FB_VMODE_NONINTERLACED, /* vmode */
60 0, /* flag */
61};
62
Fabio Estevamc08f68c2011-05-10 07:50:46 +000063#ifdef CONFIG_HW_WATCHDOG
64#include <watchdog.h>
Stefano Babicf8f8acd2010-07-06 19:32:09 +020065void hw_watchdog_reset(void)
66{
67 int val;
68
69 /* toggle watchdog trigger pin */
Stefano Babic4c0443c2011-08-21 10:57:53 +020070 val = gpio_get_value(66);
Stefano Babicf8f8acd2010-07-06 19:32:09 +020071 val = val ? 0 : 1;
Stefano Babic4c0443c2011-08-21 10:57:53 +020072 gpio_set_value(66, val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +020073}
74#endif
75
76static void init_drive_strength(void)
77{
78 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
79 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
80 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
81 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
82 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
83 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
84 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
85 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
86 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
87 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
88 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
89 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
90 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
91 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
92 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
93 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
94 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
95 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
96 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
97 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
98 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
99 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
100 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
101 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
102 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
103 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
104 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
105
106 /* Setting pad options */
107 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
108 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
109 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
110 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
111 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
112 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
113 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
114 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
115 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
116 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
117 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
118 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
119 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
120 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
121 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
122 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
123 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
124 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
125 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
126 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
127 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
128 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
129 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
130 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
131 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
132 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
133 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
134 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
135 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
136 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
137 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
138 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
139 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
140 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
141 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
142 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
143 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
144 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
145 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
146 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
147 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
148 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
149}
150
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200151int dram_init(void)
152{
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200153 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
154 PHYS_SDRAM_1_SIZE);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200155
156 return 0;
157}
158
159static void setup_weim(void)
160{
161 struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
162
Fabio Estevamea113822011-06-11 17:41:53 +0000163 pweim->cs0gcr1 = 0x004100b9;
164 pweim->cs0gcr2 = 0x00000001;
165 pweim->cs0rcr1 = 0x0a018000;
166 pweim->cs0rcr2 = 0;
167 pweim->cs0wcr1 = 0x0704a240;
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200168}
169
170static void setup_uart(void)
171{
172 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
173 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
174 /* console RX on Pin EIM_D25 */
175 mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
176 mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
177 /* console TX on Pin EIM_D26 */
178 mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
179 mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
180}
181
182#ifdef CONFIG_MXC_SPI
183void spi_io_init(void)
184{
185 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
186 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
187 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
188 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
189
190 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
191 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
192 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
193 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
194
195 /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
196 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
197 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
198 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
199 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
200
201 /*
202 * SS1 will be used as GPIO because of uninterrupted
203 * long SPI transmissions (GPIO4_25)
204 */
205 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
206 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
207 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
208 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
209
210 /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
211 mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
212 mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
213 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
214 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
215
216 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
217 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
218 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
219 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
220}
221
222static void reset_peripherals(int reset)
223{
224 if (reset) {
225
226 /* reset_n is on NANDF_D15 */
Stefano Babic4c0443c2011-08-21 10:57:53 +0200227 gpio_direction_output(89, 0);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200228
229#ifdef CONFIG_VISION2_HW_1_0
230 /*
231 * set FEC Configuration lines
232 * set levels of FEC config lines
233 */
Stefano Babic4c0443c2011-08-21 10:57:53 +0200234 gpio_direction_output(75, 0);
235 gpio_direction_output(74, 1);
236 gpio_direction_output(95, 1);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200237
238 /* set direction of FEC config lines */
Stefano Babic4c0443c2011-08-21 10:57:53 +0200239 gpio_direction_output(59, 0);
240 gpio_direction_output(60, 0);
241 gpio_direction_output(61, 0);
242 gpio_direction_output(55, 1);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200243
244 /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
245 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
246 /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
247 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
248 /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
249 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
250 /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
251 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
252 /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */
253 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
254 /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
255 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
256 /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
257 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
258#endif
259
260 /*
261 * activate reset_n pin
262 * Select mux mode: ALT3 mux port: NAND D15
263 */
264 mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
265 mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
266 PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
267 } else {
268 /* set FEC Control lines */
Stefano Babic4c0443c2011-08-21 10:57:53 +0200269 gpio_direction_input(89);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200270 udelay(500);
271
272#ifdef CONFIG_VISION2_HW_1_0
273 /* FEC RDATA[3] */
274 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
275 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
276
277 /* FEC RDATA[2] */
278 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
279 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
280
281 /* FEC RDATA[1] */
282 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
283 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
284
285 /* FEC RDATA[0] */
286 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
287 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
288
289 /* FEC RX_CLK */
290 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
291 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
292
293 /* FEC RX_ER */
294 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
295 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
296
297 /* FEC COL */
298 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
299 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
300#endif
301 }
302}
303
304static void power_init_mx51(void)
305{
306 unsigned int val;
Stefano Babicbac395e2011-10-02 12:58:03 +0200307 struct pmic *p;
308
309 pmic_init();
310 p = get_pmic();
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200311
312 /* Write needed to Power Gate 2 register */
Stefano Babicbac395e2011-10-02 12:58:03 +0200313 pmic_reg_read(p, REG_POWER_MISC, &val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200314
315 /* enable VCAM with 2.775V to enable read from PMIC */
316 val = VCAMCONFIG | VCAMEN;
Stefano Babicbac395e2011-10-02 12:58:03 +0200317 pmic_reg_write(p, REG_MODE_1, val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200318
319 /*
320 * Set switchers in Auto in NORMAL mode & STANDBY mode
321 * Setup the switcher mode for SW1 & SW2
322 */
Stefano Babicbac395e2011-10-02 12:58:03 +0200323 pmic_reg_read(p, REG_SW_4, &val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200324 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
325 (SWMODE_MASK << SWMODE2_SHIFT)));
326 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
327 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
Stefano Babicbac395e2011-10-02 12:58:03 +0200328 pmic_reg_write(p, REG_SW_4, val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200329
330 /* Setup the switcher mode for SW3 & SW4 */
Stefano Babicbac395e2011-10-02 12:58:03 +0200331 pmic_reg_read(p, REG_SW_5, &val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200332 val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
333 (SWMODE_MASK << SWMODE3_SHIFT));
334 val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
335 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
Stefano Babicbac395e2011-10-02 12:58:03 +0200336 pmic_reg_write(p, REG_SW_5, val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200337
338
339 /* Set VGEN3 to 1.8V, VCAM to 3.0V */
Stefano Babicbac395e2011-10-02 12:58:03 +0200340 pmic_reg_read(p, REG_SETTING_0, &val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200341 val &= ~(VCAM_MASK | VGEN3_MASK);
342 val |= VCAM_3_0;
Stefano Babicbac395e2011-10-02 12:58:03 +0200343 pmic_reg_write(p, REG_SETTING_0, val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200344
345 /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
Stefano Babicbac395e2011-10-02 12:58:03 +0200346 pmic_reg_read(p, REG_SETTING_1, &val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200347 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
348 val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
Stefano Babicbac395e2011-10-02 12:58:03 +0200349 pmic_reg_write(p, REG_SETTING_1, val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200350
351 /* Configure VGEN3 and VCAM regulators to use external PNP */
352 val = VGEN3CONFIG | VCAMCONFIG;
Stefano Babicbac395e2011-10-02 12:58:03 +0200353 pmic_reg_write(p, REG_MODE_1, val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200354 udelay(200);
355
356 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
357 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
358 VVIDEOEN | VAUDIOEN | VSDEN;
Stefano Babicbac395e2011-10-02 12:58:03 +0200359 pmic_reg_write(p, REG_MODE_1, val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200360
Stefano Babicbac395e2011-10-02 12:58:03 +0200361 pmic_reg_read(p, REG_POWER_CTL2, &val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200362 val |= WDIRESET;
Stefano Babicbac395e2011-10-02 12:58:03 +0200363 pmic_reg_write(p, REG_POWER_CTL2, val);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200364
365 udelay(2500);
366
367}
368#endif
369
370static void setup_gpios(void)
371{
372 unsigned int i;
373
374 /* CAM_SUP_DISn, GPIO1_7 */
375 mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
376 mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
377
378 /* DAB Display EN, GPIO3_1 */
379 mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
380 mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
381
382 /* WDOG_TRIGGER, GPIO3_2 */
383 mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
384 mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
385
386 /* Now we need to trigger the watchdog */
387 WATCHDOG_RESET();
388
389 /* Display2 TxEN, GPIO3_3 */
390 mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
391 mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
392
393 /* DAB Light EN, GPIO3_4 */
394 mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
395 mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
396
397 /* AUDIO_MUTE, GPIO3_5 */
398 mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
399 mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
400
401 /* SPARE_OUT, GPIO3_6 */
402 mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
403 mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
404
405 /* BEEPER_EN, GPIO3_26 */
406 mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
407 mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
408
409 /* POWER_OFF, GPIO3_27 */
410 mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
411 mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
412
413 /* FRAM_WE, GPIO3_30 */
414 mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
415 mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
416
417 /* EXPANSION_EN, GPIO4_26 */
418 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
419 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
420
Stefano Babica0152c42010-10-21 10:34:39 +0200421 /* PWM Output GPIO1_2 */
422 mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
423
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200424 /*
425 * Set GPIO1_4 to high and output; it is used to reset
426 * the system on reboot
427 */
Stefano Babic4c0443c2011-08-21 10:57:53 +0200428 gpio_direction_output(4, 1);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200429
Stefano Babic4c0443c2011-08-21 10:57:53 +0200430 gpio_direction_output(7, 0);
Fabio Estevamafffcc72011-11-21 05:57:39 +0000431 for (i = 65; i < 71; i++)
Stefano Babic4c0443c2011-08-21 10:57:53 +0200432 gpio_direction_output(i, 0);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200433
Stefano Babic4c0443c2011-08-21 10:57:53 +0200434 gpio_direction_output(94, 0);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200435
436 /* Set POWER_OFF high */
Stefano Babic4c0443c2011-08-21 10:57:53 +0200437 gpio_direction_output(91, 1);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200438
Stefano Babic4c0443c2011-08-21 10:57:53 +0200439 gpio_direction_output(90, 0);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200440
Stefano Babic4c0443c2011-08-21 10:57:53 +0200441 gpio_direction_output(122, 0);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200442
Stefano Babic4c0443c2011-08-21 10:57:53 +0200443 gpio_direction_output(121, 1);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200444
445 WATCHDOG_RESET();
446}
447
448static void setup_fec(void)
449{
450 /*FEC_MDIO*/
451 mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
452 mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
453
454 /*FEC_MDC*/
455 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
456 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
457
458 /* FEC RDATA[3] */
459 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
460 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
461
462 /* FEC RDATA[2] */
463 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
464 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
465
466 /* FEC RDATA[1] */
467 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
468 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
469
470 /* FEC RDATA[0] */
471 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
472 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
473
474 /* FEC TDATA[3] */
475 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
476 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
477
478 /* FEC TDATA[2] */
479 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
480 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
481
482 /* FEC TDATA[1] */
483 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
484 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
485
486 /* FEC TDATA[0] */
487 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
488 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
489
490 /* FEC TX_EN */
491 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
492 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
493
494 /* FEC TX_ER */
495 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
496 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
497
498 /* FEC TX_CLK */
499 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
500 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
501
502 /* FEC TX_COL */
503 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
504 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
505
506 /* FEC RX_CLK */
507 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
508 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
509
510 /* FEC RX_CRS */
511 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
512 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
513
514 /* FEC RX_ER */
515 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
516 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
517
518 /* FEC RX_DV */
519 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
520 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
521}
522
523struct fsl_esdhc_cfg esdhc_cfg[1] = {
524 {MMC_SDHC1_BASE_ADDR, 1},
525};
526
527int get_mmc_getcd(u8 *cd, struct mmc *mmc)
528{
529 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
530
531 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
Stefano Babic4c0443c2011-08-21 10:57:53 +0200532 *cd = gpio_get_value(0);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200533 else
534 *cd = 0;
535
536 return 0;
537}
538
539#ifdef CONFIG_FSL_ESDHC
540int board_mmc_init(bd_t *bis)
541{
542 mxc_request_iomux(MX51_PIN_SD1_CMD,
543 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
544 mxc_request_iomux(MX51_PIN_SD1_CLK,
545 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
546 mxc_request_iomux(MX51_PIN_SD1_DATA0,
547 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
548 mxc_request_iomux(MX51_PIN_SD1_DATA1,
549 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
550 mxc_request_iomux(MX51_PIN_SD1_DATA2,
551 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
552 mxc_request_iomux(MX51_PIN_SD1_DATA3,
553 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
554 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
555 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
556 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
557 PAD_CTL_PUE_PULL |
558 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
559 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
560 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
561 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
562 PAD_CTL_PUE_PULL |
563 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
564 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
565 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
566 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
567 PAD_CTL_PUE_PULL |
568 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
569 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
570 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
571 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
572 PAD_CTL_PUE_PULL |
573 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
574 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
575 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
576 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
577 PAD_CTL_PUE_PULL |
578 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
579 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
580 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
581 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
582 PAD_CTL_PUE_PULL |
583 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
584 mxc_request_iomux(MX51_PIN_GPIO1_0,
585 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
586 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
587 PAD_CTL_HYS_ENABLE);
588 mxc_request_iomux(MX51_PIN_GPIO1_1,
589 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
590 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
591 PAD_CTL_HYS_ENABLE);
592
593 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
594}
595#endif
596
Stefano Babice9934f02011-09-28 11:21:15 +0200597void lcd_enable(void)
598{
599 int ret;
600
601 mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
602 mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
603
604 gpio_set_value(2, 1);
605 mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
606
Marek Vasut02ae1a12011-10-06 00:25:03 +0200607 ret = mx51_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
Stefano Babice9934f02011-09-28 11:21:15 +0200608 if (ret)
609 puts("LCD cannot be configured\n");
610}
611
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200612int board_early_init_f(void)
613{
614
615
616 init_drive_strength();
617
618 /* Setup debug led */
Stefano Babic4c0443c2011-08-21 10:57:53 +0200619 gpio_direction_output(6, 0);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200620 mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
621 mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
622
623 /* wait a little while to give the pll time to settle */
624 sdelay(100000);
625
626 setup_weim();
627 setup_uart();
628 setup_fec();
629 setup_gpios();
630
631 spi_io_init();
632
633 return 0;
634}
635
Stefano Babica0152c42010-10-21 10:34:39 +0200636static void backlight(int on)
637{
638 if (on) {
Stefano Babic4c0443c2011-08-21 10:57:53 +0200639 gpio_set_value(65, 1);
Stefano Babica0152c42010-10-21 10:34:39 +0200640 udelay(10000);
Stefano Babic4c0443c2011-08-21 10:57:53 +0200641 gpio_set_value(68, 1);
Stefano Babica0152c42010-10-21 10:34:39 +0200642 } else {
Stefano Babic4c0443c2011-08-21 10:57:53 +0200643 gpio_set_value(65, 0);
644 gpio_set_value(68, 0);
Stefano Babica0152c42010-10-21 10:34:39 +0200645 }
646}
647
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200648int board_init(void)
649{
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200650 /* address of boot parameters */
651 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
652
Stefano Babice9934f02011-09-28 11:21:15 +0200653 lcd_enable();
654
655 backlight(1);
656
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200657 return 0;
658}
659
660int board_late_init(void)
661{
662 power_init_mx51();
663
664 reset_peripherals(1);
665 udelay(2000);
666 reset_peripherals(0);
667 udelay(2000);
668
669 /* Early revisions require a second reset */
670#ifdef CONFIG_VISION2_HW_1_0
671 reset_peripherals(1);
672 udelay(2000);
673 reset_peripherals(0);
674 udelay(2000);
675#endif
676
Stefano Babice9934f02011-09-28 11:21:15 +0200677 setenv("stdout", "serial");
678
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200679 return 0;
680}
681
682int checkboard(void)
683{
Jason Liu51958902011-04-22 02:55:42 +0000684 puts("Board: TTControl Vision II CPU V\n");
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200685
686 return 0;
687}
688
Stefano Babica0152c42010-10-21 10:34:39 +0200689int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
690{
691 int on;
692
693 if (argc < 2)
694 return cmd_usage(cmdtp);
695
696 on = (strcmp(argv[1], "on") == 0);
697 backlight(on);
698
699 return 0;
700}
701
702U_BOOT_CMD(
703 lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
704 "Vision2 Backlight",
705 "lcdbl [on|off]\n"
706);