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stroese13fdf8a2003-09-12 08:55:18 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_VOH405 1 /* ...on a VOH405 board */
stroese13fdf8a2003-09-12 08:55:18 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese13fdf8a2003-09-12 08:55:18 +000042
stroesea20b27a2004-12-16 18:05:42 +000043#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
stroese13fdf8a2003-09-12 08:55:18 +000044
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000049#undef CONFIG_BOOTCOMMAND
stroese13fdf8a2003-09-12 08:55:18 +000050
stroesea20b27a2004-12-16 18:05:42 +000051#define CONFIG_PREBOOT /* enable preboot variable */
52
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroese13fdf8a2003-09-12 08:55:18 +000054
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +010055#define CONFIG_NET_MULTI 1
56#undef CONFIG_HAS_ETH1
57
Ben Warren96e21f82008-10-27 23:50:15 -070058#define CONFIG_PPC4xx_EMAC
stroese13fdf8a2003-09-12 08:55:18 +000059#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000060#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000061#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +010062#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
stroesea20b27a2004-12-16 18:05:42 +000063
64#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
stroese13fdf8a2003-09-12 08:55:18 +000065
Jon Loeligera5562902007-07-08 15:31:57 -050066
67/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050068 * BOOTP options
69 */
70#define CONFIG_BOOTP_BOOTFILESIZE
71#define CONFIG_BOOTP_BOOTPATH
72#define CONFIG_BOOTP_GATEWAY
73#define CONFIG_BOOTP_HOSTNAME
74
75
76/*
Jon Loeligera5562902007-07-08 15:31:57 -050077 * Command line configuration.
78 */
79#include <config_cmd_default.h>
80
81#define CONFIG_CMD_DHCP
82#define CONFIG_CMD_PCI
83#define CONFIG_CMD_IRQ
84#define CONFIG_CMD_IDE
85#define CONFIG_CMD_FAT
86#define CONFIG_CMD_ELF
87#define CONFIG_CMD_NAND
88#define CONFIG_CMD_DATE
89#define CONFIG_CMD_I2C
90#define CONFIG_CMD_MII
91#define CONFIG_CMD_PING
92#define CONFIG_CMD_EEPROM
93
stroese13fdf8a2003-09-12 08:55:18 +000094
95#define CONFIG_MAC_PARTITION
96#define CONFIG_DOS_PARTITION
97
stroesea20b27a2004-12-16 18:05:42 +000098#define CONFIG_SUPPORT_VFAT
99
wdenkc837dcb2004-01-20 23:12:12 +0000100#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese13fdf8a2003-09-12 08:55:18 +0000101
wdenkc837dcb2004-01-20 23:12:12 +0000102#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000104
wdenkc837dcb2004-01-20 23:12:12 +0000105#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese13fdf8a2003-09-12 08:55:18 +0000106
107/*
108 * Miscellaneous configurable options
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_LONGHELP /* undef to save memory */
111#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
stroese13fdf8a2003-09-12 08:55:18 +0000112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
114#ifdef CONFIG_SYS_HUSH_PARSER
115#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
stroese13fdf8a2003-09-12 08:55:18 +0000116#endif
117
Jon Loeligera5562902007-07-08 15:31:57 -0500118#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000120#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000122#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
124#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
125#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroese13fdf8a2003-09-12 08:55:18 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroese13fdf8a2003-09-12 08:55:18 +0000130
stroesea20b27a2004-12-16 18:05:42 +0000131#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
134#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroese13fdf8a2003-09-12 08:55:18 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_BASE_BAUD 691200
stroesea20b27a2004-12-16 18:05:42 +0000138#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
stroese13fdf8a2003-09-12 08:55:18 +0000139
140/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BAUDRATE_TABLE \
stroese13fdf8a2003-09-12 08:55:18 +0000142 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
143 57600, 115200, 230400, 460800, 921600 }
144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
146#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroese13fdf8a2003-09-12 08:55:18 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroese13fdf8a2003-09-12 08:55:18 +0000149
150#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
151
wdenkc837dcb2004-01-20 23:12:12 +0000152#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese13fdf8a2003-09-12 08:55:18 +0000153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese13fdf8a2003-09-12 08:55:18 +0000155
156/*-----------------------------------------------------------------------
157 * NAND-FLASH stuff
158 *-----------------------------------------------------------------------
159 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200162#define NAND_BIG_DELAY_US 25
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
165#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
166#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
167#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
stroese13fdf8a2003-09-12 08:55:18 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
170#define CONFIG_SYS_NAND_QUIET 1
stroesea20b27a2004-12-16 18:05:42 +0000171
stroese13fdf8a2003-09-12 08:55:18 +0000172/*-----------------------------------------------------------------------
173 * PCI stuff
174 *-----------------------------------------------------------------------
175 */
stroesea20b27a2004-12-16 18:05:42 +0000176#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
177#define PCI_HOST_FORCE 1 /* configure as pci host */
178#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroese13fdf8a2003-09-12 08:55:18 +0000179
stroesea20b27a2004-12-16 18:05:42 +0000180#define CONFIG_PCI /* include pci support */
181#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
182#define CONFIG_PCI_PNP /* do pci plug-and-play */
183 /* resource configuration */
stroese13fdf8a2003-09-12 08:55:18 +0000184
stroesea20b27a2004-12-16 18:05:42 +0000185#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroese13fdf8a2003-09-12 08:55:18 +0000186
stroesea20b27a2004-12-16 18:05:42 +0000187#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
190#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
191#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
192#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
193#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
194#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
195#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
196#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
197#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroese13fdf8a2003-09-12 08:55:18 +0000198
199/*-----------------------------------------------------------------------
200 * IDE/ATA stuff
201 *-----------------------------------------------------------------------
202 */
wdenkc837dcb2004-01-20 23:12:12 +0000203#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
204#undef CONFIG_IDE_LED /* no led for ide supported */
stroese13fdf8a2003-09-12 08:55:18 +0000205#define CONFIG_IDE_RESET 1 /* reset for ide supported */
206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
208#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
stroese13fdf8a2003-09-12 08:55:18 +0000209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
211#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
212#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0010
stroese13fdf8a2003-09-12 08:55:18 +0000213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
215#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
216#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroese13fdf8a2003-09-12 08:55:18 +0000217
218/*
219 * For booting Linux, the board info and command line data
220 * have to be in the first 8 MB of memory, since this is
221 * the maximum mapped by the Linux kernel during initialization.
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroese13fdf8a2003-09-12 08:55:18 +0000224/*-----------------------------------------------------------------------
225 * FLASH organization
226 */
227#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
230#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroese13fdf8a2003-09-12 08:55:18 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
233#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
stroese13fdf8a2003-09-12 08:55:18 +0000234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
236#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
237#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroese13fdf8a2003-09-12 08:55:18 +0000238/*
239 * The following defines are added for buggy IOP480 byte interface.
240 * All other boards should use the standard values (CPCI405 etc.)
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
243#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
244#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroese13fdf8a2003-09-12 08:55:18 +0000245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroese13fdf8a2003-09-12 08:55:18 +0000247
stroese13fdf8a2003-09-12 08:55:18 +0000248/*-----------------------------------------------------------------------
249 * Start addresses for the final memory configuration
250 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroese13fdf8a2003-09-12 08:55:18 +0000252 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_SDRAM_BASE 0x00000000
254#define CONFIG_SYS_FLASH_BASE 0xFFF80000
255#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
256#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
257#define CONFIG_SYS_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */
stroese13fdf8a2003-09-12 08:55:18 +0000258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
260# define CONFIG_SYS_RAMBOOT 1
stroese13fdf8a2003-09-12 08:55:18 +0000261#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262# undef CONFIG_SYS_RAMBOOT
stroese13fdf8a2003-09-12 08:55:18 +0000263#endif
264
265/*-----------------------------------------------------------------------
266 * Environment Variable setup
267 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200268#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200269#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
270#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroese13fdf8a2003-09-12 08:55:18 +0000271 /* total size of a CAT24WC16 is 2048 bytes */
272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
274#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
stroese13fdf8a2003-09-12 08:55:18 +0000275
276/*-----------------------------------------------------------------------
277 * I2C EEPROM (CAT24WC16) for environment
278 */
279#define CONFIG_HARD_I2C /* I2c with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
281#define CONFIG_SYS_I2C_SLAVE 0x7F
stroese13fdf8a2003-09-12 08:55:18 +0000282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
284#define CONFIG_SYS_EEPROM_WREN 1
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100285
stroese13fdf8a2003-09-12 08:55:18 +0000286/* CAT24WC32/64... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000288/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
290#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
stroese13fdf8a2003-09-12 08:55:18 +0000291 /* 32 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000292 /* last 5 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroese13fdf8a2003-09-12 08:55:18 +0000294
295/*-----------------------------------------------------------------------
stroese13fdf8a2003-09-12 08:55:18 +0000296 * External Bus Controller (EBC) Setup
297 */
298
wdenkc837dcb2004-01-20 23:12:12 +0000299#define CAN_BA 0xF0000000 /* CAN Base Address */
300#define DUART0_BA 0xF0000400 /* DUART Base Address */
301#define DUART1_BA 0xF0000408 /* DUART Base Address */
302#define RTC_BA 0xF0000500 /* RTC Base Address */
303#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000305
wdenkc837dcb2004-01-20 23:12:12 +0000306/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_EBC_PB0AP 0x92015480
308/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
309#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000310
wdenkc837dcb2004-01-20 23:12:12 +0000311/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_EBC_PB1AP 0x92015480
313#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000314
wdenkc837dcb2004-01-20 23:12:12 +0000315/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
317#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000318
wdenkc837dcb2004-01-20 23:12:12 +0000319/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
321#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000322
wdenkc837dcb2004-01-20 23:12:12 +0000323/* Memory Bank 4 (Epson VGA) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
325#define CONFIG_SYS_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000326
327/*-----------------------------------------------------------------------
stroesea20b27a2004-12-16 18:05:42 +0000328 * LCD Setup
329 */
330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
332#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
333#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
334#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
stroesea20b27a2004-12-16 18:05:42 +0000335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
stroesea20b27a2004-12-16 18:05:42 +0000337
338/*-----------------------------------------------------------------------
stroese13fdf8a2003-09-12 08:55:18 +0000339 * FPGA stuff
340 */
341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000343
344/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_FPGA_CTRL 0x000
stroese13fdf8a2003-09-12 08:55:18 +0000346
347/* FPGA Control Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
349#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
350#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
stroese13fdf8a2003-09-12 08:55:18 +0000351
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
353#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroese13fdf8a2003-09-12 08:55:18 +0000354
355/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
357#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
358#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
359#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
360#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroese13fdf8a2003-09-12 08:55:18 +0000361
362/*-----------------------------------------------------------------------
363 * Definitions for initial stack pointer and data area (in data cache)
364 */
365/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_TEMP_STACK_OCM 1
stroese13fdf8a2003-09-12 08:55:18 +0000367
368/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
370#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
371#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
372#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
stroese13fdf8a2003-09-12 08:55:18 +0000373
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
375#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
376#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroese13fdf8a2003-09-12 08:55:18 +0000377
378/*-----------------------------------------------------------------------
379 * Definitions for GPIO setup (PPC405EP specific)
380 *
wdenkc837dcb2004-01-20 23:12:12 +0000381 * GPIO0[0] - External Bus Controller BLAST output
382 * GPIO0[1-9] - Instruction trace outputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000383 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
384 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
385 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
386 * GPIO0[24-27] - UART0 control signal inputs/outputs
387 * GPIO0[28-29] - UART1 data signal input/output
stroesea20b27a2004-12-16 18:05:42 +0000388 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000389 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_GPIO0_OSRH 0x00000550
391#define CONFIG_SYS_GPIO0_OSRL 0x00000110
392#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
393#define CONFIG_SYS_GPIO0_ISR1L 0x15555440
394#define CONFIG_SYS_GPIO0_TSRH 0x00000000
395#define CONFIG_SYS_GPIO0_TSRL 0x00000000
396#define CONFIG_SYS_GPIO0_TCR 0x777E0017
stroese13fdf8a2003-09-12 08:55:18 +0000397
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
399#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
400#define CONFIG_SYS_IIC_ON (0x80000000 >> 8)
401#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
402#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
403#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
stroese13fdf8a2003-09-12 08:55:18 +0000404
405/*
406 * Internal Definitions
407 *
408 * Boot Flags
409 */
410#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
411#define BOOTFLAG_WARM 0x02 /* Software reboot */
412
413/*
414 * Default speed selection (cpu_plb_opb_ebc) in mhz.
415 * This value will be set if iic boot eprom is disabled.
416 */
417#if 1
wdenkc837dcb2004-01-20 23:12:12 +0000418#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
419#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000420#endif
421#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000422#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
423#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
stroese13fdf8a2003-09-12 08:55:18 +0000424#endif
425#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000426#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
427#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000428#endif
429
430#endif /* __CONFIG_H */