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Suman Anna900349b2022-05-25 13:38:47 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Board specific initialization for AM62x platforms
4 *
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
7 *
8 */
9
Nikhil M Jaind5f563c2023-01-31 15:35:19 +053010#include <env.h>
Suman Anna900349b2022-05-25 13:38:47 +053011#include <spl.h>
Nikhil M Jaind5f563c2023-01-31 15:35:19 +053012#include <video.h>
13#include <splash.h>
Georgi Vlaev4c092bb2022-06-14 17:45:33 +030014#include <k3-ddrss.h>
Suman Anna900349b2022-05-25 13:38:47 +053015#include <fdt_support.h>
Nikhil M Jaind5f563c2023-01-31 15:35:19 +053016#include <asm/io.h>
Suman Anna900349b2022-05-25 13:38:47 +053017#include <asm/arch/hardware.h>
18#include <asm/arch/sys_proto.h>
Nikhil M Jaind5f563c2023-01-31 15:35:19 +053019#include <dm/uclass.h>
Suman Anna900349b2022-05-25 13:38:47 +053020
21DECLARE_GLOBAL_DATA_PTR;
22
Nikhil M Jain53ae9782023-04-20 17:41:11 +053023#if CONFIG_IS_ENABLED(SPLASH_SCREEN)
Nikhil M Jaind5f563c2023-01-31 15:35:19 +053024static struct splash_location default_splash_locations[] = {
25 {
Nikhil M Jain53ae9782023-04-20 17:41:11 +053026 .name = "sf",
27 .storage = SPLASH_STORAGE_SF,
28 .flags = SPLASH_STORAGE_RAW,
29 .offset = 0x700000,
30 },
31 {
Nikhil M Jaind5f563c2023-01-31 15:35:19 +053032 .name = "mmc",
33 .storage = SPLASH_STORAGE_MMC,
34 .flags = SPLASH_STORAGE_FS,
35 .devpart = "1:1",
36 },
37};
38
39int splash_screen_prepare(void)
40{
41 return splash_source_load(default_splash_locations,
42 ARRAY_SIZE(default_splash_locations));
43}
44#endif
45
Suman Anna900349b2022-05-25 13:38:47 +053046int board_init(void)
47{
48 return 0;
49}
50
51int dram_init(void)
52{
Georgi Vlaev249e9f32022-06-14 17:45:32 +030053 return fdtdec_setup_mem_size_base();
Suman Anna900349b2022-05-25 13:38:47 +053054}
55
56int dram_init_banksize(void)
57{
Georgi Vlaev249e9f32022-06-14 17:45:32 +030058 return fdtdec_setup_memory_banksize();
Suman Anna900349b2022-05-25 13:38:47 +053059}
Georgi Vlaev4c092bb2022-06-14 17:45:33 +030060
61#if defined(CONFIG_SPL_BUILD)
62#if defined(CONFIG_K3_AM64_DDRSS)
63static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
64{
65 struct udevice *dev;
66 int ret;
67
68 dram_init_banksize();
69
70 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
71 if (ret)
72 panic("Cannot get RAM device for ddr size fixup: %d\n", ret);
73
74 ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
75 if (ret)
76 printf("Error fixing up ddr node for ECC use! %d\n", ret);
77}
78#else
79static void fixup_memory_node(struct spl_image_info *spl_image)
80{
81 u64 start[CONFIG_NR_DRAM_BANKS];
82 u64 size[CONFIG_NR_DRAM_BANKS];
83 int bank;
84 int ret;
85
86 dram_init();
87 dram_init_banksize();
88
89 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
90 start[bank] = gd->bd->bi_dram[bank].start;
91 size[bank] = gd->bd->bi_dram[bank].size;
92 }
93
94 /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */
95 ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
96 CONFIG_NR_DRAM_BANKS);
97 if (ret)
98 printf("Error fixing up memory node! %d\n", ret);
99}
100#endif
101
102void spl_perform_fixups(struct spl_image_info *spl_image)
103{
104#if defined(CONFIG_K3_AM64_DDRSS)
105 fixup_ddr_driver_for_ecc(spl_image);
106#else
107 fixup_memory_node(spl_image);
108#endif
109}
110#endif