blob: 2144fca665e227e0de7cbafed07a82480da1a7b2 [file] [log] [blame]
Alison Wang6b57ff62014-05-06 09:13:01 +08001/*
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08002 * Copyright 2013-2015 Freescale Semiconductor, Inc.
Alison Wang6b57ff62014-05-06 09:13:01 +08003 *
4 * Freescale Quad Serial Peripheral Interface (QSPI) driver
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <malloc.h>
11#include <spi.h>
12#include <asm/io.h>
13#include <linux/sizes.h>
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +080014#include <dm.h>
15#include <errno.h>
Alexander Steinbeedbc22015-11-04 09:19:10 +010016#include <watchdog.h>
Alison Wang6b57ff62014-05-06 09:13:01 +080017#include "fsl_qspi.h"
18
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +080019DECLARE_GLOBAL_DATA_PTR;
20
Alison Wang6b57ff62014-05-06 09:13:01 +080021#define RX_BUFFER_SIZE 0x80
Peng Fanb93ab2e2014-12-31 11:01:38 +080022#ifdef CONFIG_MX6SX
23#define TX_BUFFER_SIZE 0x200
24#else
Alison Wang6b57ff62014-05-06 09:13:01 +080025#define TX_BUFFER_SIZE 0x40
Peng Fanb93ab2e2014-12-31 11:01:38 +080026#endif
Alison Wang6b57ff62014-05-06 09:13:01 +080027
Gong Qianyu87704132015-12-14 18:26:25 +080028#define OFFSET_BITS_MASK GENMASK(23, 0)
Alison Wang6b57ff62014-05-06 09:13:01 +080029
30#define FLASH_STATUS_WEL 0x02
31
32/* SEQID */
33#define SEQID_WREN 1
34#define SEQID_FAST_READ 2
35#define SEQID_RDSR 3
36#define SEQID_SE 4
37#define SEQID_CHIP_ERASE 5
38#define SEQID_PP 6
39#define SEQID_RDID 7
Peng Fanba4dc8a2014-12-31 11:01:39 +080040#define SEQID_BE_4K 8
Peng Fana2358782015-01-04 17:07:14 +080041#ifdef CONFIG_SPI_FLASH_BAR
42#define SEQID_BRRD 9
43#define SEQID_BRWR 10
44#define SEQID_RDEAR 11
45#define SEQID_WREAR 12
46#endif
Yuan Yaofebffe82016-03-15 14:36:42 +080047#define SEQID_WRAR 13
48#define SEQID_RDAR 14
Alison Wang6b57ff62014-05-06 09:13:01 +080049
Peng Fan53e3db72014-12-31 11:01:36 +080050/* QSPI CMD */
51#define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
52#define QSPI_CMD_RDSR 0x05 /* Read status register */
53#define QSPI_CMD_WREN 0x06 /* Write enable */
54#define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */
Peng Fanba4dc8a2014-12-31 11:01:39 +080055#define QSPI_CMD_BE_4K 0x20 /* 4K erase */
Peng Fan53e3db72014-12-31 11:01:36 +080056#define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */
57#define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
58#define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */
Alison Wang6b57ff62014-05-06 09:13:01 +080059
Peng Fana2358782015-01-04 17:07:14 +080060/* Used for Micron, winbond and Macronix flashes */
61#define QSPI_CMD_WREAR 0xc5 /* EAR register write */
62#define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */
63
64/* Used for Spansion flashes only. */
65#define QSPI_CMD_BRRD 0x16 /* Bank register read */
66#define QSPI_CMD_BRWR 0x17 /* Bank register write */
67
Yuan Yaofebffe82016-03-15 14:36:42 +080068/* Used for Spansion S25FS-S family flash only. */
69#define QSPI_CMD_RDAR 0x65 /* Read any device register */
70#define QSPI_CMD_WRAR 0x71 /* Write any device register */
71
Peng Fan53e3db72014-12-31 11:01:36 +080072/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
73#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
74#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
75#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
Alison Wang6b57ff62014-05-06 09:13:01 +080076
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +080077/* fsl_qspi_platdata flags */
Jagan Teki29e6abd2015-10-23 01:37:18 +053078#define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +080079
80/* default SCK frequency, unit: HZ */
81#define FSL_QSPI_DEFAULT_SCK_FREQ 50000000
82
83/* QSPI max chipselect signals number */
84#define FSL_QSPI_MAX_CHIPSELECT_NUM 4
85
86#ifdef CONFIG_DM_SPI
87/**
88 * struct fsl_qspi_platdata - platform data for Freescale QSPI
89 *
90 * @flags: Flags for QSPI QSPI_FLAG_...
91 * @speed_hz: Default SCK frequency
92 * @reg_base: Base address of QSPI registers
93 * @amba_base: Base address of QSPI memory mapping
94 * @amba_total_size: size of QSPI memory mapping
95 * @flash_num: Number of active slave devices
96 * @num_chipselect: Number of QSPI chipselect signals
97 */
98struct fsl_qspi_platdata {
99 u32 flags;
100 u32 speed_hz;
Yuan Yaobf9bffa2016-03-15 14:36:40 +0800101 fdt_addr_t reg_base;
102 fdt_addr_t amba_base;
103 fdt_size_t amba_total_size;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800104 u32 flash_num;
105 u32 num_chipselect;
106};
Alison Wang6b57ff62014-05-06 09:13:01 +0800107#endif
108
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800109/**
110 * struct fsl_qspi_priv - private data for Freescale QSPI
111 *
112 * @flags: Flags for QSPI QSPI_FLAG_...
113 * @bus_clk: QSPI input clk frequency
114 * @speed_hz: Default SCK frequency
115 * @cur_seqid: current LUT table sequence id
116 * @sf_addr: flash access offset
117 * @amba_base: Base address of QSPI memory mapping of every CS
118 * @amba_total_size: size of QSPI memory mapping
119 * @cur_amba_base: Base address of QSPI memory mapping of current CS
120 * @flash_num: Number of active slave devices
121 * @num_chipselect: Number of QSPI chipselect signals
122 * @regs: Point to QSPI register structure for I/O access
123 */
124struct fsl_qspi_priv {
125 u32 flags;
126 u32 bus_clk;
127 u32 speed_hz;
128 u32 cur_seqid;
129 u32 sf_addr;
130 u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
131 u32 amba_total_size;
132 u32 cur_amba_base;
133 u32 flash_num;
134 u32 num_chipselect;
135 struct fsl_qspi_regs *regs;
Alison Wang6b57ff62014-05-06 09:13:01 +0800136};
137
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800138#ifndef CONFIG_DM_SPI
Alison Wang6b57ff62014-05-06 09:13:01 +0800139struct fsl_qspi {
140 struct spi_slave slave;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800141 struct fsl_qspi_priv priv;
Alison Wang6b57ff62014-05-06 09:13:01 +0800142};
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800143#endif
144
145static u32 qspi_read32(u32 flags, u32 *addr)
146{
147 return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
148 in_be32(addr) : in_le32(addr);
149}
150
151static void qspi_write32(u32 flags, u32 *addr, u32 val)
152{
153 flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
154 out_be32(addr, val) : out_le32(addr, val);
155}
Alison Wang6b57ff62014-05-06 09:13:01 +0800156
157/* QSPI support swapping the flash read/write data
158 * in hardware for LS102xA, but not for VF610 */
159static inline u32 qspi_endian_xchg(u32 data)
160{
161#ifdef CONFIG_VF610
162 return swab32(data);
163#else
164 return data;
165#endif
166}
167
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800168static void qspi_set_lut(struct fsl_qspi_priv *priv)
Alison Wang6b57ff62014-05-06 09:13:01 +0800169{
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800170 struct fsl_qspi_regs *regs = priv->regs;
Alison Wang6b57ff62014-05-06 09:13:01 +0800171 u32 lut_base;
172
173 /* Unlock the LUT */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800174 qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
175 qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
Alison Wang6b57ff62014-05-06 09:13:01 +0800176
177 /* Write Enable */
178 lut_base = SEQID_WREN * 4;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800179 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
Alison Wang6b57ff62014-05-06 09:13:01 +0800180 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800181 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
182 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
183 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
Alison Wang6b57ff62014-05-06 09:13:01 +0800184
185 /* Fast Read */
186 lut_base = SEQID_FAST_READ * 4;
Peng Fana2358782015-01-04 17:07:14 +0800187#ifdef CONFIG_SPI_FLASH_BAR
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800188 qspi_write32(priv->flags, &regs->lut[lut_base],
189 OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
190 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
Peng Fana2358782015-01-04 17:07:14 +0800191 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
192#else
Alison Wang6b57ff62014-05-06 09:13:01 +0800193 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800194 qspi_write32(priv->flags, &regs->lut[lut_base],
195 OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
196 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
197 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
Alison Wang6b57ff62014-05-06 09:13:01 +0800198 else
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800199 qspi_write32(priv->flags, &regs->lut[lut_base],
Peng Fan53e3db72014-12-31 11:01:36 +0800200 OPRND0(QSPI_CMD_FAST_READ_4B) |
201 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
202 OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
203 INSTR1(LUT_ADDR));
Peng Fana2358782015-01-04 17:07:14 +0800204#endif
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800205 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
206 OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
207 OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
208 INSTR1(LUT_READ));
209 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
210 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
Alison Wang6b57ff62014-05-06 09:13:01 +0800211
212 /* Read Status */
213 lut_base = SEQID_RDSR * 4;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800214 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
Alison Wang6b57ff62014-05-06 09:13:01 +0800215 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
216 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800217 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
218 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
219 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
Alison Wang6b57ff62014-05-06 09:13:01 +0800220
221 /* Erase a sector */
222 lut_base = SEQID_SE * 4;
Peng Fana2358782015-01-04 17:07:14 +0800223#ifdef CONFIG_SPI_FLASH_BAR
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800224 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
Peng Fana2358782015-01-04 17:07:14 +0800225 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
226 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
227#else
Alison Wang6b57ff62014-05-06 09:13:01 +0800228 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800229 qspi_write32(priv->flags, &regs->lut[lut_base],
230 OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
231 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
232 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
Alison Wang6b57ff62014-05-06 09:13:01 +0800233 else
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800234 qspi_write32(priv->flags, &regs->lut[lut_base],
235 OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
236 INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
237 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
Peng Fana2358782015-01-04 17:07:14 +0800238#endif
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800239 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
240 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
241 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
Alison Wang6b57ff62014-05-06 09:13:01 +0800242
243 /* Erase the whole chip */
244 lut_base = SEQID_CHIP_ERASE * 4;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800245 qspi_write32(priv->flags, &regs->lut[lut_base],
246 OPRND0(QSPI_CMD_CHIP_ERASE) |
247 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
248 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
249 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
250 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
Alison Wang6b57ff62014-05-06 09:13:01 +0800251
252 /* Page Program */
253 lut_base = SEQID_PP * 4;
Peng Fana2358782015-01-04 17:07:14 +0800254#ifdef CONFIG_SPI_FLASH_BAR
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800255 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
Peng Fana2358782015-01-04 17:07:14 +0800256 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
257 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
258#else
Alison Wang6b57ff62014-05-06 09:13:01 +0800259 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800260 qspi_write32(priv->flags, &regs->lut[lut_base],
261 OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
262 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
263 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
Alison Wang6b57ff62014-05-06 09:13:01 +0800264 else
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800265 qspi_write32(priv->flags, &regs->lut[lut_base],
266 OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
267 INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
268 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
Peng Fana2358782015-01-04 17:07:14 +0800269#endif
Peng Fanb93ab2e2014-12-31 11:01:38 +0800270#ifdef CONFIG_MX6SX
271 /*
272 * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
273 * So, Use IDATSZ in IPCR to determine the size and here set 0.
274 */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800275 qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
Peng Fanb93ab2e2014-12-31 11:01:38 +0800276 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
277#else
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800278 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
279 OPRND0(TX_BUFFER_SIZE) |
280 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
Peng Fanb93ab2e2014-12-31 11:01:38 +0800281#endif
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800282 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
283 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
Alison Wang6b57ff62014-05-06 09:13:01 +0800284
285 /* READ ID */
286 lut_base = SEQID_RDID * 4;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800287 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
Alison Wang6b57ff62014-05-06 09:13:01 +0800288 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
289 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800290 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
291 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
292 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
Alison Wang6b57ff62014-05-06 09:13:01 +0800293
Peng Fanba4dc8a2014-12-31 11:01:39 +0800294 /* SUB SECTOR 4K ERASE */
295 lut_base = SEQID_BE_4K * 4;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800296 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
Peng Fanba4dc8a2014-12-31 11:01:39 +0800297 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
298 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
299
Peng Fana2358782015-01-04 17:07:14 +0800300#ifdef CONFIG_SPI_FLASH_BAR
301 /*
302 * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
303 * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
304 * initialization.
305 */
306 lut_base = SEQID_BRRD * 4;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800307 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
Peng Fana2358782015-01-04 17:07:14 +0800308 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
309 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
310
311 lut_base = SEQID_BRWR * 4;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800312 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
Peng Fana2358782015-01-04 17:07:14 +0800313 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
314 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
315
316 lut_base = SEQID_RDEAR * 4;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800317 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
Peng Fana2358782015-01-04 17:07:14 +0800318 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
319 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
320
321 lut_base = SEQID_WREAR * 4;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800322 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
Peng Fana2358782015-01-04 17:07:14 +0800323 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
324 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
325#endif
Yuan Yaofebffe82016-03-15 14:36:42 +0800326
327 /*
328 * Read any device register.
329 * Used for Spansion S25FS-S family flash only.
330 */
331 lut_base = SEQID_RDAR * 4;
332 qspi_write32(priv->flags, &regs->lut[lut_base],
333 OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
334 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
335 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
336 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
337 OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
338 OPRND1(1) | PAD1(LUT_PAD1) |
339 INSTR1(LUT_READ));
340
341 /*
342 * Write any device register.
343 * Used for Spansion S25FS-S family flash only.
344 */
345 lut_base = SEQID_WRAR * 4;
346 qspi_write32(priv->flags, &regs->lut[lut_base],
347 OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
348 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
349 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
350 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
351 OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
352
Alison Wang6b57ff62014-05-06 09:13:01 +0800353 /* Lock the LUT */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800354 qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
355 qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
Alison Wang6b57ff62014-05-06 09:13:01 +0800356}
357
Peng Fan5f7f70c2015-01-08 10:40:20 +0800358#if defined(CONFIG_SYS_FSL_QSPI_AHB)
359/*
360 * If we have changed the content of the flash by writing or erasing,
361 * we need to invalidate the AHB buffer. If we do not do so, we may read out
362 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
363 * domain at the same time.
364 */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800365static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
Peng Fan5f7f70c2015-01-08 10:40:20 +0800366{
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800367 struct fsl_qspi_regs *regs = priv->regs;
Peng Fan5f7f70c2015-01-08 10:40:20 +0800368 u32 reg;
369
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800370 reg = qspi_read32(priv->flags, &regs->mcr);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800371 reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800372 qspi_write32(priv->flags, &regs->mcr, reg);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800373
374 /*
375 * The minimum delay : 1 AHB + 2 SFCK clocks.
376 * Delay 1 us is enough.
377 */
378 udelay(1);
379
380 reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800381 qspi_write32(priv->flags, &regs->mcr, reg);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800382}
383
384/* Read out the data from the AHB buffer. */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800385static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
Peng Fan5f7f70c2015-01-08 10:40:20 +0800386{
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800387 struct fsl_qspi_regs *regs = priv->regs;
Peng Fan5f7f70c2015-01-08 10:40:20 +0800388 u32 mcr_reg;
Yunhui Cui04e5c6d2016-07-13 10:46:27 +0800389 void *rx_addr = NULL;
Peng Fan5f7f70c2015-01-08 10:40:20 +0800390
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800391 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800392
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800393 qspi_write32(priv->flags, &regs->mcr,
394 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
Peng Fan5f7f70c2015-01-08 10:40:20 +0800395 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
396
Yunhui Cui04e5c6d2016-07-13 10:46:27 +0800397 rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800398 /* Read out the data directly from the AHB buffer. */
Yunhui Cui04e5c6d2016-07-13 10:46:27 +0800399 memcpy(rxbuf, rx_addr, len);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800400
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800401 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800402}
403
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800404static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
Peng Fan5f7f70c2015-01-08 10:40:20 +0800405{
406 u32 reg, reg2;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800407 struct fsl_qspi_regs *regs = priv->regs;
Peng Fan5f7f70c2015-01-08 10:40:20 +0800408
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800409 reg = qspi_read32(priv->flags, &regs->mcr);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800410 /* Disable the module */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800411 qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800412
413 /* Set the Sampling Register for DDR */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800414 reg2 = qspi_read32(priv->flags, &regs->smpr);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800415 reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
416 reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800417 qspi_write32(priv->flags, &regs->smpr, reg2);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800418
419 /* Enable the module again (enable the DDR too) */
420 reg |= QSPI_MCR_DDR_EN_MASK;
421 /* Enable bit 29 for imx6sx */
Jagan Teki29e6abd2015-10-23 01:37:18 +0530422 reg |= BIT(29);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800423
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800424 qspi_write32(priv->flags, &regs->mcr, reg);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800425}
426
427/*
428 * There are two different ways to read out the data from the flash:
429 * the "IP Command Read" and the "AHB Command Read".
430 *
431 * The IC guy suggests we use the "AHB Command Read" which is faster
432 * then the "IP Command Read". (What's more is that there is a bug in
433 * the "IP Command Read" in the Vybrid.)
434 *
435 * After we set up the registers for the "AHB Command Read", we can use
436 * the memcpy to read the data directly. A "missed" access to the buffer
437 * causes the controller to clear the buffer, and use the sequence pointed
438 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
439 */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800440static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
Peng Fan5f7f70c2015-01-08 10:40:20 +0800441{
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800442 struct fsl_qspi_regs *regs = priv->regs;
443
Peng Fan5f7f70c2015-01-08 10:40:20 +0800444 /* AHB configuration for access buffer 0/1/2 .*/
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800445 qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
446 qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
447 qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
448 qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
Peng Fan5f7f70c2015-01-08 10:40:20 +0800449 (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
450
451 /* We only use the buffer3 */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800452 qspi_write32(priv->flags, &regs->buf0ind, 0);
453 qspi_write32(priv->flags, &regs->buf1ind, 0);
454 qspi_write32(priv->flags, &regs->buf2ind, 0);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800455
456 /*
457 * Set the default lut sequence for AHB Read.
458 * Parallel mode is disabled.
459 */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800460 qspi_write32(priv->flags, &regs->bfgencr,
Peng Fan5f7f70c2015-01-08 10:40:20 +0800461 SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
462
463 /*Enable DDR Mode*/
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800464 qspi_enable_ddr_mode(priv);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800465}
466#endif
467
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800468#ifdef CONFIG_SPI_FLASH_BAR
469/* Bank register read/write, EAR register read/write */
470static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
Alison Wang6b57ff62014-05-06 09:13:01 +0800471{
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800472 struct fsl_qspi_regs *regs = priv->regs;
473 u32 reg, mcr_reg, data, seqid;
474
475 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
476 qspi_write32(priv->flags, &regs->mcr,
477 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
478 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
479 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
480
481 qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
482
483 if (priv->cur_seqid == QSPI_CMD_BRRD)
484 seqid = SEQID_BRRD;
485 else
486 seqid = SEQID_RDEAR;
487
488 qspi_write32(priv->flags, &regs->ipcr,
489 (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
490
491 /* Wait previous command complete */
492 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
493 ;
494
495 while (1) {
496 reg = qspi_read32(priv->flags, &regs->rbsr);
497 if (reg & QSPI_RBSR_RDBFL_MASK) {
498 data = qspi_read32(priv->flags, &regs->rbdr[0]);
499 data = qspi_endian_xchg(data);
500 memcpy(rxbuf, &data, len);
501 qspi_write32(priv->flags, &regs->mcr,
502 qspi_read32(priv->flags, &regs->mcr) |
503 QSPI_MCR_CLR_RXF_MASK);
504 break;
505 }
506 }
507
508 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
509}
510#endif
511
512static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
513{
514 struct fsl_qspi_regs *regs = priv->regs;
Gong Qianyu52070142016-01-26 15:06:40 +0800515 u32 mcr_reg, rbsr_reg, data, size;
516 int i;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800517
518 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
519 qspi_write32(priv->flags, &regs->mcr,
520 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
521 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
522 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
523
524 qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
525
526 qspi_write32(priv->flags, &regs->ipcr,
527 (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
528 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
529 ;
530
531 i = 0;
Gong Qianyu52070142016-01-26 15:06:40 +0800532 while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800533 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
534 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
535 data = qspi_read32(priv->flags, &regs->rbdr[i]);
536 data = qspi_endian_xchg(data);
Gong Qianyu52070142016-01-26 15:06:40 +0800537 size = (len < 4) ? len : 4;
538 memcpy(rxbuf, &data, size);
539 len -= size;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800540 rxbuf++;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800541 i++;
542 }
543 }
544
545 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
546}
547
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800548/* If not use AHB read, read data from ip interface */
549static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
550{
551 struct fsl_qspi_regs *regs = priv->regs;
552 u32 mcr_reg, data;
553 int i, size;
554 u32 to_or_from;
Yuan Yaofebffe82016-03-15 14:36:42 +0800555 u32 seqid;
556
557 if (priv->cur_seqid == QSPI_CMD_RDAR)
558 seqid = SEQID_RDAR;
559 else
560 seqid = SEQID_FAST_READ;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800561
562 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
563 qspi_write32(priv->flags, &regs->mcr,
564 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
565 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
566 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
567
568 to_or_from = priv->sf_addr + priv->cur_amba_base;
569
570 while (len > 0) {
Alexander Steinbeedbc22015-11-04 09:19:10 +0100571 WATCHDOG_RESET();
572
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800573 qspi_write32(priv->flags, &regs->sfar, to_or_from);
574
575 size = (len > RX_BUFFER_SIZE) ?
576 RX_BUFFER_SIZE : len;
577
578 qspi_write32(priv->flags, &regs->ipcr,
Yuan Yaofebffe82016-03-15 14:36:42 +0800579 (seqid << QSPI_IPCR_SEQID_SHIFT) |
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800580 size);
581 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
582 ;
583
584 to_or_from += size;
585 len -= size;
586
587 i = 0;
588 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
589 data = qspi_read32(priv->flags, &regs->rbdr[i]);
590 data = qspi_endian_xchg(data);
Yuan Yaofebffe82016-03-15 14:36:42 +0800591 if (size < 4)
592 memcpy(rxbuf, &data, size);
593 else
594 memcpy(rxbuf, &data, 4);
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800595 rxbuf++;
596 size -= 4;
597 i++;
598 }
599 qspi_write32(priv->flags, &regs->mcr,
600 qspi_read32(priv->flags, &regs->mcr) |
601 QSPI_MCR_CLR_RXF_MASK);
602 }
603
604 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
605}
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800606
607static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
608{
609 struct fsl_qspi_regs *regs = priv->regs;
610 u32 mcr_reg, data, reg, status_reg, seqid;
611 int i, size, tx_size;
612 u32 to_or_from = 0;
613
614 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
615 qspi_write32(priv->flags, &regs->mcr,
616 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
617 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
618 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
619
620 status_reg = 0;
621 while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
Alexander Steinbeedbc22015-11-04 09:19:10 +0100622 WATCHDOG_RESET();
623
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800624 qspi_write32(priv->flags, &regs->ipcr,
625 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
626 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
627 ;
628
629 qspi_write32(priv->flags, &regs->ipcr,
630 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
631 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
632 ;
633
634 reg = qspi_read32(priv->flags, &regs->rbsr);
635 if (reg & QSPI_RBSR_RDBFL_MASK) {
636 status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
637 status_reg = qspi_endian_xchg(status_reg);
638 }
639 qspi_write32(priv->flags, &regs->mcr,
640 qspi_read32(priv->flags, &regs->mcr) |
641 QSPI_MCR_CLR_RXF_MASK);
642 }
643
644 /* Default is page programming */
645 seqid = SEQID_PP;
Yuan Yaofebffe82016-03-15 14:36:42 +0800646 if (priv->cur_seqid == QSPI_CMD_WRAR)
647 seqid = SEQID_WRAR;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800648#ifdef CONFIG_SPI_FLASH_BAR
649 if (priv->cur_seqid == QSPI_CMD_BRWR)
650 seqid = SEQID_BRWR;
651 else if (priv->cur_seqid == QSPI_CMD_WREAR)
652 seqid = SEQID_WREAR;
653#endif
654
655 to_or_from = priv->sf_addr + priv->cur_amba_base;
656
657 qspi_write32(priv->flags, &regs->sfar, to_or_from);
658
659 tx_size = (len > TX_BUFFER_SIZE) ?
660 TX_BUFFER_SIZE : len;
661
662 size = tx_size / 4;
663 for (i = 0; i < size; i++) {
664 memcpy(&data, txbuf, 4);
665 data = qspi_endian_xchg(data);
666 qspi_write32(priv->flags, &regs->tbdr, data);
667 txbuf += 4;
668 }
669
670 size = tx_size % 4;
671 if (size) {
672 data = 0;
673 memcpy(&data, txbuf, size);
674 data = qspi_endian_xchg(data);
675 qspi_write32(priv->flags, &regs->tbdr, data);
676 }
677
678 qspi_write32(priv->flags, &regs->ipcr,
679 (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
680 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
681 ;
682
683 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
684}
685
Gong Qianyu940d2b82016-01-26 15:06:41 +0800686static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800687{
688 struct fsl_qspi_regs *regs = priv->regs;
689 u32 mcr_reg, reg, data;
690
691 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
692 qspi_write32(priv->flags, &regs->mcr,
693 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
694 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
695 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
696
697 qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
698
699 qspi_write32(priv->flags, &regs->ipcr,
700 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
701 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
702 ;
703
704 while (1) {
705 reg = qspi_read32(priv->flags, &regs->rbsr);
706 if (reg & QSPI_RBSR_RDBFL_MASK) {
707 data = qspi_read32(priv->flags, &regs->rbdr[0]);
708 data = qspi_endian_xchg(data);
Gong Qianyu940d2b82016-01-26 15:06:41 +0800709 memcpy(rxbuf, &data, len);
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800710 qspi_write32(priv->flags, &regs->mcr,
711 qspi_read32(priv->flags, &regs->mcr) |
712 QSPI_MCR_CLR_RXF_MASK);
713 break;
714 }
715 }
716
717 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
718}
719
720static void qspi_op_erase(struct fsl_qspi_priv *priv)
721{
722 struct fsl_qspi_regs *regs = priv->regs;
723 u32 mcr_reg;
724 u32 to_or_from = 0;
725
726 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
727 qspi_write32(priv->flags, &regs->mcr,
728 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
729 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
730 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
731
732 to_or_from = priv->sf_addr + priv->cur_amba_base;
733 qspi_write32(priv->flags, &regs->sfar, to_or_from);
734
735 qspi_write32(priv->flags, &regs->ipcr,
736 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
737 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
738 ;
739
740 if (priv->cur_seqid == QSPI_CMD_SE) {
741 qspi_write32(priv->flags, &regs->ipcr,
742 (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
743 } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
744 qspi_write32(priv->flags, &regs->ipcr,
745 (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
746 }
747 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
748 ;
749
750 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
751}
752
753int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
754 const void *dout, void *din, unsigned long flags)
755{
756 u32 bytes = DIV_ROUND_UP(bitlen, 8);
757 static u32 wr_sfaddr;
758 u32 txbuf;
759
760 if (dout) {
761 if (flags & SPI_XFER_BEGIN) {
762 priv->cur_seqid = *(u8 *)dout;
763 memcpy(&txbuf, dout, 4);
764 }
765
766 if (flags == SPI_XFER_END) {
767 priv->sf_addr = wr_sfaddr;
768 qspi_op_write(priv, (u8 *)dout, bytes);
769 return 0;
770 }
771
Yuan Yaofebffe82016-03-15 14:36:42 +0800772 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
773 priv->cur_seqid == QSPI_CMD_RDAR) {
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800774 priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
775 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
776 (priv->cur_seqid == QSPI_CMD_BE_4K)) {
777 priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
778 qspi_op_erase(priv);
Yuan Yaofebffe82016-03-15 14:36:42 +0800779 } else if (priv->cur_seqid == QSPI_CMD_PP ||
780 priv->cur_seqid == QSPI_CMD_WRAR) {
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800781 wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
782 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
783 (priv->cur_seqid == QSPI_CMD_WREAR)) {
784#ifdef CONFIG_SPI_FLASH_BAR
785 wr_sfaddr = 0;
786#endif
787 }
788 }
789
790 if (din) {
791 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
792#ifdef CONFIG_SYS_FSL_QSPI_AHB
793 qspi_ahb_read(priv, din, bytes);
794#else
795 qspi_op_read(priv, din, bytes);
796#endif
Yuan Yaofebffe82016-03-15 14:36:42 +0800797 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
798 qspi_op_read(priv, din, bytes);
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800799 } else if (priv->cur_seqid == QSPI_CMD_RDID)
800 qspi_op_rdid(priv, din, bytes);
801 else if (priv->cur_seqid == QSPI_CMD_RDSR)
Gong Qianyu940d2b82016-01-26 15:06:41 +0800802 qspi_op_rdsr(priv, din, bytes);
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800803#ifdef CONFIG_SPI_FLASH_BAR
804 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
805 (priv->cur_seqid == QSPI_CMD_RDEAR)) {
806 priv->sf_addr = 0;
807 qspi_op_rdbank(priv, din, bytes);
808 }
809#endif
810 }
811
812#ifdef CONFIG_SYS_FSL_QSPI_AHB
813 if ((priv->cur_seqid == QSPI_CMD_SE) ||
814 (priv->cur_seqid == QSPI_CMD_PP) ||
815 (priv->cur_seqid == QSPI_CMD_BE_4K) ||
816 (priv->cur_seqid == QSPI_CMD_WREAR) ||
817 (priv->cur_seqid == QSPI_CMD_BRWR))
818 qspi_ahb_invalid(priv);
819#endif
820
821 return 0;
822}
823
824void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
825{
826 u32 mcr_val;
827
828 mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
829 if (disable)
830 mcr_val |= QSPI_MCR_MDIS_MASK;
831 else
832 mcr_val &= ~QSPI_MCR_MDIS_MASK;
833 qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
834}
835
836void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
837{
838 u32 smpr_val;
839
840 smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
841 smpr_val &= ~clear_bits;
842 smpr_val |= set_bits;
843 qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
844}
845#ifndef CONFIG_DM_SPI
846static unsigned long spi_bases[] = {
847 QSPI0_BASE_ADDR,
848#ifdef CONFIG_MX6SX
849 QSPI1_BASE_ADDR,
850#endif
851};
852
853static unsigned long amba_bases[] = {
854 QSPI0_AMBA_BASE,
855#ifdef CONFIG_MX6SX
856 QSPI1_AMBA_BASE,
857#endif
858};
859
860static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
861{
862 return container_of(slave, struct fsl_qspi, slave);
Alison Wang6b57ff62014-05-06 09:13:01 +0800863}
864
865struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
866 unsigned int max_hz, unsigned int mode)
867{
868 struct fsl_qspi *qspi;
869 struct fsl_qspi_regs *regs;
Peng Fan5f7f70c2015-01-08 10:40:20 +0800870 u32 total_size;
Alison Wang6b57ff62014-05-06 09:13:01 +0800871
872 if (bus >= ARRAY_SIZE(spi_bases))
873 return NULL;
874
Peng Faned0c81c2014-12-31 11:01:37 +0800875 if (cs >= FSL_QSPI_FLASH_NUM)
876 return NULL;
877
Alison Wang6b57ff62014-05-06 09:13:01 +0800878 qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
879 if (!qspi)
880 return NULL;
881
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800882#ifdef CONFIG_SYS_FSL_QSPI_BE
883 qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
884#endif
885
886 regs = (struct fsl_qspi_regs *)spi_bases[bus];
887 qspi->priv.regs = regs;
Peng Faned0c81c2014-12-31 11:01:37 +0800888 /*
889 * According cs, use different amba_base to choose the
890 * corresponding flash devices.
891 *
892 * If not, only one flash device is used even if passing
893 * different cs using `sf probe`
894 */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800895 qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
Alison Wang6b57ff62014-05-06 09:13:01 +0800896
897 qspi->slave.max_write_size = TX_BUFFER_SIZE;
898
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800899 qspi_write32(qspi->priv.flags, &regs->mcr,
900 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
Alison Wang6b57ff62014-05-06 09:13:01 +0800901
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800902 qspi_cfg_smpr(&qspi->priv,
903 ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
904 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
Alison Wang6b57ff62014-05-06 09:13:01 +0800905
906 total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
Peng Faned0c81c2014-12-31 11:01:37 +0800907 /*
908 * Any read access to non-implemented addresses will provide
909 * undefined results.
910 *
911 * In case single die flash devices, TOP_ADDR_MEMA2 and
912 * TOP_ADDR_MEMB2 should be initialized/programmed to
913 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
914 * setting the size of these devices to 0. This would ensure
915 * that the complete memory map is assigned to only one flash device.
916 */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800917 qspi_write32(qspi->priv.flags, &regs->sfa1ad,
918 FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
919 qspi_write32(qspi->priv.flags, &regs->sfa2ad,
920 FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
921 qspi_write32(qspi->priv.flags, &regs->sfb1ad,
922 total_size | amba_bases[bus]);
923 qspi_write32(qspi->priv.flags, &regs->sfb2ad,
924 total_size | amba_bases[bus]);
Alison Wang6b57ff62014-05-06 09:13:01 +0800925
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800926 qspi_set_lut(&qspi->priv);
Alison Wang6b57ff62014-05-06 09:13:01 +0800927
Peng Fan5f7f70c2015-01-08 10:40:20 +0800928#ifdef CONFIG_SYS_FSL_QSPI_AHB
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800929 qspi_init_ahb_read(&qspi->priv);
Peng Fan5f7f70c2015-01-08 10:40:20 +0800930#endif
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800931
932 qspi_module_disable(&qspi->priv, 0);
933
Alison Wang6b57ff62014-05-06 09:13:01 +0800934 return &qspi->slave;
935}
936
937void spi_free_slave(struct spi_slave *slave)
938{
939 struct fsl_qspi *qspi = to_qspi_spi(slave);
940
941 free(qspi);
942}
943
944int spi_claim_bus(struct spi_slave *slave)
945{
946 return 0;
947}
948
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800949void spi_release_bus(struct spi_slave *slave)
Peng Fana2358782015-01-04 17:07:14 +0800950{
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800951 /* Nothing to do */
Alison Wang6b57ff62014-05-06 09:13:01 +0800952}
953
954int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
955 const void *dout, void *din, unsigned long flags)
956{
957 struct fsl_qspi *qspi = to_qspi_spi(slave);
Alison Wang6b57ff62014-05-06 09:13:01 +0800958
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800959 return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);
960}
Alison Wang6b57ff62014-05-06 09:13:01 +0800961
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800962void spi_init(void)
963{
964 /* Nothing to do */
965}
Peng Fan5f7f70c2015-01-08 10:40:20 +0800966#else
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800967static int fsl_qspi_child_pre_probe(struct udevice *dev)
968{
Simon Glassbcbe3d12015-09-28 23:32:01 -0600969 struct spi_slave *slave = dev_get_parent_priv(dev);
Alison Wang6b57ff62014-05-06 09:13:01 +0800970
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800971 slave->max_write_size = TX_BUFFER_SIZE;
Peng Fan5f7f70c2015-01-08 10:40:20 +0800972
Alison Wang6b57ff62014-05-06 09:13:01 +0800973 return 0;
974}
975
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800976static int fsl_qspi_probe(struct udevice *bus)
977{
Yuan Yao4e147412016-03-15 14:36:41 +0800978 u32 amba_size_per_chip;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800979 struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
980 struct fsl_qspi_priv *priv = dev_get_priv(bus);
981 struct dm_spi_bus *dm_spi_bus;
Yuan Yao4e147412016-03-15 14:36:41 +0800982 int i;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800983
984 dm_spi_bus = bus->uclass_priv;
985
986 dm_spi_bus->max_hz = plat->speed_hz;
987
Gong Qianyuc2a4cb12016-01-26 15:06:39 +0800988 priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800989 priv->flags = plat->flags;
990
991 priv->speed_hz = plat->speed_hz;
Yuan Yaobf9bffa2016-03-15 14:36:40 +0800992 /*
993 * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
994 * AMBA memory zone should be located on the 0~4GB space
995 * even on a 64bits cpu.
996 */
997 priv->amba_base[0] = (u32)plat->amba_base;
998 priv->amba_total_size = (u32)plat->amba_total_size;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +0800999 priv->flash_num = plat->flash_num;
1000 priv->num_chipselect = plat->num_chipselect;
1001
1002 qspi_write32(priv->flags, &priv->regs->mcr,
1003 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
1004
1005 qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
1006 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
1007
Yuan Yao4e147412016-03-15 14:36:41 +08001008 /*
1009 * Assign AMBA memory zone for every chipselect
1010 * QuadSPI has two channels, every channel has two chipselects.
1011 * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
1012 * into two parts and assign to every channel. This indicate that every
1013 * channel only has one valid chipselect.
1014 * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
1015 * into four parts and assign to every chipselect.
1016 * Every channel will has two valid chipselects.
1017 */
1018 amba_size_per_chip = priv->amba_total_size >>
1019 (priv->num_chipselect >> 1);
1020 for (i = 1 ; i < priv->num_chipselect ; i++)
1021 priv->amba_base[i] =
1022 amba_size_per_chip + priv->amba_base[i - 1];
1023
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08001024 /*
1025 * Any read access to non-implemented addresses will provide
1026 * undefined results.
1027 *
1028 * In case single die flash devices, TOP_ADDR_MEMA2 and
1029 * TOP_ADDR_MEMB2 should be initialized/programmed to
1030 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
1031 * setting the size of these devices to 0. This would ensure
1032 * that the complete memory map is assigned to only one flash device.
1033 */
Yuan Yao4e147412016-03-15 14:36:41 +08001034 qspi_write32(priv->flags, &priv->regs->sfa1ad, priv->amba_base[1]);
1035 switch (priv->num_chipselect) {
1036 case 2:
1037 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1038 priv->amba_base[1]);
1039 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1040 priv->amba_base[1] + amba_size_per_chip);
1041 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1042 priv->amba_base[1] + amba_size_per_chip);
1043 break;
1044 case 4:
1045 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1046 priv->amba_base[2]);
1047 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1048 priv->amba_base[3]);
1049 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1050 priv->amba_base[3] + amba_size_per_chip);
1051 break;
1052 default:
1053 debug("Error: Unsupported chipselect number %u!\n",
1054 priv->num_chipselect);
1055 qspi_module_disable(priv, 1);
1056 return -EINVAL;
1057 }
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08001058
1059 qspi_set_lut(priv);
1060
1061#ifdef CONFIG_SYS_FSL_QSPI_AHB
1062 qspi_init_ahb_read(priv);
1063#endif
1064
1065 qspi_module_disable(priv, 0);
1066
1067 return 0;
1068}
1069
1070static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
1071{
Yuan Yaobf9bffa2016-03-15 14:36:40 +08001072 struct fdt_resource res_regs, res_mem;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08001073 struct fsl_qspi_platdata *plat = bus->platdata;
1074 const void *blob = gd->fdt_blob;
1075 int node = bus->of_offset;
1076 int ret, flash_num = 0, subnode;
1077
1078 if (fdtdec_get_bool(blob, node, "big-endian"))
1079 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
1080
Yuan Yaobf9bffa2016-03-15 14:36:40 +08001081 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1082 "QuadSPI", &res_regs);
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08001083 if (ret) {
Yuan Yaobf9bffa2016-03-15 14:36:40 +08001084 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1085 return -ENOMEM;
1086 }
1087 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1088 "QuadSPI-memory", &res_mem);
1089 if (ret) {
1090 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08001091 return -ENOMEM;
1092 }
1093
1094 /* Count flash numbers */
1095 fdt_for_each_subnode(blob, subnode, node)
1096 ++flash_num;
1097
1098 if (flash_num == 0) {
1099 debug("Error: Missing flashes!\n");
1100 return -ENODEV;
1101 }
1102
1103 plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1104 FSL_QSPI_DEFAULT_SCK_FREQ);
1105 plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1106 FSL_QSPI_MAX_CHIPSELECT_NUM);
1107
Yuan Yaobf9bffa2016-03-15 14:36:40 +08001108 plat->reg_base = res_regs.start;
1109 plat->amba_base = res_mem.start;
1110 plat->amba_total_size = res_mem.end - res_mem.start + 1;
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08001111 plat->flash_num = flash_num;
1112
Yuan Yaobf9bffa2016-03-15 14:36:40 +08001113 debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08001114 __func__,
Yuan Yaobf9bffa2016-03-15 14:36:40 +08001115 (u64)plat->reg_base,
1116 (u64)plat->amba_base,
1117 (u64)plat->amba_total_size,
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08001118 plat->speed_hz,
1119 plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1120 );
1121
1122 return 0;
1123}
1124
1125static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1126 const void *dout, void *din, unsigned long flags)
1127{
1128 struct fsl_qspi_priv *priv;
1129 struct udevice *bus;
1130
1131 bus = dev->parent;
1132 priv = dev_get_priv(bus);
1133
1134 return qspi_xfer(priv, bitlen, dout, din, flags);
1135}
1136
1137static int fsl_qspi_claim_bus(struct udevice *dev)
1138{
1139 struct fsl_qspi_priv *priv;
1140 struct udevice *bus;
1141 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1142
1143 bus = dev->parent;
1144 priv = dev_get_priv(bus);
1145
Yuan Yao4e147412016-03-15 14:36:41 +08001146 priv->cur_amba_base = priv->amba_base[slave_plat->cs];
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08001147
1148 qspi_module_disable(priv, 0);
1149
1150 return 0;
1151}
1152
1153static int fsl_qspi_release_bus(struct udevice *dev)
1154{
1155 struct fsl_qspi_priv *priv;
1156 struct udevice *bus;
1157
1158 bus = dev->parent;
1159 priv = dev_get_priv(bus);
1160
1161 qspi_module_disable(priv, 1);
1162
1163 return 0;
1164}
1165
1166static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
Alison Wang6b57ff62014-05-06 09:13:01 +08001167{
1168 /* Nothing to do */
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08001169 return 0;
Alison Wang6b57ff62014-05-06 09:13:01 +08001170}
Haikun.Wang@freescale.com5bc48302015-04-01 11:10:40 +08001171
1172static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1173{
1174 /* Nothing to do */
1175 return 0;
1176}
1177
1178static const struct dm_spi_ops fsl_qspi_ops = {
1179 .claim_bus = fsl_qspi_claim_bus,
1180 .release_bus = fsl_qspi_release_bus,
1181 .xfer = fsl_qspi_xfer,
1182 .set_speed = fsl_qspi_set_speed,
1183 .set_mode = fsl_qspi_set_mode,
1184};
1185
1186static const struct udevice_id fsl_qspi_ids[] = {
1187 { .compatible = "fsl,vf610-qspi" },
1188 { .compatible = "fsl,imx6sx-qspi" },
1189 { }
1190};
1191
1192U_BOOT_DRIVER(fsl_qspi) = {
1193 .name = "fsl_qspi",
1194 .id = UCLASS_SPI,
1195 .of_match = fsl_qspi_ids,
1196 .ops = &fsl_qspi_ops,
1197 .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1198 .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1199 .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1200 .probe = fsl_qspi_probe,
1201 .child_pre_probe = fsl_qspi_child_pre_probe,
1202};
1203#endif