blob: 46335b4b7f7977d8f62e417d95ebe1f3f0def4f5 [file] [log] [blame]
Larry Johnson87dc0962007-12-22 15:16:25 -05001/*
Larry Johnsona87fb1b2009-01-28 15:30:37 -05002 * (C) Copyright 2007-2009
Larry Johnson87dc0962007-12-22 15:16:25 -05003 * Larry Johnson, lrj@acm.org
4 *
5 * (C) Copyright 2006-2007
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
8 * (C) Copyright 2006
9 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
10 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Larry Johnson214398d2008-01-18 21:49:05 -050028/*
Larry Johnson87dc0962007-12-22 15:16:25 -050029 * korat.h - configuration for Korat board
Larry Johnson214398d2008-01-18 21:49:05 -050030 */
Larry Johnson87dc0962007-12-22 15:16:25 -050031#ifndef __CONFIG_H
32#define __CONFIG_H
33
Larry Johnson214398d2008-01-18 21:49:05 -050034/*
Larry Johnson87dc0962007-12-22 15:16:25 -050035 * High Level Configuration Options
Larry Johnson214398d2008-01-18 21:49:05 -050036 */
37#define CONFIG_440EPX 1 /* Specific PPC440EPx */
38#define CONFIG_4xx 1 /* ... PPC4xx family */
Larry Johnson87dc0962007-12-22 15:16:25 -050039#define CONFIG_SYS_CLK_FREQ 33333333
40
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041#ifdef CONFIG_KORAT_PERMANENT
42#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
43#else
44#define CONFIG_SYS_TEXT_BASE 0xF7F60000
45#endif
46
Larry Johnson214398d2008-01-18 21:49:05 -050047#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
48#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Larry Johnson87dc0962007-12-22 15:16:25 -050049
Larry Johnson214398d2008-01-18 21:49:05 -050050/*
Larry Johnson87dc0962007-12-22 15:16:25 -050051 * Manufacturer's information serial EEPROM parameters
Larry Johnson214398d2008-01-18 21:49:05 -050052 */
53#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
Larry Johnson6433fa22008-03-17 11:10:35 -050054#define MAN_INFO_FIELD 2
55#define MAN_INFO_LENGTH 9
Larry Johnson87dc0962007-12-22 15:16:25 -050056#define MAN_MAC_ADDR_FIELD 3
Larry Johnson6433fa22008-03-17 11:10:35 -050057#define MAN_MAC_ADDR_LENGTH 12
Larry Johnson87dc0962007-12-22 15:16:25 -050058
Larry Johnson214398d2008-01-18 21:49:05 -050059/*
60 * Base addresses -- Note these are effective addresses where the actual
61 * resources get mapped (not physical addresses).
62 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
64#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
Larry Johnson87dc0962007-12-22 15:16:25 -050065
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
67#define CONFIG_SYS_FLASH0_SIZE 0x01000000
68#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE)
69#define CONFIG_SYS_FLASH1_TOP 0xF8000000
70#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
71#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
72#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
Wolfgang Denk14d0a022010-10-07 21:51:12 +020073#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
75#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
76#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
77#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
Stefan Roese10954932009-11-12 12:00:49 +010078#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
Larry Johnson87dc0962007-12-22 15:16:25 -050079
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_USB2D0_BASE 0xe0000100
81#define CONFIG_SYS_USB_DEVICE 0xe0000000
82#define CONFIG_SYS_USB_HOST 0xe0000400
83#define CONFIG_SYS_CPLD_BASE 0xc0000000
Larry Johnson87dc0962007-12-22 15:16:25 -050084
Larry Johnson214398d2008-01-18 21:49:05 -050085/*
Larry Johnson87dc0962007-12-22 15:16:25 -050086 * Initial RAM & stack pointer
Larry Johnson214398d2008-01-18 21:49:05 -050087 */
Larry Johnson87dc0962007-12-22 15:16:25 -050088/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#undef CONFIG_SYS_INIT_RAM_DCACHE
90#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +020091#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020092#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidman800eb092010-09-20 08:51:53 +020093#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Larry Johnson87dc0962007-12-22 15:16:25 -050094
Larry Johnson214398d2008-01-18 21:49:05 -050095/*
Larry Johnson87dc0962007-12-22 15:16:25 -050096 * Serial Port
Larry Johnson214398d2008-01-18 21:49:05 -050097 */
Stefan Roese550650d2010-09-20 16:05:31 +020098#define CONFIG_CONS_INDEX 1 /* Use UART0 */
99#define CONFIG_SYS_NS16550
100#define CONFIG_SYS_NS16550_SERIAL
101#define CONFIG_SYS_NS16550_REG_SIZE 1
102#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
Larry Johnson87dc0962007-12-22 15:16:25 -0500104#define CONFIG_BAUDRATE 115200
105#define CONFIG_SERIAL_MULTI 1
Larry Johnson87dc0962007-12-22 15:16:25 -0500106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_BAUDRATE_TABLE \
Larry Johnson87dc0962007-12-22 15:16:25 -0500108 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
109
Larry Johnson214398d2008-01-18 21:49:05 -0500110/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500111 * Environment
Larry Johnson214398d2008-01-18 21:49:05 -0500112 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200113#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
Larry Johnson87dc0962007-12-22 15:16:25 -0500114
Larry Johnson214398d2008-01-18 21:49:05 -0500115/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500116 * FLASH related
Larry Johnson214398d2008-01-18 21:49:05 -0500117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200119#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Larry Johnson6433fa22008-03-17 11:10:35 -0500120#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
Larry Johnson87dc0962007-12-22 15:16:25 -0500121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
Larry Johnson87dc0962007-12-22 15:16:25 -0500123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
125#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
Larry Johnson87dc0962007-12-22 15:16:25 -0500126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
128#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Larry Johnson87dc0962007-12-22 15:16:25 -0500129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
131#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Larry Johnson87dc0962007-12-22 15:16:25 -0500132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
134#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Larry Johnson87dc0962007-12-22 15:16:25 -0500135
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200136#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200138#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Larry Johnson87dc0962007-12-22 15:16:25 -0500139
Larry Johnson6433fa22008-03-17 11:10:35 -0500140/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200141#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
142#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Larry Johnson87dc0962007-12-22 15:16:25 -0500143
Larry Johnson214398d2008-01-18 21:49:05 -0500144/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500145 * DDR SDRAM
Larry Johnson214398d2008-01-18 21:49:05 -0500146 */
Larry Johnson214398d2008-01-18 21:49:05 -0500147#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
148#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
149#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
150#define CONFIG_DDR_ECC /* Use ECC when available */
Larry Johnson87dc0962007-12-22 15:16:25 -0500151#define SPD_EEPROM_ADDRESS {0x50}
152#define CONFIG_PROG_SDRAM_TLB
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500153#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */
154 /* per 440EPx Errata CHIP_11 */
Larry Johnson87dc0962007-12-22 15:16:25 -0500155
Larry Johnson214398d2008-01-18 21:49:05 -0500156/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500157 * I2C
Larry Johnson214398d2008-01-18 21:49:05 -0500158 */
159#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
160#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200161#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
163#define CONFIG_SYS_I2C_SLAVE 0x7F
Larry Johnson87dc0962007-12-22 15:16:25 -0500164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_I2C_MULTI_EEPROMS
166#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
167#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
168#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
169#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Larry Johnson87dc0962007-12-22 15:16:25 -0500170
171/* I2C RTC */
172#define CONFIG_RTC_M41T60 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Larry Johnson87dc0962007-12-22 15:16:25 -0500174
175/* I2C SYSMON (LM73) */
Larry Johnson214398d2008-01-18 21:49:05 -0500176#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
177#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_DTT_MAX_TEMP 70
179#define CONFIG_SYS_DTT_MIN_TEMP -30
Larry Johnson87dc0962007-12-22 15:16:25 -0500180
181#define CONFIG_PREBOOT "echo;" \
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500182 "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
Larry Johnson87dc0962007-12-22 15:16:25 -0500183 "echo"
184
185#undef CONFIG_BOOTARGS
186
187/* Setup some board specific values for the default environment variables */
188#define CONFIG_HOSTNAME korat
Larry Johnson87dc0962007-12-22 15:16:25 -0500189
Larry Johnson6433fa22008-03-17 11:10:35 -0500190/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
Larry Johnson47ce4a22008-06-14 16:53:02 -0400191#define CONFIG_EXTRA_ENV_SETTINGS \
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500192 "u_boot=korat/u-boot.bin\0" \
193 "load=tftp 200000 ${u_boot}\0" \
194 "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \
195 "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \
196 "F7F60000 F7FBFFFF\0" \
197 "upd=run load update\0" \
198 "bootfile=korat/uImage\0" \
199 "dtb=korat/korat.dtb\0" \
200 "kernel_addr=F4000000\0" \
201 "ramdisk_addr=F4400000\0" \
202 "dtb_addr=F41E0000\0" \
203 "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \
204 "cp.b ${fileaddr} F4000000 ${filesize}\0" \
205 "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \
206 "cp.b ${fileaddr} F41E0000 ${filesize}\0" \
207 "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \
208 "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \
209 "${dtb}\0" \
210 "rd_size=73728\0" \
211 "ramargs=setenv bootargs root=/dev/ram rw " \
212 "ramdisk_size=${rd_size}\0" \
213 "usbdev=sda1\0" \
214 "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \
215 "rootpath=/opt/eldk/ppc_4xxFP\0" \
Larry Johnson87dc0962007-12-22 15:16:25 -0500216 "netdev=eth0\0" \
217 "nfsargs=setenv bootargs root=/dev/nfs rw " \
218 "nfsroot=${serverip}:${rootpath}\0" \
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500219 "pciclk=33\0" \
220 "addide=setenv bootargs ${bootargs} ide=reverse " \
221 "idebus=${pciclk}\0" \
Larry Johnson87dc0962007-12-22 15:16:25 -0500222 "addip=setenv bootargs ${bootargs} " \
223 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
224 ":${hostname}:${netdev}:off panic=1\0" \
225 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500226 "flash_cf=run usbargs addide addip addtty; " \
227 "bootm ${kernel_addr} - ${dtb_addr}\0" \
228 "flash_nfs=run nfsargs addide addip addtty; " \
229 "bootm ${kernel_addr} - ${dtb_addr}\0" \
230 "flash_self=run ramargs addip addtty; " \
231 "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \
Larry Johnson87dc0962007-12-22 15:16:25 -0500232 ""
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500233
234#define CONFIG_BOOTCOMMAND "run flash_cf"
Larry Johnson87dc0962007-12-22 15:16:25 -0500235
Larry Johnson214398d2008-01-18 21:49:05 -0500236#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
Larry Johnson87dc0962007-12-22 15:16:25 -0500237
Larry Johnson214398d2008-01-18 21:49:05 -0500238#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Larry Johnson87dc0962007-12-22 15:16:25 -0500240
Ben Warren96e21f82008-10-27 23:50:15 -0700241#define CONFIG_PPC4xx_EMAC
Larry Johnson47ce4a22008-06-14 16:53:02 -0400242#define CONFIG_IBM_EMAC4_V4 1
Larry Johnson214398d2008-01-18 21:49:05 -0500243#define CONFIG_MII 1 /* MII PHY management */
244#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
Larry Johnson87dc0962007-12-22 15:16:25 -0500245#define CONFIG_PHY_DYNAMIC_ANEG 1
246
Larry Johnson6433fa22008-03-17 11:10:35 -0500247#undef CONFIG_PHY_RESET /* Don't do software PHY reset */
Larry Johnson87dc0962007-12-22 15:16:25 -0500248#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
249
250#define CONFIG_HAS_ETH0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */
Larry Johnson214398d2008-01-18 21:49:05 -0500252 /* buffers & descriptors */
Larry Johnson214398d2008-01-18 21:49:05 -0500253#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
Larry Johnson87dc0962007-12-22 15:16:25 -0500254#define CONFIG_PHY1_ADDR 3
255
256/* USB */
257#define CONFIG_USB_OHCI
258#define CONFIG_USB_STORAGE
259
260/* Comment this out to enable USB 1.1 device */
261#define USB_2_0_DEVICE
262
263/* Partitions */
264#define CONFIG_MAC_PARTITION
265#define CONFIG_DOS_PARTITION
266#define CONFIG_ISO_PARTITION
267
268/*
269 * BOOTP options
270 */
271#define CONFIG_BOOTP_BOOTFILESIZE
272#define CONFIG_BOOTP_BOOTPATH
273#define CONFIG_BOOTP_GATEWAY
274#define CONFIG_BOOTP_HOSTNAME
275#define CONFIG_BOOTP_SUBNETMASK
276
277/*
278 * Command line configuration.
279 */
280#include <config_cmd_default.h>
281
282#define CONFIG_CMD_ASKENV
283#define CONFIG_CMD_DATE
284#define CONFIG_CMD_DHCP
285#define CONFIG_CMD_DTT
286#define CONFIG_CMD_DIAG
287#define CONFIG_CMD_EEPROM
288#define CONFIG_CMD_ELF
289#define CONFIG_CMD_FAT
290#define CONFIG_CMD_I2C
Larry Johnson87dc0962007-12-22 15:16:25 -0500291#define CONFIG_CMD_IRQ
292#define CONFIG_CMD_MII
293#define CONFIG_CMD_NET
294#define CONFIG_CMD_NFS
295#define CONFIG_CMD_PCI
296#define CONFIG_CMD_PING
297#define CONFIG_CMD_REGINFO
298#define CONFIG_CMD_SDRAM
299#define CONFIG_CMD_USB
300
301/* POST support */
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500302#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
303 CONFIG_SYS_POST_CPU | \
304 CONFIG_SYS_POST_ECC | \
305 CONFIG_SYS_POST_ETHER | \
306 CONFIG_SYS_POST_FPU | \
307 CONFIG_SYS_POST_I2C | \
308 CONFIG_SYS_POST_MEMORY | \
309 CONFIG_SYS_POST_RTC | \
310 CONFIG_SYS_POST_SPR | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311 CONFIG_SYS_POST_UART)
Larry Johnson87dc0962007-12-22 15:16:25 -0500312
Larry Johnson87dc0962007-12-22 15:16:25 -0500313#define CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
Larry Johnson87dc0962007-12-22 15:16:25 -0500315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Larry Johnson87dc0962007-12-22 15:16:25 -0500317
318#define CONFIG_SUPPORT_VFAT
319
Larry Johnson214398d2008-01-18 21:49:05 -0500320/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500321 * Miscellaneous configurable options
Larry Johnson214398d2008-01-18 21:49:05 -0500322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_LONGHELP /* undef to save memory */
324#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Larry Johnson87dc0962007-12-22 15:16:25 -0500325#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Larry Johnson87dc0962007-12-22 15:16:25 -0500327#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Larry Johnson87dc0962007-12-22 15:16:25 -0500329#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200331 /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
333#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Larry Johnson87dc0962007-12-22 15:16:25 -0500334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
336#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Larry Johnson87dc0962007-12-22 15:16:25 -0500337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
339#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Larry Johnson87dc0962007-12-22 15:16:25 -0500340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Larry Johnson87dc0962007-12-22 15:16:25 -0500342
Larry Johnson214398d2008-01-18 21:49:05 -0500343#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
344#define CONFIG_LOOPW 1 /* enable loopw command */
345#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
346#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
347#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
Larry Johnson87dc0962007-12-22 15:16:25 -0500348
Larry Johnson214398d2008-01-18 21:49:05 -0500349/*
Larry Johnson6433fa22008-03-17 11:10:35 -0500350 * Korat-specific options
351 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
Larry Johnson6433fa22008-03-17 11:10:35 -0500353
354/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500355 * PCI stuff
Larry Johnson214398d2008-01-18 21:49:05 -0500356 */
Larry Johnson87dc0962007-12-22 15:16:25 -0500357/* General PCI */
Larry Johnson214398d2008-01-18 21:49:05 -0500358#define CONFIG_PCI /* include pci support */
359#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
Larry Johnson214398d2008-01-18 21:49:05 -0500361#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
363 /* CONFIG_SYS_PCI_MEMBASE */
Larry Johnson87dc0962007-12-22 15:16:25 -0500364/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_PCI_TARGET_INIT
366#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roesea760b022009-11-12 16:41:09 +0100367#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
Larry Johnson87dc0962007-12-22 15:16:25 -0500368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
370#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
Larry Johnson87dc0962007-12-22 15:16:25 -0500371
372/*
Larry Johnson214398d2008-01-18 21:49:05 -0500373 * For booting Linux, the board info and command line data have to be in the
374 * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
375 * during initialization.
Larry Johnson87dc0962007-12-22 15:16:25 -0500376 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Larry Johnson87dc0962007-12-22 15:16:25 -0500378
Larry Johnson214398d2008-01-18 21:49:05 -0500379/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500380 * External Bus Controller (EBC) Setup
Larry Johnson214398d2008-01-18 21:49:05 -0500381 */
Larry Johnson87dc0962007-12-22 15:16:25 -0500382
383/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
385#define CONFIG_SYS_EBC_PB0AP 0x04017300
386#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
387#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
388#define CONFIG_SYS_EBC_PB0AP 0x04017300
389#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
Larry Johnson6433fa22008-03-17 11:10:35 -0500390#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
Larry Johnson6433fa22008-03-17 11:10:35 -0500392#endif
Larry Johnson87dc0962007-12-22 15:16:25 -0500393
394/* Memory Bank 1 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
396#define CONFIG_SYS_EBC_PB1AP 0x04017300
397#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
Larry Johnson6433fa22008-03-17 11:10:35 -0500398#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
Larry Johnson6433fa22008-03-17 11:10:35 -0500400#endif
Larry Johnson87dc0962007-12-22 15:16:25 -0500401
402/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_EBC_PB2AP 0x04017300
404#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000)
Larry Johnson87dc0962007-12-22 15:16:25 -0500405
Larry Johnson214398d2008-01-18 21:49:05 -0500406/*
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500407 * GPIO Setup
408 *
409 * Korat GPIO usage:
410 *
411 * Init.
412 * Pin Source I/O value Function
413 * ------ ------ --- ----- ---------------------------------
414 * GPIO00 Alt1 I/O x PerAddr07
415 * GPIO01 Alt1 I/O x PerAddr06
416 * GPIO02 Alt1 I/O x PerAddr05
417 * GPIO03 GPIO x x GPIO03 to expansion bus connector
418 * GPIO04 GPIO x x GPIO04 to expansion bus connector
419 * GPIO05 GPIO x x GPIO05 to expansion bus connector
420 * GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
421 * GPIO07 Alt1 O x PerCS2 (CPLD)
422 * GPIO08 Alt1 O x PerCS3 to expansion bus connector
423 * GPIO09 Alt1 O x PerCS4 to expansion bus connector
424 * GPIO10 Alt1 O x PerCS5 to expansion bus connector
425 * GPIO11 Alt1 I x PerErr
426 * GPIO12 GPIO O 0 ATMega !Reset
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500427 * GPIO13 GPIO x x Test Point 2 (TP2)
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500428 * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
429 * GPIO15 GPIO O 0 CPU Run LED !On
430 * GPIO16 Alt1 O x GMC1TxD0
431 * GPIO17 Alt1 O x GMC1TxD1
432 * GPIO18 Alt1 O x GMC1TxD2
433 * GPIO19 Alt1 O x GMC1TxD3
434 * GPIO20 Alt1 I x RejectPkt0
435 * GPIO21 Alt1 I x RejectPkt1
436 * GPIO22 GPIO I x PGOOD_DDR
437 * GPIO23 Alt1 O x SCPD0
438 * GPIO24 Alt1 O x GMC0TxD2
439 * GPIO25 Alt1 O x GMC0TxD3
440 * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
441 * GPIO27 GPIO O 0 PHY #0 1000BASE-X select
442 * GPIO28 GPIO O 0 PHY #1 1000BASE-X select
443 * GPIO29 GPIO I x Test jumper !Present
444 * GPIO30 GPIO I x SFP module #0 !Present
445 * GPIO31 GPIO I x SFP module #1 !Present
446 *
447 * GPIO32 GPIO O 1 SFP module #0 Tx !Enable
448 * GPIO33 GPIO O 1 SFP module #1 Tx !Enable
449 * GPIO34 Alt2 I x !UART1_CTS
450 * GPIO35 Alt2 O x !UART1_RTS
451 * GPIO36 Alt1 I x !UART0_CTS
452 * GPIO37 Alt1 O x !UART0_RTS
453 * GPIO38 Alt2 O x UART1_Tx
454 * GPIO39 Alt2 I x UART1_Rx
455 * GPIO40 Alt1 I x IRQ0 (Ethernet 0)
456 * GPIO41 Alt1 I x IRQ1 (Ethernet 1)
457 * GPIO42 Alt1 I x IRQ2 (PCI interrupt)
458 * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
459 * GPIO44 xxxx x x (grounded through pulldown)
460 * GPIO45 GPIO O 0 PHY #0 Enable
461 * GPIO46 GPIO O 0 PHY #1 Enable
462 * GPIO47 GPIO I x Reset switch !Pressed
463 * GPIO48 GPIO I x Shutdown switch !Pressed
464 * GPIO49 xxxx x x (reserved for trace port)
465 * . . . . .
466 * . . . . .
467 * . . . . .
468 * GPIO63 xxxx x x (reserved for trace port)
Larry Johnson214398d2008-01-18 21:49:05 -0500469 */
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500470
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12
472#define CONFIG_SYS_GPIO_ATMEGA_SS_ 13
473#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27
474#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28
475#define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30
476#define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31
477#define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32
478#define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33
479#define CONFIG_SYS_GPIO_PHY0_EN 45
480#define CONFIG_SYS_GPIO_PHY1_EN 46
481#define CONFIG_SYS_GPIO_RESET_PRESSED_ 47
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500482
Larry Johnson214398d2008-01-18 21:49:05 -0500483/*
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500484 * PPC440 GPIO Configuration
485 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500487{ \
488/* GPIO Core 0 */ \
489{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
490{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
491{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
492{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
493{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
494{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
495{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
496{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
497{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
498{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
499{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
500{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
501{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500502{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500503{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
504{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
505{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
506{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
507{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
508{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
509{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
510{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
511{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
512{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
513{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
514{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
515{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
516{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
517{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
518{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
519{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
520{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
521}, \
522{ \
523/* GPIO Core 1 */ \
524{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
525{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
526{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
527{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
528{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
529{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
530{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
531{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
532{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
533{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
534{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
535{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
536{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
537{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
538{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
539{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
540{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
541{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
542{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
543{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
544{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
545{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
546{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
547{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
548{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
549{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
550{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
551{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
552{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
553{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
554{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
555{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
556} \
557}
558
Larry Johnson87dc0962007-12-22 15:16:25 -0500559#if defined(CONFIG_CMD_KGDB)
Larry Johnson214398d2008-01-18 21:49:05 -0500560#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
561#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
Larry Johnson87dc0962007-12-22 15:16:25 -0500562#endif
Larry Johnson214398d2008-01-18 21:49:05 -0500563
Larry Johnson47ce4a22008-06-14 16:53:02 -0400564/* Pass open firmware flat tree */
565#define CONFIG_OF_LIBFDT 1
566#define CONFIG_OF_BOARD_SETUP 1
567
Larry Johnson87dc0962007-12-22 15:16:25 -0500568#endif /* __CONFIG_H */