blob: 3418d4e2b55972964d0640ec89d237e0903c186a [file] [log] [blame]
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +01001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2017-2019 A. Karas, SomLabs
4 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
5 *
6 * Configuration settings for the SoMlabs VisionSOM 6ULL board.
7 */
8#ifndef __SOMLABS_VISIONSOM_6ULL_H
9#define __SOMLABS_VISIONSOM_6ULL_H
10
11#include <asm/arch/imx-regs.h>
12#include <linux/sizes.h>
13#include "mx6_common.h"
14#include <asm/mach-imx/gpio.h>
15
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010016/* MMC Configs */
17#ifdef CONFIG_FSL_USDHC
Tom Rini6cc04542022-10-28 20:27:13 -040018#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010019
Tom Rini6cc04542022-10-28 20:27:13 -040020#define CFG_SYS_FSL_USDHC_NUM 1
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010021#endif /* CONFIG_FSL_USDHC */
22
Tom Rini0613c362022-12-04 10:03:50 -050023#define CFG_EXTRA_ENV_SETTINGS \
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010024 "bootm_size=0x10000000\0" \
25 "console=ttymxc0\0" \
26 "initrd_addr=0x86800000\0" \
27 "fdt_addr=0x83000000\0" \
28 "script=boot.scr\0" \
29 "image=zImage\0" \
30 "splashimage=0x80000000\0" \
31 "splashfile=/boot/splash.bmp\0" \
32 "mmcdev=1\0" \
33 "mmcpart=1\0" \
34 "mmcroot=/dev/mmcblk1p1 rootwait rw\0" \
35 "setrootmmc=setenv rootspec root=${mmcroot}\0" \
36 "setbootscriptmmc=setenv loadbootscript " \
37 "load mmc ${mmcdev}:${mmcpart} " \
38 "${loadaddr} /boot/${script};\0" \
39 "setloadmmc=setenv loadimage load mmc ${mmcdev}:${mmcpart} " \
40 "${loadaddr} /boot/${image}; " \
41 "setenv loadfdt load mmc ${mmcdev}:${mmcpart} " \
42 "${fdt_addr} /boot/${fdt_file};\0" \
43 "setbootargs=setenv bootargs console=${console},${baudrate} " \
44 "${rootspec}\0" \
45 "execbootscript=echo Running bootscript...; source\0" \
46 "setfdtfile=setenv fdt_file somlabs-visionsom-6ull.dtb\0" \
47 "checkbootdev=run setbootscriptmmc; " \
48 "run setrootmmc; " \
49 "run setloadmmc; " \
50
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010051/* Miscellaneous configurable options */
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010052
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010053/* Physical Memory Map */
54#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
55
Tom Riniaa6e94d2022-11-16 13:10:37 -050056#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
Tom Rini65cc0e22022-11-16 13:10:41 -050057#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
58#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010059
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010060/* environment organization */
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010061
62/* USB Configs */
63#ifdef CONFIG_CMD_USB
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010064#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
65#define CONFIG_MXC_USB_FLAGS 0
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010066#endif
67
68#ifdef CONFIG_CMD_NET
Tom Rinifa760c32022-12-04 10:03:53 -050069#define CFG_FEC_MXC_PHYADDR 0x1
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010070#endif
71
Arkadiusz Karas5b6f8f32020-01-02 19:31:21 +010072#endif