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wdenk42d1f032003-10-15 23:53:47 +00001/*
Dipen Dudhatbeba93e2011-01-19 12:46:27 +05302 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +000010 */
11
Andy Fleming75b9d4a2008-08-31 16:33:26 -050012#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000013#include <common.h>
14#include <watchdog.h>
15#include <command.h>
Andy Fleming80522dc2008-10-30 16:51:33 -050016#include <fsl_esdhc.h>
wdenk42d1f032003-10-15 23:53:47 +000017#include <asm/cache.h>
Sergei Poselenov740280e2008-06-06 15:42:40 +020018#include <asm/io.h>
Becky Bruce199e2622010-06-17 11:37:25 -050019#include <asm/mmu.h>
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053020#include <asm/fsl_ifc.h>
Becky Bruce199e2622010-06-17 11:37:25 -050021#include <asm/fsl_law.h>
Becky Bruce38dba0c2010-12-17 17:17:56 -060022#include <asm/fsl_lbc.h>
York Sunebbe11d2010-09-28 15:20:33 -070023#include <post.h>
24#include <asm/processor.h>
York Sun5614e712013-09-30 09:22:09 -070025#include <fsl_ddr_sdram.h>
wdenk42d1f032003-10-15 23:53:47 +000026
James Yang591933c2008-02-08 16:44:53 -060027DECLARE_GLOBAL_DATA_PTR;
28
Ira W. Snyderc18de0d2011-11-21 13:20:32 -080029/*
30 * Default board reset function
31 */
32static void
33__board_reset(void)
34{
35 /* Do nothing */
36}
37void board_reset(void) __attribute__((weak, alias("__board_reset")));
38
wdenk42d1f032003-10-15 23:53:47 +000039int checkcpu (void)
40{
wdenk97d80fc2004-06-09 00:34:46 +000041 sys_info_t sysinfo;
wdenk97d80fc2004-06-09 00:34:46 +000042 uint pvr, svr;
43 uint ver;
44 uint major, minor;
Kumar Gala4dbdb762008-06-10 16:53:46 -050045 struct cpu_type *cpu;
Wolfgang Denk08ef89e2008-10-19 02:35:49 +020046 char buf1[32], buf2[32];
York Sunf165bc32013-06-25 11:37:43 -070047#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
48 ccsr_gur_t __iomem *gur =
49 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50#endif
York Sun98ffa192012-10-08 07:44:31 +000051
52 /*
53 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
54 * mode. Previous platform use ddr ratio to do the same. This
55 * information is only for display here.
56 */
57#ifdef CONFIG_FSL_CORENET
58#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
59 u32 ddr_sync = 0; /* only async mode is supported */
60#else
61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
63#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
64#else /* CONFIG_FSL_CORENET */
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080065#ifdef CONFIG_DDR_CLK_FREQ
66 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
67 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
68#else
Kumar Galaee1e35b2008-05-29 01:21:24 -050069 u32 ddr_ratio = 0;
Kumar Gala39aaca12009-03-19 02:46:19 -050070#endif /* CONFIG_DDR_CLK_FREQ */
York Sun98ffa192012-10-08 07:44:31 +000071#endif /* CONFIG_FSL_CORENET */
72
Timur Tabifbb9ecf2011-08-05 16:15:24 -050073 unsigned int i, core, nr_cores = cpu_numcores();
74 u32 mask = cpu_mask();
wdenk42d1f032003-10-15 23:53:47 +000075
wdenk97d80fc2004-06-09 00:34:46 +000076 svr = get_svr();
wdenk97d80fc2004-06-09 00:34:46 +000077 major = SVR_MAJ(svr);
78 minor = SVR_MIN(svr);
79
Poonam Aggrwal0e870982009-07-31 12:08:14 +053080 if (cpu_numcores() > 1) {
Poonam Aggrwal21170c82009-09-03 19:42:40 +053081#ifndef CONFIG_MP
82 puts("Unicore software on multiprocessor system!!\n"
83 "To enable mutlticore build define CONFIG_MP\n");
84#endif
Kim Phillips680c6132010-08-09 18:39:57 -050085 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Poonam Aggrwal0e870982009-07-31 12:08:14 +053086 printf("CPU%d: ", pic->whoami);
87 } else {
88 puts("CPU: ");
89 }
Andy Fleming1ced1212008-02-06 01:19:40 -060090
Simon Glass67ac13b2012-12-13 20:48:48 +000091 cpu = gd->arch.cpu;
Poonam Aggrwal0e870982009-07-31 12:08:14 +053092
Poonam Aggrwal58442dc2009-09-02 13:35:21 +053093 puts(cpu->name);
94 if (IS_E_PROCESSOR(svr))
95 puts("E");
Andy Fleming1ced1212008-02-06 01:19:40 -060096
wdenk97d80fc2004-06-09 00:34:46 +000097 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk42d1f032003-10-15 23:53:47 +000098
wdenk6c9e7892005-03-15 22:56:53 +000099 pvr = get_pvr();
100 ver = PVR_VER(pvr);
101 major = PVR_MAJ(pvr);
102 minor = PVR_MIN(pvr);
103
104 printf("Core: ");
Kumar Gala89927382011-07-25 09:28:39 -0500105 switch(ver) {
106 case PVR_VER_E500_V1:
107 case PVR_VER_E500_V2:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300108 puts("e500");
Kumar Gala89927382011-07-25 09:28:39 -0500109 break;
110 case PVR_VER_E500MC:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300111 puts("e500mc");
Kumar Gala89927382011-07-25 09:28:39 -0500112 break;
113 case PVR_VER_E5500:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300114 puts("e5500");
Kumar Gala89927382011-07-25 09:28:39 -0500115 break;
Kumar Gala5b6b85a2012-08-17 08:20:23 +0000116 case PVR_VER_E6500:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300117 puts("e6500");
Kumar Gala5b6b85a2012-08-17 08:20:23 +0000118 break;
Kumar Gala89927382011-07-25 09:28:39 -0500119 default:
Kumar Gala2a3a96c2009-10-21 13:23:54 -0500120 puts("Unknown");
Kumar Gala89927382011-07-25 09:28:39 -0500121 break;
wdenk6c9e7892005-03-15 22:56:53 +0000122 }
Kumar Gala0f060c32008-10-23 01:47:38 -0500123
wdenk6c9e7892005-03-15 22:56:53 +0000124 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
125
York Sun2f1712b2012-10-08 07:44:10 +0000126 if (nr_cores > CONFIG_MAX_CPUS) {
127 panic("\nUnexpected number of cores: %d, max is %d\n",
128 nr_cores, CONFIG_MAX_CPUS);
129 }
130
wdenk97d80fc2004-06-09 00:34:46 +0000131 get_sys_info(&sysinfo);
132
Kumar Galab29dee32009-02-04 09:35:57 -0600133 puts("Clock Configuration:");
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500134 for_each_cpu(i, core, nr_cores, mask) {
Wolfgang Denk1bba30e2009-02-19 00:41:08 +0100135 if (!(i & 3))
136 printf ("\n ");
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500137 printf("CPU%d:%-4s MHz, ", core,
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530138 strmhz(buf1, sysinfo.freq_processor[core]));
Kumar Galab29dee32009-02-04 09:35:57 -0600139 }
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530140 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
141 printf("\n");
Kumar Galaee1e35b2008-05-29 01:21:24 -0500142
Kumar Gala39aaca12009-03-19 02:46:19 -0500143#ifdef CONFIG_FSL_CORENET
144 if (ddr_sync == 1) {
145 printf(" DDR:%-4s MHz (%s MT/s data rate) "
146 "(Synchronous), ",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530147 strmhz(buf1, sysinfo.freq_ddrbus/2),
148 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Gala39aaca12009-03-19 02:46:19 -0500149 } else {
150 printf(" DDR:%-4s MHz (%s MT/s data rate) "
151 "(Asynchronous), ",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530152 strmhz(buf1, sysinfo.freq_ddrbus/2),
153 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Gala39aaca12009-03-19 02:46:19 -0500154 }
155#else
Kumar Galad4357932007-12-07 04:59:26 -0600156 switch (ddr_ratio) {
157 case 0x0:
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200158 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530159 strmhz(buf1, sysinfo.freq_ddrbus/2),
160 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Galad4357932007-12-07 04:59:26 -0600161 break;
162 case 0x7:
Kumar Gala39aaca12009-03-19 02:46:19 -0500163 printf(" DDR:%-4s MHz (%s MT/s data rate) "
164 "(Synchronous), ",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530165 strmhz(buf1, sysinfo.freq_ddrbus/2),
166 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Galad4357932007-12-07 04:59:26 -0600167 break;
168 default:
Kumar Gala39aaca12009-03-19 02:46:19 -0500169 printf(" DDR:%-4s MHz (%s MT/s data rate) "
170 "(Asynchronous), ",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530171 strmhz(buf1, sysinfo.freq_ddrbus/2),
172 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Galad4357932007-12-07 04:59:26 -0600173 break;
174 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500175#endif
wdenk97d80fc2004-06-09 00:34:46 +0000176
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530177#if defined(CONFIG_FSL_LBC)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530178 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
179 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
Kumar Gala39aaca12009-03-19 02:46:19 -0500180 } else {
Trent Piephoada591d2008-12-03 15:16:37 -0800181 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530182 sysinfo.freq_localbus);
Kumar Gala39aaca12009-03-19 02:46:19 -0500183 }
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530184#endif
wdenk97d80fc2004-06-09 00:34:46 +0000185
Kumar Gala800c73c2012-10-08 07:44:06 +0000186#if defined(CONFIG_FSL_IFC)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530187 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
Kumar Gala800c73c2012-10-08 07:44:06 +0000188#endif
189
Andy Fleming1ced1212008-02-06 01:19:40 -0600190#ifdef CONFIG_CPM2
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530191 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
Andy Fleming1ced1212008-02-06 01:19:40 -0600192#endif
wdenk97d80fc2004-06-09 00:34:46 +0000193
Haiying Wangb3d7f202009-05-20 12:30:29 -0400194#ifdef CONFIG_QE
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530195 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
Haiying Wangb3d7f202009-05-20 12:30:29 -0400196#endif
197
Kumar Gala39aaca12009-03-19 02:46:19 -0500198#ifdef CONFIG_SYS_DPAA_FMAN
199 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
Emil Medve7eda1f82010-06-17 00:08:29 -0500200 printf(" FMAN%d: %s MHz\n", i + 1,
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530201 strmhz(buf1, sysinfo.freq_fman[i]));
Kumar Gala39aaca12009-03-19 02:46:19 -0500202 }
203#endif
204
Haiying Wang990e1a82012-10-11 07:13:39 +0000205#ifdef CONFIG_SYS_DPAA_QBMAN
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530206 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
Haiying Wang990e1a82012-10-11 07:13:39 +0000207#endif
208
Kumar Gala39aaca12009-03-19 02:46:19 -0500209#ifdef CONFIG_SYS_DPAA_PME
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530210 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
Kumar Gala39aaca12009-03-19 02:46:19 -0500211#endif
212
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500213 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000214
York Sunf165bc32013-06-25 11:37:43 -0700215#ifdef CONFIG_FSL_CORENET
216 /* Display the RCW, so that no one gets confused as to what RCW
217 * we're actually using for this boot.
218 */
219 puts("Reset Configuration Word (RCW):");
220 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
221 u32 rcw = in_be32(&gur->rcwsr[i]);
222
223 if ((i % 4) == 0)
224 printf("\n %08x:", i * 4);
225 printf(" %08x", rcw);
226 }
227 puts("\n");
228#endif
229
wdenk42d1f032003-10-15 23:53:47 +0000230 return 0;
231}
232
233
234/* ------------------------------------------------------------------------- */
235
Mike Frysinger882b7d72010-10-20 03:41:17 -0400236int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenk42d1f032003-10-15 23:53:47 +0000237{
Kumar Galac3483222009-09-08 13:46:46 -0500238/* Everything after the first generation of PQ3 parts has RSTCR */
239#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
240 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
Sergei Poselenov793670c2008-05-08 14:17:08 +0200241 unsigned long val, msr;
242
wdenk42d1f032003-10-15 23:53:47 +0000243 /*
244 * Initiate hard reset in debug control register DBCR0
Kumar Galac3483222009-09-08 13:46:46 -0500245 * Make sure MSR[DE] = 1. This only resets the core.
wdenk42d1f032003-10-15 23:53:47 +0000246 */
Sergei Poselenov793670c2008-05-08 14:17:08 +0200247 msr = mfmsr ();
248 msr |= MSR_DE;
249 mtmsr (msr);
urwithsughosh@gmail.comdf909682007-09-24 13:32:13 -0400250
Sergei Poselenov793670c2008-05-08 14:17:08 +0200251 val = mfspr(DBCR0);
252 val |= 0x70000000;
253 mtspr(DBCR0,val);
Kumar Galac3483222009-09-08 13:46:46 -0500254#else
255 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Ira W. Snyderc18de0d2011-11-21 13:20:32 -0800256
257 /* Attempt board-specific reset */
258 board_reset();
259
260 /* Next try asserting HRESET_REQ */
261 out_be32(&gur->rstcr, 0x2);
Kumar Galac3483222009-09-08 13:46:46 -0500262 udelay(100);
263#endif
Sergei Poselenov793670c2008-05-08 14:17:08 +0200264
wdenk42d1f032003-10-15 23:53:47 +0000265 return 1;
266}
267
268
269/*
270 * Get timebase clock frequency
271 */
Kumar Gala66412c62011-02-18 05:40:54 -0600272#ifndef CONFIG_SYS_FSL_TBCLK_DIV
273#define CONFIG_SYS_FSL_TBCLK_DIV 8
274#endif
wdenk42d1f032003-10-15 23:53:47 +0000275unsigned long get_tbclk (void)
276{
Kumar Gala66412c62011-02-18 05:40:54 -0600277 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
278
279 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
wdenk42d1f032003-10-15 23:53:47 +0000280}
281
282
283#if defined(CONFIG_WATCHDOG)
284void
wdenk42d1f032003-10-15 23:53:47 +0000285reset_85xx_watchdog(void)
286{
287 /*
288 * Clear TSR(WIS) bit by writing 1
289 */
Mark Marshall320d53d2012-09-09 23:06:03 +0000290 mtspr(SPRN_TSR, TSR_WIS);
wdenk42d1f032003-10-15 23:53:47 +0000291}
Horst Kronstorferdf616ca2013-03-13 10:14:05 +0000292
293void
294watchdog_reset(void)
295{
296 int re_enable = disable_interrupts();
297
298 reset_85xx_watchdog();
299 if (re_enable)
300 enable_interrupts();
301}
wdenk42d1f032003-10-15 23:53:47 +0000302#endif /* CONFIG_WATCHDOG */
303
Sergei Poselenov740280e2008-06-06 15:42:40 +0200304/*
Andy Fleming80522dc2008-10-30 16:51:33 -0500305 * Initializes on-chip MMC controllers.
306 * to override, implement board_mmc_init()
307 */
308int cpu_mmc_init(bd_t *bis)
309{
310#ifdef CONFIG_FSL_ESDHC
311 return fsl_esdhc_mmc_init(bis);
312#else
313 return 0;
314#endif
315}
Becky Bruce199e2622010-06-17 11:37:25 -0500316
317/*
318 * Print out the state of various machine registers.
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530319 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
320 * parameters for IFC and TLBs
Becky Bruce199e2622010-06-17 11:37:25 -0500321 */
322void mpc85xx_reginfo(void)
323{
324 print_tlbcam();
325 print_laws();
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530326#if defined(CONFIG_FSL_LBC)
Becky Bruce199e2622010-06-17 11:37:25 -0500327 print_lbc_regs();
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530328#endif
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530329#ifdef CONFIG_FSL_IFC
330 print_ifc_regs();
331#endif
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530332
Becky Bruce199e2622010-06-17 11:37:25 -0500333}
York Sunebbe11d2010-09-28 15:20:33 -0700334
Becky Bruce38dba0c2010-12-17 17:17:56 -0600335/* Common ddr init for non-corenet fsl 85xx platforms */
336#ifndef CONFIG_FSL_CORENET
Scott Woodc97cd1b2012-09-20 19:02:18 -0500337#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
338 !defined(CONFIG_SYS_INIT_L2_ADDR)
Zhao Chenhuic1fc2d42011-01-28 17:58:37 +0800339phys_size_t initdram(int board_type)
340{
341#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
342 return fsl_ddr_sdram_size();
343#else
Mingkai Hu76d354f2013-04-12 15:56:28 +0800344 return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Zhao Chenhuic1fc2d42011-01-28 17:58:37 +0800345#endif
346}
347#else /* CONFIG_SYS_RAMBOOT */
Becky Bruce38dba0c2010-12-17 17:17:56 -0600348phys_size_t initdram(int board_type)
349{
350 phys_size_t dram_size = 0;
351
Becky Bruce810c4422010-12-17 17:17:58 -0600352#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
Becky Bruce38dba0c2010-12-17 17:17:56 -0600353 {
354 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
355 unsigned int x = 10;
356 unsigned int i;
357
358 /*
359 * Work around to stabilize DDR DLL
360 */
361 out_be32(&gur->ddrdllcr, 0x81000000);
362 asm("sync;isync;msync");
363 udelay(200);
364 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
365 setbits_be32(&gur->devdisr, 0x00010000);
366 for (i = 0; i < x; i++)
367 ;
368 clrbits_be32(&gur->devdisr, 0x00010000);
369 x++;
370 }
371 }
372#endif
373
York Sun1b3e3c42011-06-07 09:42:16 +0800374#if defined(CONFIG_SPD_EEPROM) || \
375 defined(CONFIG_DDR_SPD) || \
376 defined(CONFIG_SYS_DDR_RAW_TIMING)
Becky Bruce38dba0c2010-12-17 17:17:56 -0600377 dram_size = fsl_ddr_sdram();
378#else
379 dram_size = fixed_sdram();
380#endif
381 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
382 dram_size *= 0x100000;
383
384#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
385 /*
386 * Initialize and enable DDR ECC.
387 */
388 ddr_enable_ecc(dram_size);
389#endif
390
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530391#if defined(CONFIG_FSL_LBC)
Becky Bruce38dba0c2010-12-17 17:17:56 -0600392 /* Some boards also have sdram on the lbc */
Becky Bruce70961ba2010-12-17 17:17:57 -0600393 lbc_sdram_init();
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530394#endif
Becky Bruce38dba0c2010-12-17 17:17:56 -0600395
Wolfgang Denk21cd5812011-07-25 10:13:53 +0200396 debug("DDR: ");
Becky Bruce38dba0c2010-12-17 17:17:56 -0600397 return dram_size;
398}
Zhao Chenhuic1fc2d42011-01-28 17:58:37 +0800399#endif /* CONFIG_SYS_RAMBOOT */
Becky Bruce38dba0c2010-12-17 17:17:56 -0600400#endif
401
York Sunebbe11d2010-09-28 15:20:33 -0700402#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
403
404/* Board-specific functions defined in each board's ddr.c */
405void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
406 unsigned int ctrl_num);
407void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
408 phys_addr_t *rpn);
409unsigned int
410 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
411
Becky Bruce9cdfe282011-07-18 18:49:15 -0500412void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
413
York Sunebbe11d2010-09-28 15:20:33 -0700414static void dump_spd_ddr_reg(void)
415{
416 int i, j, k, m;
417 u8 *p_8;
418 u32 *p_32;
419 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
420 generic_spd_eeprom_t
421 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
422
423 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
424 fsl_ddr_get_spd(spd[i], i);
425
426 puts("SPD data of all dimms (zero vaule is omitted)...\n");
427 puts("Byte (hex) ");
428 k = 1;
429 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
430 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
431 printf("Dimm%d ", k++);
432 }
433 puts("\n");
434 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
435 m = 0;
436 printf("%3d (0x%02x) ", k, k);
437 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
438 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
439 p_8 = (u8 *) &spd[i][j];
440 if (p_8[k]) {
441 printf("0x%02x ", p_8[k]);
442 m++;
443 } else
444 puts(" ");
445 }
446 }
447 if (m)
448 puts("\n");
449 else
450 puts("\r");
451 }
452
453 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
454 switch (i) {
455 case 0:
York Sun5614e712013-09-30 09:22:09 -0700456 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
York Sunebbe11d2010-09-28 15:20:33 -0700457 break;
York Sun5614e712013-09-30 09:22:09 -0700458#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
York Sunebbe11d2010-09-28 15:20:33 -0700459 case 1:
York Sun5614e712013-09-30 09:22:09 -0700460 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
York Sunebbe11d2010-09-28 15:20:33 -0700461 break;
462#endif
York Sun5614e712013-09-30 09:22:09 -0700463#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
York Suna4c66502012-08-17 08:22:39 +0000464 case 2:
York Sun5614e712013-09-30 09:22:09 -0700465 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
York Suna4c66502012-08-17 08:22:39 +0000466 break;
467#endif
York Sun5614e712013-09-30 09:22:09 -0700468#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
York Suna4c66502012-08-17 08:22:39 +0000469 case 3:
York Sun5614e712013-09-30 09:22:09 -0700470 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
York Suna4c66502012-08-17 08:22:39 +0000471 break;
472#endif
York Sunebbe11d2010-09-28 15:20:33 -0700473 default:
474 printf("%s unexpected controller number = %u\n",
475 __func__, i);
476 return;
477 }
478 }
479 printf("DDR registers dump for all controllers "
480 "(zero vaule is omitted)...\n");
481 puts("Offset (hex) ");
482 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
483 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
484 puts("\n");
485 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
486 m = 0;
487 printf("%6d (0x%04x)", k * 4, k * 4);
488 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
489 p_32 = (u32 *) ddr[i];
490 if (p_32[k]) {
491 printf(" 0x%08x", p_32[k]);
492 m++;
493 } else
494 puts(" ");
495 }
496 if (m)
497 puts("\n");
498 else
499 puts("\r");
500 }
501 puts("\n");
502}
503
504/* invalid the TLBs for DDR and setup new ones to cover p_addr */
505static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
506{
507 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
508 unsigned long epn;
509 u32 tsize, valid, ptr;
York Sunebbe11d2010-09-28 15:20:33 -0700510 int ddr_esel;
511
Becky Bruce9cdfe282011-07-18 18:49:15 -0500512 clear_ddr_tlbs_phys(p_addr, size>>20);
York Sunebbe11d2010-09-28 15:20:33 -0700513
514 /* Setup new tlb to cover the physical address */
515 setup_ddr_tlbs_phys(p_addr, size>>20);
516
517 ptr = vstart;
518 ddr_esel = find_tlb_idx((void *)ptr, 1);
519 if (ddr_esel != -1) {
520 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
521 } else {
522 printf("TLB error in function %s\n", __func__);
523 return -1;
524 }
525
526 return 0;
527}
528
529/*
530 * slide the testing window up to test another area
531 * for 32_bit system, the maximum testable memory is limited to
532 * CONFIG_MAX_MEM_MAPPED
533 */
534int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
535{
536 phys_addr_t test_cap, p_addr;
537 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
538
539#if !defined(CONFIG_PHYS_64BIT) || \
540 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
541 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
542 test_cap = p_size;
543#else
544 test_cap = gd->ram_size;
545#endif
546 p_addr = (*vstart) + (*size) + (*phys_offset);
547 if (p_addr < test_cap - 1) {
548 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
549 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
550 return -1;
551 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
552 *size = (u32) p_size;
553 printf("Testing 0x%08llx - 0x%08llx\n",
554 (u64)(*vstart) + (*phys_offset),
555 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
556 } else
557 return 1;
558
559 return 0;
560}
561
562/* initialization for testing area */
563int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
564{
565 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
566
567 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
568 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
569 *phys_offset = 0;
570
571#if !defined(CONFIG_PHYS_64BIT) || \
572 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
573 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
574 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
575 puts("Cannot test more than ");
576 print_size(CONFIG_MAX_MEM_MAPPED,
577 " without proper 36BIT support.\n");
578 }
579#endif
580 printf("Testing 0x%08llx - 0x%08llx\n",
581 (u64)(*vstart) + (*phys_offset),
582 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
583
584 return 0;
585}
586
587/* invalid TLBs for DDR and remap as normal after testing */
588int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
589{
590 unsigned long epn;
591 u32 tsize, valid, ptr;
592 phys_addr_t rpn = 0;
593 int ddr_esel;
594
595 /* disable the TLBs for this testing */
596 ptr = *vstart;
597
598 while (ptr < (*vstart) + (*size)) {
599 ddr_esel = find_tlb_idx((void *)ptr, 1);
600 if (ddr_esel != -1) {
601 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
602 disable_tlb(ddr_esel);
603 }
604 ptr += TSIZE_TO_BYTES(tsize);
605 }
606
607 puts("Remap DDR ");
608 setup_ddr_tlbs(gd->ram_size>>20);
609 puts("\n");
610
611 return 0;
612}
613
614void arch_memory_failure_handle(void)
615{
616 dump_spd_ddr_reg();
617}
618#endif