wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 2 | * Copyright 2004,2007,2008 Freescale Semiconductor, Inc. |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 3 | * (C) Copyright 2002, 2003 Motorola Inc. |
| 4 | * Xianghua Xiao (X.Xiao@motorola.com) |
| 5 | * |
| 6 | * (C) Copyright 2000 |
| 7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 28 | #include <config.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 29 | #include <common.h> |
| 30 | #include <watchdog.h> |
| 31 | #include <command.h> |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 32 | #include <tsec.h> |
Ben Warren | 3456a14 | 2008-10-22 23:20:29 -0700 | [diff] [blame] | 33 | #include <netdev.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 34 | #include <asm/cache.h> |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 35 | #include <asm/io.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 36 | |
James Yang | 591933c | 2008-02-08 16:44:53 -0600 | [diff] [blame] | 37 | DECLARE_GLOBAL_DATA_PTR; |
| 38 | |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 39 | struct cpu_type cpu_type_list [] = { |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 40 | CPU_TYPE_ENTRY(8533, 8533), |
| 41 | CPU_TYPE_ENTRY(8533, 8533_E), |
Kumar Gala | ef50d6c | 2008-08-12 11:14:19 -0500 | [diff] [blame] | 42 | CPU_TYPE_ENTRY(8536, 8536), |
| 43 | CPU_TYPE_ENTRY(8536, 8536_E), |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 44 | CPU_TYPE_ENTRY(8540, 8540), |
| 45 | CPU_TYPE_ENTRY(8541, 8541), |
| 46 | CPU_TYPE_ENTRY(8541, 8541_E), |
| 47 | CPU_TYPE_ENTRY(8543, 8543), |
| 48 | CPU_TYPE_ENTRY(8543, 8543_E), |
| 49 | CPU_TYPE_ENTRY(8544, 8544), |
| 50 | CPU_TYPE_ENTRY(8544, 8544_E), |
| 51 | CPU_TYPE_ENTRY(8545, 8545), |
| 52 | CPU_TYPE_ENTRY(8545, 8545_E), |
| 53 | CPU_TYPE_ENTRY(8547, 8547_E), |
| 54 | CPU_TYPE_ENTRY(8548, 8548), |
| 55 | CPU_TYPE_ENTRY(8548, 8548_E), |
| 56 | CPU_TYPE_ENTRY(8555, 8555), |
| 57 | CPU_TYPE_ENTRY(8555, 8555_E), |
| 58 | CPU_TYPE_ENTRY(8560, 8560), |
| 59 | CPU_TYPE_ENTRY(8567, 8567), |
| 60 | CPU_TYPE_ENTRY(8567, 8567_E), |
| 61 | CPU_TYPE_ENTRY(8568, 8568), |
| 62 | CPU_TYPE_ENTRY(8568, 8568_E), |
| 63 | CPU_TYPE_ENTRY(8572, 8572), |
| 64 | CPU_TYPE_ENTRY(8572, 8572_E), |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 65 | }; |
| 66 | |
Anatolij Gustschin | 96026d4 | 2008-06-12 12:40:11 +0200 | [diff] [blame] | 67 | struct cpu_type *identify_cpu(u32 ver) |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 68 | { |
| 69 | int i; |
| 70 | for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) |
| 71 | if (cpu_type_list[i].soc_ver == ver) |
| 72 | return &cpu_type_list[i]; |
| 73 | |
| 74 | return NULL; |
| 75 | } |
| 76 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 77 | int checkcpu (void) |
| 78 | { |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 79 | sys_info_t sysinfo; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 80 | uint pvr, svr; |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 81 | uint fam; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 82 | uint ver; |
| 83 | uint major, minor; |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 84 | struct cpu_type *cpu; |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 85 | char buf1[32], buf2[32]; |
Kumar Gala | ee1e35b | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 86 | #ifdef CONFIG_DDR_CLK_FREQ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 87 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Jason Jin | c039111 | 2008-09-27 14:40:57 +0800 | [diff] [blame] | 88 | u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) |
| 89 | >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; |
Kumar Gala | ee1e35b | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 90 | #else |
| 91 | u32 ddr_ratio = 0; |
| 92 | #endif |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 93 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 94 | svr = get_svr(); |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 95 | ver = SVR_SOC_VER(svr); |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 96 | major = SVR_MAJ(svr); |
Kumar Gala | ef50d6c | 2008-08-12 11:14:19 -0500 | [diff] [blame] | 97 | #ifdef CONFIG_MPC8536 |
| 98 | major &= 0x7; /* the msb of this nibble is a mfg code */ |
| 99 | #endif |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 100 | minor = SVR_MIN(svr); |
| 101 | |
Ed Swarthout | 6856b3d | 2008-10-08 23:37:59 -0500 | [diff] [blame] | 102 | #if (CONFIG_NUM_CPUS > 1) |
| 103 | volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); |
| 104 | printf("CPU%d: ", pic->whoami); |
| 105 | #else |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 106 | puts("CPU: "); |
Ed Swarthout | 6856b3d | 2008-10-08 23:37:59 -0500 | [diff] [blame] | 107 | #endif |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 108 | |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 109 | cpu = identify_cpu(ver); |
| 110 | if (cpu) { |
| 111 | puts(cpu->name); |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 112 | |
Kim Phillips | 06b4186 | 2008-06-17 17:45:22 -0500 | [diff] [blame] | 113 | if (IS_E_PROCESSOR(svr)) |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 114 | puts("E"); |
| 115 | } else { |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 116 | puts("Unknown"); |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 117 | } |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 118 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 119 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 120 | |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 121 | pvr = get_pvr(); |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 122 | fam = PVR_FAM(pvr); |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 123 | ver = PVR_VER(pvr); |
| 124 | major = PVR_MAJ(pvr); |
| 125 | minor = PVR_MIN(pvr); |
| 126 | |
| 127 | printf("Core: "); |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 128 | switch (fam) { |
| 129 | case PVR_FAM(PVR_85xx): |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 130 | puts("E500"); |
| 131 | break; |
| 132 | default: |
| 133 | puts("Unknown"); |
| 134 | break; |
| 135 | } |
Kumar Gala | 0f060c3 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 136 | |
| 137 | if (PVR_MEM(pvr) == 0x03) |
| 138 | puts("MC"); |
| 139 | |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 140 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); |
| 141 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 142 | get_sys_info(&sysinfo); |
| 143 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 144 | puts("Clock Configuration:\n"); |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 145 | printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); |
| 146 | printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); |
Kumar Gala | ee1e35b | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 147 | |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 148 | switch (ddr_ratio) { |
| 149 | case 0x0: |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 150 | printf(" DDR:%-4s MHz (%s MT/s data rate), ", |
| 151 | strmhz(buf1, sysinfo.freqDDRBus/2), |
| 152 | strmhz(buf2, sysinfo.freqDDRBus)); |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 153 | break; |
| 154 | case 0x7: |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 155 | printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", |
| 156 | strmhz(buf1, sysinfo.freqDDRBus/2), |
| 157 | strmhz(buf2, sysinfo.freqDDRBus)); |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 158 | break; |
| 159 | default: |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 160 | printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", |
| 161 | strmhz(buf1, sysinfo.freqDDRBus/2), |
| 162 | strmhz(buf2, sysinfo.freqDDRBus)); |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 163 | break; |
| 164 | } |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 165 | |
Trent Piepho | ada591d | 2008-12-03 15:16:37 -0800 | [diff] [blame^] | 166 | if (sysinfo.freqLocalBus > LCRR_CLKDIV) |
| 167 | printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); |
| 168 | else |
| 169 | printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", |
| 170 | sysinfo.freqLocalBus); |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 171 | |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 172 | #ifdef CONFIG_CPM2 |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 173 | printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 174 | #endif |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 175 | |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 176 | puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 177 | |
| 178 | return 0; |
| 179 | } |
| 180 | |
| 181 | |
| 182 | /* ------------------------------------------------------------------------- */ |
| 183 | |
| 184 | int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) |
| 185 | { |
Zang Roy-r61911 | 96629cb | 2006-12-05 16:42:30 +0800 | [diff] [blame] | 186 | uint pvr; |
| 187 | uint ver; |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 188 | unsigned long val, msr; |
| 189 | |
Zang Roy-r61911 | 96629cb | 2006-12-05 16:42:30 +0800 | [diff] [blame] | 190 | pvr = get_pvr(); |
| 191 | ver = PVR_VER(pvr); |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 192 | |
Zang Roy-r61911 | 96629cb | 2006-12-05 16:42:30 +0800 | [diff] [blame] | 193 | if (ver & 1){ |
| 194 | /* e500 v2 core has reset control register */ |
| 195 | volatile unsigned int * rstcr; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 196 | rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0); |
Wolfgang Denk | 2f15278 | 2007-05-05 18:23:11 +0200 | [diff] [blame] | 197 | *rstcr = 0x2; /* HRESET_REQ */ |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 198 | udelay(100); |
| 199 | } |
| 200 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 201 | /* |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 202 | * Fallthrough if the code above failed |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 203 | * Initiate hard reset in debug control register DBCR0 |
| 204 | * Make sure MSR[DE] = 1 |
| 205 | */ |
urwithsughosh@gmail.com | df90968 | 2007-09-24 13:32:13 -0400 | [diff] [blame] | 206 | |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 207 | msr = mfmsr (); |
| 208 | msr |= MSR_DE; |
| 209 | mtmsr (msr); |
urwithsughosh@gmail.com | df90968 | 2007-09-24 13:32:13 -0400 | [diff] [blame] | 210 | |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 211 | val = mfspr(DBCR0); |
| 212 | val |= 0x70000000; |
| 213 | mtspr(DBCR0,val); |
| 214 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 215 | return 1; |
| 216 | } |
| 217 | |
| 218 | |
| 219 | /* |
| 220 | * Get timebase clock frequency |
| 221 | */ |
| 222 | unsigned long get_tbclk (void) |
| 223 | { |
James Yang | 591933c | 2008-02-08 16:44:53 -0600 | [diff] [blame] | 224 | return (gd->bus_clk + 4UL)/8UL; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | |
| 228 | #if defined(CONFIG_WATCHDOG) |
| 229 | void |
| 230 | watchdog_reset(void) |
| 231 | { |
| 232 | int re_enable = disable_interrupts(); |
| 233 | reset_85xx_watchdog(); |
| 234 | if (re_enable) enable_interrupts(); |
| 235 | } |
| 236 | |
| 237 | void |
| 238 | reset_85xx_watchdog(void) |
| 239 | { |
| 240 | /* |
| 241 | * Clear TSR(WIS) bit by writing 1 |
| 242 | */ |
| 243 | unsigned long val; |
Andy Fleming | 03b81b4 | 2007-04-23 01:44:44 -0500 | [diff] [blame] | 244 | val = mfspr(SPRN_TSR); |
| 245 | val |= TSR_WIS; |
| 246 | mtspr(SPRN_TSR, val); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 247 | } |
| 248 | #endif /* CONFIG_WATCHDOG */ |
| 249 | |
| 250 | #if defined(CONFIG_DDR_ECC) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 251 | void dma_init(void) { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 252 | volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 253 | |
| 254 | dma->satr0 = 0x02c40000; |
| 255 | dma->datr0 = 0x02c40000; |
Andy Fleming | 03b81b4 | 2007-04-23 01:44:44 -0500 | [diff] [blame] | 256 | dma->sr0 = 0xfffffff; /* clear any errors */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 257 | asm("sync; isync; msync"); |
| 258 | return; |
| 259 | } |
| 260 | |
| 261 | uint dma_check(void) { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 262 | volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 263 | volatile uint status = dma->sr0; |
| 264 | |
| 265 | /* While the channel is busy, spin */ |
| 266 | while((status & 4) == 4) { |
| 267 | status = dma->sr0; |
| 268 | } |
| 269 | |
Andy Fleming | 03b81b4 | 2007-04-23 01:44:44 -0500 | [diff] [blame] | 270 | /* clear MR0[CS] channel start bit */ |
| 271 | dma->mr0 &= 0x00000001; |
| 272 | asm("sync;isync;msync"); |
| 273 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 274 | if (status != 0) { |
| 275 | printf ("DMA Error: status = %x\n", status); |
| 276 | } |
| 277 | return status; |
| 278 | } |
| 279 | |
| 280 | int dma_xfer(void *dest, uint count, void *src) { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 281 | volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 282 | |
| 283 | dma->dar0 = (uint) dest; |
| 284 | dma->sar0 = (uint) src; |
| 285 | dma->bcr0 = count; |
| 286 | dma->mr0 = 0xf000004; |
| 287 | asm("sync;isync;msync"); |
| 288 | dma->mr0 = 0xf000005; |
| 289 | asm("sync;isync;msync"); |
| 290 | return dma_check(); |
| 291 | } |
| 292 | #endif |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 293 | |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 294 | /* |
Sergei Poselenov | 59f6305 | 2008-08-15 15:42:11 +0200 | [diff] [blame] | 295 | * Configures a UPM. The function requires the respective MxMR to be set |
| 296 | * before calling this function. "size" is the number or entries, not a sizeof. |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 297 | */ |
| 298 | void upmconfig (uint upm, uint * table, uint size) |
| 299 | { |
| 300 | int i, mdr, mad, old_mad = 0; |
| 301 | volatile u32 *mxmr; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 302 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 303 | volatile u32 *brp,*orp; |
| 304 | volatile u8* dummy = NULL; |
| 305 | int upmmask; |
| 306 | |
| 307 | switch (upm) { |
| 308 | case UPMA: |
| 309 | mxmr = &lbc->mamr; |
| 310 | upmmask = BR_MS_UPMA; |
| 311 | break; |
| 312 | case UPMB: |
| 313 | mxmr = &lbc->mbmr; |
| 314 | upmmask = BR_MS_UPMB; |
| 315 | break; |
| 316 | case UPMC: |
| 317 | mxmr = &lbc->mcmr; |
| 318 | upmmask = BR_MS_UPMC; |
| 319 | break; |
| 320 | default: |
| 321 | printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); |
| 322 | hang(); |
| 323 | } |
| 324 | |
| 325 | /* Find the address for the dummy write transaction */ |
| 326 | for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; |
| 327 | i++, brp += 2, orp += 2) { |
Wolfgang Denk | e093a24 | 2008-06-28 23:34:37 +0200 | [diff] [blame] | 328 | |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 329 | /* Look for a valid BR with selected UPM */ |
Sergei Poselenov | 59f6305 | 2008-08-15 15:42:11 +0200 | [diff] [blame] | 330 | if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { |
| 331 | dummy = (volatile u8*)(in_be32(brp) & BR_BA); |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 332 | break; |
| 333 | } |
| 334 | } |
| 335 | |
| 336 | if (i == 8) { |
| 337 | printf("Error: %s() could not find matching BR\n", __FUNCTION__); |
| 338 | hang(); |
| 339 | } |
| 340 | |
| 341 | for (i = 0; i < size; i++) { |
| 342 | /* 1 */ |
Sergei Poselenov | 59f6305 | 2008-08-15 15:42:11 +0200 | [diff] [blame] | 343 | out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 344 | /* 2 */ |
| 345 | out_be32(&lbc->mdr, table[i]); |
| 346 | /* 3 */ |
| 347 | mdr = in_be32(&lbc->mdr); |
| 348 | /* 4 */ |
| 349 | *(volatile u8 *)dummy = 0; |
| 350 | /* 5 */ |
| 351 | do { |
Sergei Poselenov | 59f6305 | 2008-08-15 15:42:11 +0200 | [diff] [blame] | 352 | mad = in_be32(mxmr) & MxMR_MAD_MSK; |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 353 | } while (mad <= old_mad && !(!mad && i == (size-1))); |
| 354 | old_mad = mad; |
| 355 | } |
Sergei Poselenov | 59f6305 | 2008-08-15 15:42:11 +0200 | [diff] [blame] | 356 | out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 357 | } |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 358 | |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 359 | |
| 360 | /* |
| 361 | * Initializes on-chip ethernet controllers. |
| 362 | * to override, implement board_eth_init() |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 363 | */ |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 364 | int cpu_eth_init(bd_t *bis) |
| 365 | { |
Ben Warren | 3456a14 | 2008-10-22 23:20:29 -0700 | [diff] [blame] | 366 | #if defined(CONFIG_ETHER_ON_FCC) |
| 367 | fec_initialize(bis); |
| 368 | #endif |
Ben Warren | 0e8454e | 2008-10-22 23:32:48 -0700 | [diff] [blame] | 369 | #if defined(CONFIG_UEC_ETH1) |
| 370 | uec_initialize(0); |
| 371 | #endif |
| 372 | #if defined(CONFIG_UEC_ETH2) |
| 373 | uec_initialize(1); |
| 374 | #endif |
| 375 | #if defined(CONFIG_UEC_ETH3) |
| 376 | uec_initialize(2); |
| 377 | #endif |
| 378 | #if defined(CONFIG_UEC_ETH4) |
| 379 | uec_initialize(3); |
| 380 | #endif |
| 381 | #if defined(CONFIG_UEC_ETH5) |
| 382 | uec_initialize(4); |
| 383 | #endif |
| 384 | #if defined(CONFIG_UEC_ETH6) |
| 385 | uec_initialize(5); |
| 386 | #endif |
Ben Warren | 62e15b4 | 2008-10-30 22:15:35 -0700 | [diff] [blame] | 387 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 388 | tsec_standard_init(bis); |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 389 | #endif |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 390 | return 0; |
| 391 | } |