blob: 15ba7f1c5ed25992ae82588bed3ffa282f8449bb [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
Andy Fleming1ced1212008-02-06 01:19:40 -06002 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Andy Fleming75b9d4a2008-08-31 16:33:26 -050028#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000029#include <common.h>
30#include <watchdog.h>
31#include <command.h>
Andy Fleming75b9d4a2008-08-31 16:33:26 -050032#include <tsec.h>
Ben Warren3456a142008-10-22 23:20:29 -070033#include <netdev.h>
wdenk42d1f032003-10-15 23:53:47 +000034#include <asm/cache.h>
Sergei Poselenov740280e2008-06-06 15:42:40 +020035#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000036
James Yang591933c2008-02-08 16:44:53 -060037DECLARE_GLOBAL_DATA_PTR;
38
Andy Fleming1ced1212008-02-06 01:19:40 -060039struct cpu_type cpu_type_list [] = {
Kumar Gala4dbdb762008-06-10 16:53:46 -050040 CPU_TYPE_ENTRY(8533, 8533),
41 CPU_TYPE_ENTRY(8533, 8533_E),
Kumar Galaef50d6c2008-08-12 11:14:19 -050042 CPU_TYPE_ENTRY(8536, 8536),
43 CPU_TYPE_ENTRY(8536, 8536_E),
Kumar Gala4dbdb762008-06-10 16:53:46 -050044 CPU_TYPE_ENTRY(8540, 8540),
45 CPU_TYPE_ENTRY(8541, 8541),
46 CPU_TYPE_ENTRY(8541, 8541_E),
47 CPU_TYPE_ENTRY(8543, 8543),
48 CPU_TYPE_ENTRY(8543, 8543_E),
49 CPU_TYPE_ENTRY(8544, 8544),
50 CPU_TYPE_ENTRY(8544, 8544_E),
51 CPU_TYPE_ENTRY(8545, 8545),
52 CPU_TYPE_ENTRY(8545, 8545_E),
53 CPU_TYPE_ENTRY(8547, 8547_E),
54 CPU_TYPE_ENTRY(8548, 8548),
55 CPU_TYPE_ENTRY(8548, 8548_E),
56 CPU_TYPE_ENTRY(8555, 8555),
57 CPU_TYPE_ENTRY(8555, 8555_E),
58 CPU_TYPE_ENTRY(8560, 8560),
59 CPU_TYPE_ENTRY(8567, 8567),
60 CPU_TYPE_ENTRY(8567, 8567_E),
61 CPU_TYPE_ENTRY(8568, 8568),
62 CPU_TYPE_ENTRY(8568, 8568_E),
63 CPU_TYPE_ENTRY(8572, 8572),
64 CPU_TYPE_ENTRY(8572, 8572_E),
Andy Fleming1ced1212008-02-06 01:19:40 -060065};
66
Anatolij Gustschin96026d42008-06-12 12:40:11 +020067struct cpu_type *identify_cpu(u32 ver)
Kumar Gala4dbdb762008-06-10 16:53:46 -050068{
69 int i;
70 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
71 if (cpu_type_list[i].soc_ver == ver)
72 return &cpu_type_list[i];
73
74 return NULL;
75}
76
wdenk42d1f032003-10-15 23:53:47 +000077int checkcpu (void)
78{
wdenk97d80fc2004-06-09 00:34:46 +000079 sys_info_t sysinfo;
wdenk97d80fc2004-06-09 00:34:46 +000080 uint pvr, svr;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050081 uint fam;
wdenk97d80fc2004-06-09 00:34:46 +000082 uint ver;
83 uint major, minor;
Kumar Gala4dbdb762008-06-10 16:53:46 -050084 struct cpu_type *cpu;
Wolfgang Denk08ef89e2008-10-19 02:35:49 +020085 char buf1[32], buf2[32];
Kumar Galaee1e35b2008-05-29 01:21:24 -050086#ifdef CONFIG_DDR_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Jason Jinc0391112008-09-27 14:40:57 +080088 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
89 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
Kumar Galaee1e35b2008-05-29 01:21:24 -050090#else
91 u32 ddr_ratio = 0;
92#endif
wdenk42d1f032003-10-15 23:53:47 +000093
wdenk97d80fc2004-06-09 00:34:46 +000094 svr = get_svr();
Andy Fleming1ced1212008-02-06 01:19:40 -060095 ver = SVR_SOC_VER(svr);
wdenk97d80fc2004-06-09 00:34:46 +000096 major = SVR_MAJ(svr);
Kumar Galaef50d6c2008-08-12 11:14:19 -050097#ifdef CONFIG_MPC8536
98 major &= 0x7; /* the msb of this nibble is a mfg code */
99#endif
wdenk97d80fc2004-06-09 00:34:46 +0000100 minor = SVR_MIN(svr);
101
Ed Swarthout6856b3d2008-10-08 23:37:59 -0500102#if (CONFIG_NUM_CPUS > 1)
103 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
104 printf("CPU%d: ", pic->whoami);
105#else
wdenk6c9e7892005-03-15 22:56:53 +0000106 puts("CPU: ");
Ed Swarthout6856b3d2008-10-08 23:37:59 -0500107#endif
Andy Fleming1ced1212008-02-06 01:19:40 -0600108
Kumar Gala4dbdb762008-06-10 16:53:46 -0500109 cpu = identify_cpu(ver);
110 if (cpu) {
111 puts(cpu->name);
Andy Fleming1ced1212008-02-06 01:19:40 -0600112
Kim Phillips06b41862008-06-17 17:45:22 -0500113 if (IS_E_PROCESSOR(svr))
Kumar Gala4dbdb762008-06-10 16:53:46 -0500114 puts("E");
115 } else {
wdenk97d80fc2004-06-09 00:34:46 +0000116 puts("Unknown");
Kumar Gala4dbdb762008-06-10 16:53:46 -0500117 }
Andy Fleming1ced1212008-02-06 01:19:40 -0600118
wdenk97d80fc2004-06-09 00:34:46 +0000119 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk42d1f032003-10-15 23:53:47 +0000120
wdenk6c9e7892005-03-15 22:56:53 +0000121 pvr = get_pvr();
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500122 fam = PVR_FAM(pvr);
wdenk6c9e7892005-03-15 22:56:53 +0000123 ver = PVR_VER(pvr);
124 major = PVR_MAJ(pvr);
125 minor = PVR_MIN(pvr);
126
127 printf("Core: ");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500128 switch (fam) {
129 case PVR_FAM(PVR_85xx):
wdenk6c9e7892005-03-15 22:56:53 +0000130 puts("E500");
131 break;
132 default:
133 puts("Unknown");
134 break;
135 }
Kumar Gala0f060c32008-10-23 01:47:38 -0500136
137 if (PVR_MEM(pvr) == 0x03)
138 puts("MC");
139
wdenk6c9e7892005-03-15 22:56:53 +0000140 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
141
wdenk97d80fc2004-06-09 00:34:46 +0000142 get_sys_info(&sysinfo);
143
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500144 puts("Clock Configuration:\n");
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200145 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
146 printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
Kumar Galaee1e35b2008-05-29 01:21:24 -0500147
Kumar Galad4357932007-12-07 04:59:26 -0600148 switch (ddr_ratio) {
149 case 0x0:
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200150 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
151 strmhz(buf1, sysinfo.freqDDRBus/2),
152 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600153 break;
154 case 0x7:
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200155 printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
156 strmhz(buf1, sysinfo.freqDDRBus/2),
157 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600158 break;
159 default:
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200160 printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
161 strmhz(buf1, sysinfo.freqDDRBus/2),
162 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600163 break;
164 }
wdenk97d80fc2004-06-09 00:34:46 +0000165
Trent Piephoada591d2008-12-03 15:16:37 -0800166 if (sysinfo.freqLocalBus > LCRR_CLKDIV)
167 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
168 else
169 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
170 sysinfo.freqLocalBus);
wdenk97d80fc2004-06-09 00:34:46 +0000171
Andy Fleming1ced1212008-02-06 01:19:40 -0600172#ifdef CONFIG_CPM2
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200173 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
Andy Fleming1ced1212008-02-06 01:19:40 -0600174#endif
wdenk97d80fc2004-06-09 00:34:46 +0000175
wdenk6c9e7892005-03-15 22:56:53 +0000176 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000177
178 return 0;
179}
180
181
182/* ------------------------------------------------------------------------- */
183
184int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
185{
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800186 uint pvr;
187 uint ver;
Sergei Poselenov793670c2008-05-08 14:17:08 +0200188 unsigned long val, msr;
189
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800190 pvr = get_pvr();
191 ver = PVR_VER(pvr);
Sergei Poselenov793670c2008-05-08 14:17:08 +0200192
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800193 if (ver & 1){
194 /* e500 v2 core has reset control register */
195 volatile unsigned int * rstcr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
Wolfgang Denk2f152782007-05-05 18:23:11 +0200197 *rstcr = 0x2; /* HRESET_REQ */
Sergei Poselenov793670c2008-05-08 14:17:08 +0200198 udelay(100);
199 }
200
wdenk42d1f032003-10-15 23:53:47 +0000201 /*
Sergei Poselenov793670c2008-05-08 14:17:08 +0200202 * Fallthrough if the code above failed
wdenk42d1f032003-10-15 23:53:47 +0000203 * Initiate hard reset in debug control register DBCR0
204 * Make sure MSR[DE] = 1
205 */
urwithsughosh@gmail.comdf909682007-09-24 13:32:13 -0400206
Sergei Poselenov793670c2008-05-08 14:17:08 +0200207 msr = mfmsr ();
208 msr |= MSR_DE;
209 mtmsr (msr);
urwithsughosh@gmail.comdf909682007-09-24 13:32:13 -0400210
Sergei Poselenov793670c2008-05-08 14:17:08 +0200211 val = mfspr(DBCR0);
212 val |= 0x70000000;
213 mtspr(DBCR0,val);
214
wdenk42d1f032003-10-15 23:53:47 +0000215 return 1;
216}
217
218
219/*
220 * Get timebase clock frequency
221 */
222unsigned long get_tbclk (void)
223{
James Yang591933c2008-02-08 16:44:53 -0600224 return (gd->bus_clk + 4UL)/8UL;
wdenk42d1f032003-10-15 23:53:47 +0000225}
226
227
228#if defined(CONFIG_WATCHDOG)
229void
230watchdog_reset(void)
231{
232 int re_enable = disable_interrupts();
233 reset_85xx_watchdog();
234 if (re_enable) enable_interrupts();
235}
236
237void
238reset_85xx_watchdog(void)
239{
240 /*
241 * Clear TSR(WIS) bit by writing 1
242 */
243 unsigned long val;
Andy Fleming03b81b42007-04-23 01:44:44 -0500244 val = mfspr(SPRN_TSR);
245 val |= TSR_WIS;
246 mtspr(SPRN_TSR, val);
wdenk42d1f032003-10-15 23:53:47 +0000247}
248#endif /* CONFIG_WATCHDOG */
249
250#if defined(CONFIG_DDR_ECC)
wdenk42d1f032003-10-15 23:53:47 +0000251void dma_init(void) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000253
254 dma->satr0 = 0x02c40000;
255 dma->datr0 = 0x02c40000;
Andy Fleming03b81b42007-04-23 01:44:44 -0500256 dma->sr0 = 0xfffffff; /* clear any errors */
wdenk42d1f032003-10-15 23:53:47 +0000257 asm("sync; isync; msync");
258 return;
259}
260
261uint dma_check(void) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000263 volatile uint status = dma->sr0;
264
265 /* While the channel is busy, spin */
266 while((status & 4) == 4) {
267 status = dma->sr0;
268 }
269
Andy Fleming03b81b42007-04-23 01:44:44 -0500270 /* clear MR0[CS] channel start bit */
271 dma->mr0 &= 0x00000001;
272 asm("sync;isync;msync");
273
wdenk42d1f032003-10-15 23:53:47 +0000274 if (status != 0) {
275 printf ("DMA Error: status = %x\n", status);
276 }
277 return status;
278}
279
280int dma_xfer(void *dest, uint count, void *src) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000282
283 dma->dar0 = (uint) dest;
284 dma->sar0 = (uint) src;
285 dma->bcr0 = count;
286 dma->mr0 = 0xf000004;
287 asm("sync;isync;msync");
288 dma->mr0 = 0xf000005;
289 asm("sync;isync;msync");
290 return dma_check();
291}
292#endif
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500293
Sergei Poselenov740280e2008-06-06 15:42:40 +0200294/*
Sergei Poselenov59f63052008-08-15 15:42:11 +0200295 * Configures a UPM. The function requires the respective MxMR to be set
296 * before calling this function. "size" is the number or entries, not a sizeof.
Sergei Poselenov740280e2008-06-06 15:42:40 +0200297 */
298void upmconfig (uint upm, uint * table, uint size)
299{
300 int i, mdr, mad, old_mad = 0;
301 volatile u32 *mxmr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200303 volatile u32 *brp,*orp;
304 volatile u8* dummy = NULL;
305 int upmmask;
306
307 switch (upm) {
308 case UPMA:
309 mxmr = &lbc->mamr;
310 upmmask = BR_MS_UPMA;
311 break;
312 case UPMB:
313 mxmr = &lbc->mbmr;
314 upmmask = BR_MS_UPMB;
315 break;
316 case UPMC:
317 mxmr = &lbc->mcmr;
318 upmmask = BR_MS_UPMC;
319 break;
320 default:
321 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
322 hang();
323 }
324
325 /* Find the address for the dummy write transaction */
326 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
327 i++, brp += 2, orp += 2) {
Wolfgang Denke093a242008-06-28 23:34:37 +0200328
Sergei Poselenov740280e2008-06-06 15:42:40 +0200329 /* Look for a valid BR with selected UPM */
Sergei Poselenov59f63052008-08-15 15:42:11 +0200330 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
331 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200332 break;
333 }
334 }
335
336 if (i == 8) {
337 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
338 hang();
339 }
340
341 for (i = 0; i < size; i++) {
342 /* 1 */
Sergei Poselenov59f63052008-08-15 15:42:11 +0200343 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200344 /* 2 */
345 out_be32(&lbc->mdr, table[i]);
346 /* 3 */
347 mdr = in_be32(&lbc->mdr);
348 /* 4 */
349 *(volatile u8 *)dummy = 0;
350 /* 5 */
351 do {
Sergei Poselenov59f63052008-08-15 15:42:11 +0200352 mad = in_be32(mxmr) & MxMR_MAD_MSK;
Sergei Poselenov740280e2008-06-06 15:42:40 +0200353 } while (mad <= old_mad && !(!mad && i == (size-1)));
354 old_mad = mad;
355 }
Sergei Poselenov59f63052008-08-15 15:42:11 +0200356 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
Sergei Poselenov740280e2008-06-06 15:42:40 +0200357}
Ben Warrendd354792008-06-23 22:57:27 -0700358
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500359
360/*
361 * Initializes on-chip ethernet controllers.
362 * to override, implement board_eth_init()
Ben Warrendd354792008-06-23 22:57:27 -0700363 */
Ben Warrendd354792008-06-23 22:57:27 -0700364int cpu_eth_init(bd_t *bis)
365{
Ben Warren3456a142008-10-22 23:20:29 -0700366#if defined(CONFIG_ETHER_ON_FCC)
367 fec_initialize(bis);
368#endif
Ben Warren0e8454e2008-10-22 23:32:48 -0700369#if defined(CONFIG_UEC_ETH1)
370 uec_initialize(0);
371#endif
372#if defined(CONFIG_UEC_ETH2)
373 uec_initialize(1);
374#endif
375#if defined(CONFIG_UEC_ETH3)
376 uec_initialize(2);
377#endif
378#if defined(CONFIG_UEC_ETH4)
379 uec_initialize(3);
380#endif
381#if defined(CONFIG_UEC_ETH5)
382 uec_initialize(4);
383#endif
384#if defined(CONFIG_UEC_ETH6)
385 uec_initialize(5);
386#endif
Ben Warren62e15b42008-10-30 22:15:35 -0700387#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500388 tsec_standard_init(bis);
Ben Warrendd354792008-06-23 22:57:27 -0700389#endif
Ben Warrendd354792008-06-23 22:57:27 -0700390 return 0;
391}