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Kumar Galaec2b74f2008-01-17 16:48:33 -06001/*
Ed Swarthoute81241a2011-03-03 18:28:14 -06002 * Copyright 2008-2011 Freescale Semiconductor, Inc.
Kumar Galaec2b74f2008-01-17 16:48:33 -06003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Galaec2b74f2008-01-17 16:48:33 -06005 */
6
7#include <common.h>
8#include <asm/processor.h>
9#include <ioports.h>
Kumar Galadd6c9102008-03-26 08:53:53 -050010#include <lmb.h>
Kumar Galaec2b74f2008-01-17 16:48:33 -060011#include <asm/io.h>
Kumar Galac7259082009-09-03 08:41:31 -050012#include <asm/mmu.h>
Kumar Gala39a7e7f2009-09-17 01:44:39 -050013#include <asm/fsl_law.h>
York Sun5614e712013-09-30 09:22:09 -070014#include <fsl_ddr_sdram.h>
Kumar Galaec2b74f2008-01-17 16:48:33 -060015#include "mp.h"
16
17DECLARE_GLOBAL_DATA_PTR;
York Suneb539412012-10-08 07:44:25 +000018u32 fsl_ddr_get_intl3r(void);
Kumar Galaec2b74f2008-01-17 16:48:33 -060019
York Sunffd06e02012-10-08 07:44:30 +000020extern u32 __spin_table[];
21
Kumar Galaec2b74f2008-01-17 16:48:33 -060022u32 get_my_id()
23{
24 return mfspr(SPRN_PIR);
25}
26
Aaron Sierra9d64c6b2010-09-30 12:22:16 -050027/*
28 * Determine if U-Boot should keep secondary cores in reset, or let them out
29 * of reset and hold them in a spinloop
30 */
31int hold_cores_in_reset(int verbose)
32{
Aaron Sierra9d64c6b2010-09-30 12:22:16 -050033 /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
Joe Hershbergerec8a2522012-12-11 22:16:22 -060034 if (getenv_yesno("mp_holdoff") == 1) {
Aaron Sierra9d64c6b2010-09-30 12:22:16 -050035 if (verbose) {
36 puts("Secondary cores are being held in reset.\n");
37 puts("See 'mp_holdoff' environment variable\n");
38 }
39
40 return 1;
41 }
42
43 return 0;
44}
45
Kumar Galaec2b74f2008-01-17 16:48:33 -060046int cpu_reset(int nr)
47{
Kim Phillips680c6132010-08-09 18:39:57 -050048 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Kumar Galaec2b74f2008-01-17 16:48:33 -060049 out_be32(&pic->pir, 1 << nr);
Kumar Galac840d262009-03-31 23:11:05 -050050 /* the dummy read works around an errata on early 85xx MP PICs */
Kumar Galaec2b74f2008-01-17 16:48:33 -060051 (void)in_be32(&pic->pir);
52 out_be32(&pic->pir, 0x0);
53
54 return 0;
55}
56
57int cpu_status(int nr)
58{
59 u32 *table, id = get_my_id();
60
Aaron Sierra9d64c6b2010-09-30 12:22:16 -050061 if (hold_cores_in_reset(1))
62 return 0;
63
Kumar Galaec2b74f2008-01-17 16:48:33 -060064 if (nr == id) {
York Sunffd06e02012-10-08 07:44:30 +000065 table = (u32 *)&__spin_table;
Kumar Gala348753d2008-07-14 14:03:02 -050066 printf("table base @ 0x%p\n", table);
York Sun0c9ab432013-03-25 07:40:00 +000067 } else if (is_core_disabled(nr)) {
68 puts("Disabled\n");
Kumar Galaec2b74f2008-01-17 16:48:33 -060069 } else {
York Sunffd06e02012-10-08 07:44:30 +000070 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
Kumar Galaec2b74f2008-01-17 16:48:33 -060071 printf("Running on cpu %d\n", id);
72 printf("\n");
Kumar Gala348753d2008-07-14 14:03:02 -050073 printf("table @ 0x%p\n", table);
Kumar Gala79679d82008-03-26 08:34:25 -050074 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
Kumar Gala79679d82008-03-26 08:34:25 -050075 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
York Sun3f0997b2012-10-08 07:44:29 +000076 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
Kumar Galaec2b74f2008-01-17 16:48:33 -060077 }
78
79 return 0;
80}
81
Kumar Galaa9c3ac72010-01-12 12:56:05 -060082#ifdef CONFIG_FSL_CORENET
Kumar Gala4194b362010-01-12 11:42:43 -060083int cpu_disable(int nr)
84{
Kumar Galaa9c3ac72010-01-12 12:56:05 -060085 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
86
87 setbits_be32(&gur->coredisrl, 1 << nr);
88
89 return 0;
Kumar Gala4194b362010-01-12 11:42:43 -060090}
Kumar Gala8f3a7fa2010-06-09 22:33:53 -050091
92int is_core_disabled(int nr) {
93 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
94 u32 coredisrl = in_be32(&gur->coredisrl);
95
96 return (coredisrl & (1 << nr));
97}
Kumar Galaa9c3ac72010-01-12 12:56:05 -060098#else
99int cpu_disable(int nr)
100{
101 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
102
103 switch (nr) {
104 case 0:
105 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
106 break;
107 case 1:
108 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
109 break;
110 default:
111 printf("Invalid cpu number for disable %d\n", nr);
112 return 1;
113 }
114
115 return 0;
116}
Kumar Gala8f3a7fa2010-06-09 22:33:53 -0500117
118int is_core_disabled(int nr) {
119 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
120 u32 devdisr = in_be32(&gur->devdisr);
121
122 switch (nr) {
123 case 0:
124 return (devdisr & MPC85xx_DEVDISR_CPU0);
125 case 1:
126 return (devdisr & MPC85xx_DEVDISR_CPU1);
127 default:
128 printf("Invalid cpu number for disable %d\n", nr);
129 }
130
131 return 0;
132}
Kumar Galaa9c3ac72010-01-12 12:56:05 -0600133#endif
Kumar Gala4194b362010-01-12 11:42:43 -0600134
Kumar Gala79679d82008-03-26 08:34:25 -0500135static u8 boot_entry_map[4] = {
136 0,
137 BOOT_ENTRY_PIR,
138 BOOT_ENTRY_R3_LOWER,
Kumar Gala79679d82008-03-26 08:34:25 -0500139};
140
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200141int cpu_release(int nr, int argc, char * const argv[])
Kumar Galaec2b74f2008-01-17 16:48:33 -0600142{
York Sunffd06e02012-10-08 07:44:30 +0000143 u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
Kumar Gala79679d82008-03-26 08:34:25 -0500144 u64 boot_addr;
Kumar Galaec2b74f2008-01-17 16:48:33 -0600145
Aaron Sierra9d64c6b2010-09-30 12:22:16 -0500146 if (hold_cores_in_reset(1))
147 return 0;
148
Kumar Galaec2b74f2008-01-17 16:48:33 -0600149 if (nr == get_my_id()) {
150 printf("Invalid to release the boot core.\n\n");
151 return 1;
152 }
153
Kumar Gala79679d82008-03-26 08:34:25 -0500154 if (argc != 4) {
Kumar Galaec2b74f2008-01-17 16:48:33 -0600155 printf("Invalid number of arguments to release.\n\n");
156 return 1;
157 }
158
Kumar Gala79679d82008-03-26 08:34:25 -0500159 boot_addr = simple_strtoull(argv[0], NULL, 16);
Kumar Gala79679d82008-03-26 08:34:25 -0500160
York Sun3f0997b2012-10-08 07:44:29 +0000161 /* handle pir, r3 */
162 for (i = 1; i < 3; i++) {
Kumar Galaec2b74f2008-01-17 16:48:33 -0600163 if (argv[i][0] != '-') {
Kumar Gala79679d82008-03-26 08:34:25 -0500164 u8 entry = boot_entry_map[i];
Kumar Galaec2b74f2008-01-17 16:48:33 -0600165 val = simple_strtoul(argv[i], NULL, 16);
Kumar Gala79679d82008-03-26 08:34:25 -0500166 table[entry] = val;
Kumar Galaec2b74f2008-01-17 16:48:33 -0600167 }
168 }
169
Kumar Gala79679d82008-03-26 08:34:25 -0500170 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
Kumar Galacf6cc012008-04-28 02:24:04 -0500171
172 /* ensure all table updates complete before final address write */
173 eieio();
174
Kumar Gala79679d82008-03-26 08:34:25 -0500175 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
Kumar Galaec2b74f2008-01-17 16:48:33 -0600176
177 return 0;
178}
179
York Suneb539412012-10-08 07:44:25 +0000180u32 determine_mp_bootpg(unsigned int *pagesize)
Kumar Galac840d262009-03-31 23:11:05 -0500181{
York Suneb539412012-10-08 07:44:25 +0000182 u32 bootpg;
183#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
184 u32 svr = get_svr();
185 u32 granule_size, check;
186 struct law_entry e;
187#endif
188
York Sunffd06e02012-10-08 07:44:30 +0000189
190 /* use last 4K of mapped memory */
191 bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
192 CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
193 CONFIG_SYS_SDRAM_BASE - 4096;
York Suneb539412012-10-08 07:44:25 +0000194 if (pagesize)
195 *pagesize = 4096;
Kumar Galac840d262009-03-31 23:11:05 -0500196
York Suneb539412012-10-08 07:44:25 +0000197#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
198/*
199 * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
200 * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
201 * the way boot page chosen in u-boot avoids hitting this erratum. So only
202 * thw workaround for 3-way interleaving is needed.
203 *
204 * To make sure boot page translation works with 3-Way DDR interleaving
205 * enforce a check for the following constrains
206 * 8K granule size requires BRSIZE=8K and
207 * bootpg >> log2(BRSIZE) %3 == 1
208 * 4K and 1K granule size requires BRSIZE=4K and
209 * bootpg >> log2(BRSIZE) %3 == 0
210 */
211 if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
212 e = find_law(bootpg);
213 switch (e.trgt_id) {
214 case LAW_TRGT_IF_DDR_INTLV_123:
215 granule_size = fsl_ddr_get_intl3r() & 0x1f;
216 if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
217 if (pagesize)
218 *pagesize = 8192;
219 bootpg &= 0xffffe000; /* align to 8KB */
220 check = bootpg >> 13;
221 while ((check % 3) != 1)
222 check--;
223 bootpg = check << 13;
224 debug("Boot page (8K) at 0x%08x\n", bootpg);
225 break;
226 } else {
227 bootpg &= 0xfffff000; /* align to 4KB */
228 check = bootpg >> 12;
229 while ((check % 3) != 0)
230 check--;
231 bootpg = check << 12;
232 debug("Boot page (4K) at 0x%08x\n", bootpg);
233 }
234 break;
235 default:
236 break;
237 }
238 }
239#endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
240
241 return bootpg;
Kumar Galac840d262009-03-31 23:11:05 -0500242}
243
York Sunffd06e02012-10-08 07:44:30 +0000244phys_addr_t get_spin_phys_addr(void)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600245{
York Sunffd06e02012-10-08 07:44:30 +0000246 return virt_to_phys(&__spin_table);
Kumar Galaec2b74f2008-01-17 16:48:33 -0600247}
248
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500249#ifdef CONFIG_FSL_CORENET
York Suneb539412012-10-08 07:44:25 +0000250static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500251{
York Suneb539412012-10-08 07:44:25 +0000252 u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
York Sunffd06e02012-10-08 07:44:30 +0000253 u32 *table = (u32 *)&__spin_table;
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500254 volatile ccsr_gur_t *gur;
255 volatile ccsr_local_t *ccm;
256 volatile ccsr_rcpm_t *rcpm;
257 volatile ccsr_pic_t *pic;
258 int timeout = 10;
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500259 u32 mask = cpu_mask();
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500260 struct law_entry e;
261
262 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
263 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
264 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
Kim Phillips680c6132010-08-09 18:39:57 -0500265 pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500266
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500267 whoami = in_be32(&pic->whoami);
268 cpu_up_mask = 1 << whoami;
269 out_be32(&ccm->bstrl, bootpg);
270
271 e = find_law(bootpg);
York Suneb539412012-10-08 07:44:25 +0000272 /* pagesize is only 4K or 8K */
273 if (pagesize == 8192)
274 brsize = LAW_SIZE_8K;
275 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
276 debug("BRSIZE is 0x%x\n", brsize);
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500277
Dave Liuf5ecc6e2009-11-17 20:01:24 -0600278 /* readback to sync write */
279 in_be32(&ccm->bstrar);
280
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500281 /* disable time base at the platform */
282 out_be32(&rcpm->ctbenrl, cpu_up_mask);
283
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500284 out_be32(&gur->brrl, mask);
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500285
286 /* wait for everyone */
287 while (timeout) {
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500288 unsigned int i, cpu, nr_cpus = cpu_numcores();
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500289
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500290 for_each_cpu(i, cpu, nr_cpus, mask) {
291 if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
292 cpu_up_mask |= (1 << cpu);
293 }
294
295 if ((cpu_up_mask & mask) == mask)
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500296 break;
297
298 udelay(100);
299 timeout--;
300 }
301
302 if (timeout == 0)
303 printf("CPU up timeout. CPU up mask is %x should be %x\n",
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500304 cpu_up_mask, mask);
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500305
306 /* enable time base at the platform */
307 out_be32(&rcpm->ctbenrl, 0);
Kumar Gala7afc45a2011-03-13 10:55:53 -0500308
309 /* readback to sync write */
310 in_be32(&rcpm->ctbenrl);
311
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500312 mtspr(SPRN_TBWU, 0);
313 mtspr(SPRN_TBWL, 0);
Kumar Gala7afc45a2011-03-13 10:55:53 -0500314
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500315 out_be32(&rcpm->ctbenrl, mask);
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500316
317#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
318 /*
319 * Disabling Boot Page Translation allows the memory region 0xfffff000
320 * to 0xffffffff to be used normally. Leaving Boot Page Translation
321 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
322 * unusable for normal operation but it does allow OSes to easily
323 * reset a processor core to put it back into U-Boot's spinloop.
324 */
Ed Swarthoute81241a2011-03-03 18:28:14 -0600325 clrbits_be32(&ccm->bstrar, LAW_EN);
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500326#endif
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500327}
328#else
York Suneb539412012-10-08 07:44:25 +0000329static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600330{
331 u32 up, cpu_up_mask, whoami;
York Sunffd06e02012-10-08 07:44:30 +0000332 u32 *table = (u32 *)&__spin_table;
Kumar Galaec2b74f2008-01-17 16:48:33 -0600333 volatile u32 bpcr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
335 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kim Phillips680c6132010-08-09 18:39:57 -0500336 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Kumar Galaec2b74f2008-01-17 16:48:33 -0600337 u32 devdisr;
338 int timeout = 10;
339
340 whoami = in_be32(&pic->whoami);
341 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
342
343 /* disable time base at the platform */
344 devdisr = in_be32(&gur->devdisr);
345 if (whoami)
346 devdisr |= MPC85xx_DEVDISR_TB0;
347 else
348 devdisr |= MPC85xx_DEVDISR_TB1;
349 out_be32(&gur->devdisr, devdisr);
350
351 /* release the hounds */
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530352 up = ((1 << cpu_numcores()) - 1);
Kumar Galaec2b74f2008-01-17 16:48:33 -0600353 bpcr = in_be32(&ecm->eebpcr);
354 bpcr |= (up << 24);
355 out_be32(&ecm->eebpcr, bpcr);
356 asm("sync; isync; msync");
357
358 cpu_up_mask = 1 << whoami;
359 /* wait for everyone */
360 while (timeout) {
361 int i;
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530362 for (i = 0; i < cpu_numcores(); i++) {
Kumar Gala97b3ecb2008-04-09 04:20:57 -0500363 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
Kumar Galaec2b74f2008-01-17 16:48:33 -0600364 cpu_up_mask |= (1 << i);
365 };
366
367 if ((cpu_up_mask & up) == up)
368 break;
369
370 udelay(100);
371 timeout--;
372 }
373
Kumar Gala97b3ecb2008-04-09 04:20:57 -0500374 if (timeout == 0)
375 printf("CPU up timeout. CPU up mask is %x should be %x\n",
376 cpu_up_mask, up);
377
Kumar Galaec2b74f2008-01-17 16:48:33 -0600378 /* enable time base at the platform */
379 if (whoami)
380 devdisr |= MPC85xx_DEVDISR_TB1;
381 else
382 devdisr |= MPC85xx_DEVDISR_TB0;
383 out_be32(&gur->devdisr, devdisr);
Kumar Gala7afc45a2011-03-13 10:55:53 -0500384
385 /* readback to sync write */
386 in_be32(&gur->devdisr);
387
Kumar Galaec2b74f2008-01-17 16:48:33 -0600388 mtspr(SPRN_TBWU, 0);
389 mtspr(SPRN_TBWL, 0);
390
391 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
392 out_be32(&gur->devdisr, devdisr);
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500393
394#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
395 /*
396 * Disabling Boot Page Translation allows the memory region 0xfffff000
397 * to 0xffffffff to be used normally. Leaving Boot Page Translation
398 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
399 * unusable for normal operation but it does allow OSes to easily
400 * reset a processor core to put it back into U-Boot's spinloop.
401 */
402 clrbits_be32(&ecm->bptr, 0x80000000);
403#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -0600404}
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500405#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -0600406
Kumar Galadd6c9102008-03-26 08:53:53 -0500407void cpu_mp_lmb_reserve(struct lmb *lmb)
408{
York Suneb539412012-10-08 07:44:25 +0000409 u32 bootpg = determine_mp_bootpg(NULL);
Kumar Galadd6c9102008-03-26 08:53:53 -0500410
411 lmb_reserve(lmb, bootpg, 4096);
412}
413
Kumar Galaec2b74f2008-01-17 16:48:33 -0600414void setup_mp(void)
415{
York Sunffd06e02012-10-08 07:44:30 +0000416 extern u32 __secondary_start_page;
417 extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
York Suneb539412012-10-08 07:44:25 +0000418
York Sunffd06e02012-10-08 07:44:30 +0000419 int i;
420 ulong fixup = (u32)&__secondary_start_page;
York Suneb539412012-10-08 07:44:25 +0000421 u32 bootpg, bootpg_map, pagesize;
422
423 bootpg = determine_mp_bootpg(&pagesize);
424
425 /*
426 * pagesize is only 4K or 8K
427 * we only use the last 4K of boot page
428 * bootpg_map saves the address for the boot page
429 * 8K is used for the workaround of 3-way DDR interleaving
430 */
431
432 bootpg_map = bootpg;
433
434 if (pagesize == 8192)
435 bootpg += 4096; /* use 2nd half */
Kumar Galaec2b74f2008-01-17 16:48:33 -0600436
Aaron Sierra9d64c6b2010-09-30 12:22:16 -0500437 /* Some OSes expect secondary cores to be held in reset */
438 if (hold_cores_in_reset(0))
439 return;
440
York Sunffd06e02012-10-08 07:44:30 +0000441 /*
442 * Store the bootpg's cache-able half address for use by secondary
443 * CPU cores to continue to boot
444 */
445 __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
446
447 /* Store spin table's physical address for use by secondary cores */
448 __spin_table_addr = (u32)get_spin_phys_addr();
449
450 /* flush bootpg it before copying invalidate any staled cacheline */
451 flush_cache(bootpg, 4096);
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500452
Kumar Galac7259082009-09-03 08:41:31 -0500453 /* look for the tlb covering the reset page, there better be one */
York Sunffd06e02012-10-08 07:44:30 +0000454 i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
Kumar Galaec2b74f2008-01-17 16:48:33 -0600455
Kumar Galac7259082009-09-03 08:41:31 -0500456 /* we found a match */
457 if (i != -1) {
458 /* map reset page to bootpg so we can copy code there */
459 disable_tlb(i);
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500460
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500461 set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
Kumar Galaabc76eb2009-11-17 20:21:20 -0600462 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
Kumar Galac7259082009-09-03 08:41:31 -0500463 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
464
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500465 memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
466
York Suneb539412012-10-08 07:44:25 +0000467 plat_mp_up(bootpg_map, pagesize);
Kumar Galac7259082009-09-03 08:41:31 -0500468 } else {
469 puts("WARNING: No reset page TLB. "
470 "Skipping secondary core setup\n");
471 }
Kumar Galaec2b74f2008-01-17 16:48:33 -0600472}