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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefano Babic5b591502010-10-06 09:00:01 +02002/*
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
Stefano Babic5b591502010-10-06 09:00:01 +02004 */
5
6
7#include <common.h>
8#include <usb.h>
9#include <asm/io.h>
Stefano Babic86271112011-03-14 15:43:56 +010010#include <asm/arch/imx-regs.h>
Simon Glassc05ed002020-05-10 11:40:11 -060011#include <linux/delay.h>
Mateusz Kulikowskie162c6b2016-03-31 23:12:23 +020012#include <usb/ehci-ci.h>
Stefano Babic5b591502010-10-06 09:00:01 +020013#include <errno.h>
14
15#include "ehci.h"
Stefano Babic5b591502010-10-06 09:00:01 +020016
17#define USBCTRL_OTGBASE_OFFSET 0x600
18
Benoît Thébaudeau9fa3d092012-11-13 09:57:48 +000019#define MX25_OTG_SIC_SHIFT 29
20#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
21#define MX25_OTG_PM_BIT (1 << 24)
22#define MX25_OTG_PP_BIT (1 << 11)
23#define MX25_OTG_OCPOL_BIT (1 << 3)
24
25#define MX25_H1_SIC_SHIFT 21
26#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
27#define MX25_H1_PP_BIT (1 << 18)
Benoît Thébaudeaufa88ddb2012-11-16 06:46:24 +000028#define MX25_H1_PM_BIT (1 << 16)
Benoît Thébaudeau9fa3d092012-11-13 09:57:48 +000029#define MX25_H1_IPPUE_UP_BIT (1 << 7)
30#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
31#define MX25_H1_TLL_BIT (1 << 5)
32#define MX25_H1_USBTE_BIT (1 << 4)
33#define MX25_H1_OCPOL_BIT (1 << 2)
Matthias Weisserdddb7c92011-07-06 00:28:30 +000034
Stefano Babic5b591502010-10-06 09:00:01 +020035#define MX31_OTG_SIC_SHIFT 29
36#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
37#define MX31_OTG_PM_BIT (1 << 24)
38
39#define MX31_H2_SIC_SHIFT 21
40#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
41#define MX31_H2_PM_BIT (1 << 16)
42#define MX31_H2_DT_BIT (1 << 5)
43
44#define MX31_H1_SIC_SHIFT 13
45#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
46#define MX31_H1_PM_BIT (1 << 8)
47#define MX31_H1_DT_BIT (1 << 4)
48
Benoît Thébaudeau71a5c552012-11-13 09:58:12 +000049#define MX35_OTG_SIC_SHIFT 29
50#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
51#define MX35_OTG_PM_BIT (1 << 24)
52#define MX35_OTG_PP_BIT (1 << 11)
53#define MX35_OTG_OCPOL_BIT (1 << 3)
54
55#define MX35_H1_SIC_SHIFT 21
56#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
57#define MX35_H1_PP_BIT (1 << 18)
Benoît Thébaudeaued0a6fc2012-11-16 01:42:49 +000058#define MX35_H1_PM_BIT (1 << 16)
Benoît Thébaudeau71a5c552012-11-13 09:58:12 +000059#define MX35_H1_IPPUE_UP_BIT (1 << 7)
60#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
61#define MX35_H1_TLL_BIT (1 << 5)
62#define MX35_H1_USBTE_BIT (1 << 4)
63#define MX35_H1_OCPOL_BIT (1 << 2)
64
Stefano Babic5b591502010-10-06 09:00:01 +020065static int mxc_set_usbcontrol(int port, unsigned int flags)
66{
67 unsigned int v;
Matthias Weisserdddb7c92011-07-06 00:28:30 +000068
Benoît Thébaudeau164738e2012-11-13 09:55:57 +000069 v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
Benoît Thébaudeau9fa3d092012-11-13 09:57:48 +000070#if defined(CONFIG_MX25)
71 switch (port) {
72 case 0: /* OTG port */
73 v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
74 MX25_OTG_OCPOL_BIT);
75 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
Benoît Thébaudeau164738e2012-11-13 09:55:57 +000076
Benoît Thébaudeau9fa3d092012-11-13 09:57:48 +000077 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
78 v |= MX25_OTG_PM_BIT;
79
80 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
81 v |= MX25_OTG_PP_BIT;
82
83 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
84 v |= MX25_OTG_OCPOL_BIT;
85
86 break;
87 case 1: /* H1 port */
88 v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
89 MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
90 MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
91 MX25_H1_IPPUE_UP_BIT);
92 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
93
94 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
95 v |= MX25_H1_PM_BIT;
96
97 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
98 v |= MX25_H1_PP_BIT;
99
100 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
101 v |= MX25_H1_OCPOL_BIT;
102
103 if (!(flags & MXC_EHCI_TTL_ENABLED))
104 v |= MX25_H1_TLL_BIT;
105
106 if (flags & MXC_EHCI_INTERNAL_PHY)
107 v |= MX25_H1_USBTE_BIT;
108
109 if (flags & MXC_EHCI_IPPUE_DOWN)
110 v |= MX25_H1_IPPUE_DOWN_BIT;
111
112 if (flags & MXC_EHCI_IPPUE_UP)
113 v |= MX25_H1_IPPUE_UP_BIT;
114
115 break;
116 default:
117 return -EINVAL;
118 }
119#elif defined(CONFIG_MX31)
Benoît Thébaudeau164738e2012-11-13 09:55:57 +0000120 switch (port) {
121 case 0: /* OTG port */
122 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
123 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
124
125 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
126 v |= MX31_OTG_PM_BIT;
127
128 break;
129 case 1: /* H1 port */
130 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
131 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
132
133 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
134 v |= MX31_H1_PM_BIT;
135
136 if (!(flags & MXC_EHCI_TTL_ENABLED))
137 v |= MX31_H1_DT_BIT;
138
139 break;
140 case 2: /* H2 port */
141 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
142 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
143
144 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
145 v |= MX31_H2_PM_BIT;
146
147 if (!(flags & MXC_EHCI_TTL_ENABLED))
148 v |= MX31_H2_DT_BIT;
149
150 break;
151 default:
152 return -EINVAL;
153 }
Benoît Thébaudeau71a5c552012-11-13 09:58:12 +0000154#elif defined(CONFIG_MX35)
155 switch (port) {
156 case 0: /* OTG port */
157 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
158 MX35_OTG_OCPOL_BIT);
159 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
160
161 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
162 v |= MX35_OTG_PM_BIT;
163
164 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
165 v |= MX35_OTG_PP_BIT;
166
167 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
168 v |= MX35_OTG_OCPOL_BIT;
169
170 break;
171 case 1: /* H1 port */
172 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
173 MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
174 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
175 MX35_H1_IPPUE_UP_BIT);
176 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
177
178 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
179 v |= MX35_H1_PM_BIT;
180
181 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
182 v |= MX35_H1_PP_BIT;
183
184 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
185 v |= MX35_H1_OCPOL_BIT;
186
187 if (!(flags & MXC_EHCI_TTL_ENABLED))
188 v |= MX35_H1_TLL_BIT;
189
190 if (flags & MXC_EHCI_INTERNAL_PHY)
191 v |= MX35_H1_USBTE_BIT;
192
193 if (flags & MXC_EHCI_IPPUE_DOWN)
194 v |= MX35_H1_IPPUE_DOWN_BIT;
195
196 if (flags & MXC_EHCI_IPPUE_UP)
197 v |= MX35_H1_IPPUE_UP_BIT;
198
199 break;
200 default:
201 return -EINVAL;
202 }
Benoît Thébaudeau164738e2012-11-13 09:55:57 +0000203#else
204#error MXC EHCI USB driver not supported on this platform
Matthias Weisserdddb7c92011-07-06 00:28:30 +0000205#endif
Matthias Weisserdddb7c92011-07-06 00:28:30 +0000206 writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
Benoît Thébaudeau164738e2012-11-13 09:55:57 +0000207
Matthias Weisserdddb7c92011-07-06 00:28:30 +0000208 return 0;
Stefano Babic5b591502010-10-06 09:00:01 +0200209}
210
Troy Kisky127efc42013-10-10 15:27:57 -0700211int ehci_hcd_init(int index, enum usb_init_type init,
212 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Stefano Babic5b591502010-10-06 09:00:01 +0200213{
Stefano Babic5b591502010-10-06 09:00:01 +0200214 struct usb_ehci *ehci;
Matthias Weisserdddb7c92011-07-06 00:28:30 +0000215#ifdef CONFIG_MX31
Stefano Babic5b591502010-10-06 09:00:01 +0200216 struct clock_control_regs *sc_regs =
217 (struct clock_control_regs *)CCM_BASE;
218
Anatolij Gustschinf55feaf2011-11-19 10:10:33 +0000219 __raw_readl(&sc_regs->ccmr);
Stefano Babic5b591502010-10-06 09:00:01 +0200220 __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
Matthias Weisserdddb7c92011-07-06 00:28:30 +0000221#endif
Stefano Babic5b591502010-10-06 09:00:01 +0200222
223 udelay(80);
224
Matthias Weisserdddb7c92011-07-06 00:28:30 +0000225 ehci = (struct usb_ehci *)(IMX_USB_BASE +
Benoît Thébaudeau34d33b62012-11-13 09:57:59 +0000226 IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
Lucas Stach676ae062012-09-26 00:14:35 +0200227 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
228 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
229 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
Stefano Babic5b591502010-10-06 09:00:01 +0200230 setbits_le32(&ehci->usbmode, CM_HOST);
Stefano Babic5b591502010-10-06 09:00:01 +0200231 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
Stefano Babic5b591502010-10-06 09:00:01 +0200232 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
Benoît Thébaudeau71a5c552012-11-13 09:58:12 +0000233#ifdef CONFIG_MX35
234 /* Workaround for ENGcm11601 */
235 __raw_writel(0, &ehci->sbuscfg);
236#endif
Stefano Babic5b591502010-10-06 09:00:01 +0200237
Stefano Babica2f9bff2010-10-18 10:23:05 +0200238 udelay(10000);
239
Stefano Babic5b591502010-10-06 09:00:01 +0200240 return 0;
241}
242
243/*
244 * Destroy the appropriate control structures corresponding
245 * the the EHCI host controller.
246 */
Lucas Stach676ae062012-09-26 00:14:35 +0200247int ehci_hcd_stop(int index)
Stefano Babic5b591502010-10-06 09:00:01 +0200248{
249 return 0;
250}