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Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +02002 * (C) Copyright 2007-2009 DENX Software Engineering
Rafal Jaworowski8993e542007-07-27 14:43:59 +02003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Rafal Jaworowski8993e542007-07-27 14:43:59 +02005 */
6
7/*
Wolfgang Denk72601d02009-05-16 10:47:41 +02008 * MPC5121ADS board configuration file
Rafal Jaworowski8993e542007-07-27 14:43:59 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Wolfgang Denk72601d02009-05-16 10:47:41 +020014#define CONFIG_MPC5121ADS 1
Anatolij Gustschin10e99d82014-10-21 13:46:59 +020015#define CONFIG_DISPLAY_BOARDINFO
16#define CONFIG_SYS_GENERIC_BOARD
17
Rafal Jaworowski8993e542007-07-27 14:43:59 +020018/*
Wolfgang Denk72601d02009-05-16 10:47:41 +020019 * Memory map for the MPC5121ADS board:
Rafal Jaworowski8993e542007-07-27 14:43:59 +020020 *
21 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
22 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
23 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
24 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
John Rigby5f91db72008-02-26 09:38:14 -070025 * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
26 * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
27 * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020028 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
29 */
30
31/*
32 * High Level Configuration Options
33 */
34#define CONFIG_E300 1 /* E300 Family */
York Sun0e1bad42008-05-05 10:20:01 -050035
Wolfgang Denk2ae18242010-10-06 09:05:45 +020036#define CONFIG_SYS_TEXT_BASE 0xFFF00000
37
York Sun0e1bad42008-05-05 10:20:01 -050038/* video */
Timur Tabi7d3053f2011-02-15 17:09:19 -060039#ifdef CONFIG_FSL_DIU_FB
40#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
41#define CONFIG_VIDEO
Timur Tabie69e5202010-08-31 19:56:43 -050042#define CONFIG_CMD_BMP
York Sun0e1bad42008-05-05 10:20:01 -050043#define CONFIG_CFB_CONSOLE
Timur Tabi7d3053f2011-02-15 17:09:19 -060044#define CONFIG_VIDEO_SW_CURSOR
York Sun0e1bad42008-05-05 10:20:01 -050045#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabie69e5202010-08-31 19:56:43 -050046#define CONFIG_VIDEO_LOGO
47#define CONFIG_VIDEO_BMP_LOGO
York Sun0e1bad42008-05-05 10:20:01 -050048#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020049
John Rigby5f91db72008-02-26 09:38:14 -070050/* CONFIG_PCI is defined at config time */
Rafal Jaworowski8993e542007-07-27 14:43:59 +020051
Wolfgang Denk72601d02009-05-16 10:47:41 +020052#ifdef CONFIG_MPC5121ADS_REV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */
Martha Marxf31c49d2008-05-29 14:23:25 -040054#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
Martha Marxf31c49d2008-05-29 14:23:25 -040056#define CONFIG_PCI
57#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020058
59#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
York Sun0e1bad42008-05-05 10:20:01 -050060#define CONFIG_MISC_INIT_R
Rafal Jaworowski8993e542007-07-27 14:43:59 +020061
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_IMMR 0x80000000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020063
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
65#define CONFIG_SYS_MEMTEST_END 0x00400000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020066
67/*
68 * DDR Setup - manually set all parameters as there's no SPD etc.
69 */
Wolfgang Denk72601d02009-05-16 10:47:41 +020070#ifdef CONFIG_MPC5121ADS_REV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Martha Marxf31c49d2008-05-29 14:23:25 -040072#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_DDR_SIZE 512 /* MB */
Martha Marxf31c49d2008-05-29 14:23:25 -040074#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
76#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Anatolij Gustschinb9947bb2010-04-24 19:27:08 +020077#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020078
Anatolij Gustschin5d937e82010-04-24 19:27:07 +020079#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
80
Rafal Jaworowski8993e542007-07-27 14:43:59 +020081/* DDR Controller Configuration
Wolfgang Denkb1b54e32007-08-02 21:27:46 +020082 *
83 * SYS_CFG:
84 * [31:31] MDDRC Soft Reset: Diabled
85 * [30:30] DRAM CKE pin: Enabled
86 * [29:29] DRAM CLK: Enabled
87 * [28:28] Command Mode: Enabled (For initialization only)
88 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
89 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
90 * [20:19] Read Test: DON'T USE
91 * [18:18] Self Refresh: Enabled
92 * [17:17] 16bit Mode: Disabled
93 * [16:13] Ready Delay: 2
94 * [12:12] Half DQS Delay: Disabled
95 * [11:11] Quarter DQS Delay: Disabled
96 * [10:08] Write Delay: 2
97 * [07:07] Early ODT: Disabled
98 * [06:06] On DIE Termination: Disabled
99 * [05:05] FIFO Overflow Clear: DON'T USE here
100 * [04:04] FIFO Underflow Clear: DON'T USE here
101 * [03:03] FIFO Overflow Pending: DON'T USE here
102 * [02:02] FIFO Underlfow Pending: DON'T USE here
103 * [01:01] FIFO Overlfow Enabled: Enabled
104 * [00:00] FIFO Underflow Enabled: Enabled
105 * TIME_CFG0
106 * [31:16] DRAM Refresh Time: 0 CSB clocks
107 * [15:8] DRAM Command Time: 0 CSB clocks
108 * [07:00] DRAM Precharge Time: 0 CSB clocks
109 * TIME_CFG1
110 * [31:26] DRAM tRFC:
111 * [25:21] DRAM tWR1:
112 * [20:17] DRAM tWRT1:
113 * [16:11] DRAM tDRR:
114 * [10:05] DRAM tRC:
115 * [04:00] DRAM tRAS:
116 * TIME_CFG2
117 * [31:28] DRAM tRCD:
118 * [27:23] DRAM tFAW:
119 * [22:19] DRAM tRTW1:
120 * [18:15] DRAM tCCD:
121 * [14:10] DRAM tRTP:
122 * [09:05] DRAM tRP:
123 * [04:00] DRAM tRPA
124 */
Wolfgang Denk72601d02009-05-16 10:47:41 +0200125#ifdef CONFIG_MPC5121ADS_REV2
Martha M Stan054197b2009-09-21 14:07:14 -0400126#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
128#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
Martha Marxf31c49d2008-05-29 14:23:25 -0400129#else
Martha M Stan054197b2009-09-21 14:07:14 -0400130#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
131#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
132#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
Martha Marxf31c49d2008-05-29 14:23:25 -0400133#endif
Martha M Stan054197b2009-09-21 14:07:14 -0400134#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200135
Martha M Stana5aa3992009-09-21 14:08:00 -0400136#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00
137#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189
138#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864
139
Martha M Stan054197b2009-09-21 14:07:14 -0400140#define CONFIG_SYS_DDRCMD_NOP 0x01380000
141#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
142#define CONFIG_SYS_DDRCMD_EM2 0x01020000
143#define CONFIG_SYS_DDRCMD_EM3 0x01030000
144#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
145#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
Martha M Stana5aa3992009-09-21 14:08:00 -0400146
147#define DDRCMD_EMR_OCD(pr, ohm) ( \
148 (1 << 24) | /* MDDRC Command Request */ \
149 (1 << 16) | /* MODE Reg BA[2:0] */ \
150 (0 << 12) | /* Outputs 0=Enabled */ \
151 (0 << 11) | /* RDQS */ \
152 (1 << 10) | /* DQS# */ \
153 (pr << 7) | /* OCD prog 7=deflt,0=exit */ \
154 /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
155 ((ohm & 0x2) << 5)| /* Rtt1 */ \
156 (0 << 3) | /* additive posted CAS# */ \
157 ((ohm & 0x1) << 2)| /* Rtt0 */ \
158 (0 << 0) | /* Output Drive Strength */ \
159 (0 << 0)) /* DLL Enable 0=Normal */
160
161#define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0)
162#define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0)
163
164#define DDRCMD_MODE_REG(cas, wr) ( \
165 (1 << 24) | /* MDDRC Command Request */ \
166 (0 << 16) | /* MODE Reg BA[2:0] */ \
167 ((wr-1) << 9)| /* Write Recovery */ \
168 (cas << 4) | /* CAS */ \
169 (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \
170 (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */
171
172#define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3)
173#define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4)
174#define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8))
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200175
176/* DDR Priority Manager Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
178#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
179#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
180#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
181#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
182#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
183#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
184#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
185#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
186#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
187#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
188#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
189#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
190#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
191#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
192#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
193#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
194#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
195#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
196#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
197#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
198#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
199#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200200
201/*
202 * NOR FLASH on the Local Bus
203 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400204#undef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200206#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Martha Marxf31c49d2008-05-29 14:23:25 -0400207#ifdef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
209#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */
Martha Marxf31c49d2008-05-29 14:23:25 -0400210#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
212#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */
Martha Marxf31c49d2008-05-29 14:23:25 -0400213#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
215#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
216#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
217#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#undef CONFIG_SYS_FLASH_CHECKSUM
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200220
221/*
Stefan Roese229549a2009-06-09 16:57:47 +0200222 * NAND FLASH
Wolfgang Denk13946922009-06-14 20:58:50 +0200223 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
Stefan Roese229549a2009-06-09 16:57:47 +0200224 */
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200225#define CONFIG_CMD_NAND /* enable NAND support */
226#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
Stefan Roese229549a2009-06-09 16:57:47 +0200227#define CONFIG_NAND_MPC5121_NFC
228#define CONFIG_SYS_NAND_BASE 0x40000000
229
230#define CONFIG_SYS_MAX_NAND_DEVICE 2
Stefan Roese229549a2009-06-09 16:57:47 +0200231#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
232
233/*
234 * Configuration parameters for MPC5121 NAND driver
235 */
236#define CONFIG_FSL_NFC_WIDTH 1
237#define CONFIG_FSL_NFC_WRITE_SIZE 2048
238#define CONFIG_FSL_NFC_SPARE_SIZE 64
239#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
240
241/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200242 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
243 * window is 64KB
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_CPLD_BASE 0x82000000
246#define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */
Anatolij Gustschin676c6692013-02-08 00:03:44 +0000247#define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE
248#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_SRAM_BASE 0x30000000
251#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
254#define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
255#define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200256
257/* Use SRAM for initial stack */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200259#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200260
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200261#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200263
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200264#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
Stefan Roese229549a2009-06-09 16:57:47 +0200265#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
York Sun0e1bad42008-05-05 10:20:01 -0500266#ifdef CONFIG_FSL_DIU_FB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
York Sun0e1bad42008-05-05 10:20:01 -0500268#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
York Sun0e1bad42008-05-05 10:20:01 -0500270#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200271
272/*
273 * Serial Port
274 */
275#define CONFIG_CONS_INDEX 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200276
277/*
278 * Serial console configuration
279 */
280#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
Marek Vasutbfb31272012-09-16 16:07:24 +0200281#define CONFIG_SYS_PSC3
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200282#if CONFIG_PSC_CONSOLE != 3
283#error CONFIG_PSC_CONSOLE must be 3
284#endif
285#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_BAUDRATE_TABLE \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200287 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
288
289#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
290#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
291#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
292#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
293
294#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
295/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_HUSH_PARSER
297#ifdef CONFIG_SYS_HUSH_PARSER
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200298#endif
299
John Rigby5f91db72008-02-26 09:38:14 -0700300/*
Anatolij Gustschine5f53862013-02-08 00:03:45 +0000301 * Clocks in use
302 */
303#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
304 CLOCK_SCCR1_DDR_EN | \
305 CLOCK_SCCR1_FEC_EN | \
306 CLOCK_SCCR1_LPC_EN | \
307 CLOCK_SCCR1_NFC_EN | \
308 CLOCK_SCCR1_PATA_EN | \
309 CLOCK_SCCR1_PCI_EN | \
310 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
311 CLOCK_SCCR1_PSCFIFO_EN | \
312 CLOCK_SCCR1_TPR_EN)
313
314#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
315 CLOCK_SCCR2_I2C_EN | \
316 CLOCK_SCCR2_MEM_EN | \
317 CLOCK_SCCR2_SPDIF_EN | \
318 CLOCK_SCCR2_USB1_EN | \
319 CLOCK_SCCR2_USB2_EN)
320
321/*
John Rigby5f91db72008-02-26 09:38:14 -0700322 * PCI
323 */
324#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000325#define CONFIG_PCI_INDIRECT_BRIDGE
John Rigby5f91db72008-02-26 09:38:14 -0700326
327/*
328 * General PCI
329 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
331#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
332#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
333#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
334#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
335#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
336#define CONFIG_SYS_PCI_IO_BASE 0x00000000
337#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
338#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
John Rigby5f91db72008-02-26 09:38:14 -0700339
340
341#define CONFIG_PCI_PNP /* do pci plug-and-play */
342
343#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
344
345#endif
346
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200347/* I2C */
348#define CONFIG_HARD_I2C /* I2C with hardware support */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200349#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
351#define CONFIG_SYS_I2C_SLAVE 0x7F
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200352#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200354#endif
355
356/*
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700357 * IIM - IC Identification Module
358 */
Benoît Thébaudeau83306922013-04-23 10:17:42 +0000359#undef CONFIG_FSL_IIM
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700360
361/*
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200362 * EEPROM configuration
363 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
365#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
366#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
367#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200368
369/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200370 * Ethernet configuration
371 */
372#define CONFIG_MPC512x_FEC 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200373#define CONFIG_PHY_ADDR 0x1
374#define CONFIG_MII 1 /* MII PHY management */
Martha Marxf31c49d2008-05-29 14:23:25 -0400375#define CONFIG_FEC_AN_TIMEOUT 1
John Rigbyef11df62008-08-05 17:38:57 -0600376#define CONFIG_HAS_ETH0
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200377
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200378/*
379 * Configure on-board RTC
380 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400381#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200383
384/*
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200385 * USB Support
386 */
387#define CONFIG_CMD_USB
388
389#if defined(CONFIG_CMD_USB)
390#define CONFIG_USB_EHCI /* Enable EHCI Support */
391#define CONFIG_USB_EHCI_FSL /* On a FSL platform */
392#define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */
393#define CONFIG_EHCI_DESC_BIG_ENDIAN
394#define CONFIG_EHCI_IS_TDI
395#define CONFIG_USB_STORAGE
396#endif
397
398/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200399 * Environment
400 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200401#define CONFIG_ENV_IS_IN_FLASH 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200402/* This has to be a multiple of the Flash sector size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200404#define CONFIG_ENV_SIZE 0x2000
Martha Marxf31c49d2008-05-29 14:23:25 -0400405#ifdef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200406#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
Martha Marxf31c49d2008-05-29 14:23:25 -0400407#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200408#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
Martha Marxf31c49d2008-05-29 14:23:25 -0400409#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200410
411/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200412#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
413#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200414
415#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200417
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200418#define CONFIG_CMD_ASKENV
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200419#define CONFIG_CMD_DATE
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200420#define CONFIG_CMD_DHCP
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200421#define CONFIG_CMD_EEPROM
422#define CONFIG_CMD_EXT2
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200423#define CONFIG_CMD_I2C
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200424#define CONFIG_CMD_IDE
425#define CONFIG_CMD_JFFS2
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200426#define CONFIG_CMD_MII
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200427#define CONFIG_CMD_PING
428#define CONFIG_CMD_REGINFO
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200429
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700430#undef CONFIG_CMD_FUSE
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200431
432#if defined(CONFIG_PCI)
433#define CONFIG_CMD_PCI
434#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200435
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200436/*
437 * Dynamic MTD partition support
438 */
439#define CONFIG_CMD_MTDPARTS
440#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
441#define CONFIG_FLASH_CFI_MTD
442#define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand"
443
444/*
445 * NOR flash layout:
446 *
447 * FC000000 - FEABFFFF 42.75 MiB User Data
448 * FEAC0000 - FFABFFFF 16 MiB Root File System
449 * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel
450 * FFEC0000 - FFEFFFFF 256 KiB Device Tree
451 * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env
452 *
453 * NAND flash layout: one big partition
454 */
455#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \
456 "16m(rootfs)," \
457 "4m(kernel)," \
458 "256k(dtb)," \
459 "1m(u-boot);" \
460 "mpc5121.nand:-(data)"
461
462
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200463#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
464
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700465#define CONFIG_DOS_PARTITION
466#define CONFIG_MAC_PARTITION
467#define CONFIG_ISO_PARTITION
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200468
469#define CONFIG_CMD_FAT
470#define CONFIG_SUPPORT_VFAT
471
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700472#endif /* defined(CONFIG_CMD_IDE) */
473
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200474/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
476 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200477 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
478 * to chapter 36 of the MPC5121e Reference Manual.
479 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100480/* #define CONFIG_WATCHDOG */ /* enable watchdog */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200482
483 /*
484 * Miscellaneous configurable options
485 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#define CONFIG_SYS_LONGHELP /* undef to save memory */
487#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200488
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200489#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200491#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200493#endif
494
495
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
497#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
498#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200499
500/*
501 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700502 * have to be in the first 256 MB of memory, since this is
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200503 * the maximum mapped by the Linux kernel during initialization.
504 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700505#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200506
507/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_DCACHE_SIZE 32768
509#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200510#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200512#endif
513
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_HID0_INIT 0x000000000
Wolfgang Denke2b66fe2009-03-26 10:00:57 +0100515#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200516#define CONFIG_SYS_HID2 HID2_HBE
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200517
Becky Bruce31d82672008-05-08 19:02:12 -0500518#define CONFIG_HIGH_BATS 1 /* High BATs supported */
519
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200520#ifdef CONFIG_CMD_KGDB
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200521#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200522#endif
523
524/*
525 * Environment Configuration
526 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100527#define CONFIG_TIMESTAMP
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200528
Wolfgang Denk72601d02009-05-16 10:47:41 +0200529#define CONFIG_HOSTNAME mpc5121ads
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000530#define CONFIG_BOOTFILE "mpc5121ads/uImage"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000531#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200532
Wolfgang Denk8d103072008-01-13 23:37:50 +0100533#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200534
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200535#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200536#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
537
538#define CONFIG_BAUDRATE 115200
539
540#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100541 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200542 "echo"
543
544#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100545 "u-boot_addr_r=200000\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200546 "kernel_addr_r=600000\0" \
547 "fdt_addr_r=880000\0" \
548 "ramdisk_addr_r=900000\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100549 "u-boot_addr=FFF00000\0" \
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200550 "kernel_addr=FFAC0000\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200551 "fdt_addr=FFEC0000\0" \
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200552 "ramdisk_addr=FEAC0000\0" \
Wolfgang Denk72601d02009-05-16 10:47:41 +0200553 "ramdiskfile=mpc5121ads/uRamdisk\0" \
554 "u-boot=mpc5121ads/u-boot.bin\0" \
555 "bootfile=mpc5121ads/uImage\0" \
556 "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200557 "rootpath=/opt/eldk/ppc_6xx\n" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200558 "netdev=eth0\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100559 "consdev=ttyPSC0\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200560 "nfsargs=setenv bootargs root=/dev/nfs rw " \
561 "nfsroot=${serverip}:${rootpath}\0" \
562 "ramargs=setenv bootargs root=/dev/ram rw\0" \
563 "addip=setenv bootargs ${bootargs} " \
564 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
565 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100566 "addtty=setenv bootargs ${bootargs} " \
567 "console=${consdev},${baudrate}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200568 "flash_nfs=run nfsargs addip addtty;" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200569 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200570 "flash_self=run ramargs addip addtty;" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100571 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
572 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
573 "tftp ${fdt_addr_r} ${fdtfile};" \
574 "run nfsargs addip addtty;" \
575 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
576 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
577 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200578 "tftp ${fdt_addr_r} ${fdtfile};" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100579 "run ramargs addip addtty;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100580 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
Detlev Zundela99715b2008-04-18 14:50:01 +0200581 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100582 "update=protect off ${u-boot_addr} +${filesize};" \
583 "era ${u-boot_addr} +${filesize};" \
584 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
585 "upd=run load update\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200586 ""
587
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200588#define CONFIG_BOOTCOMMAND "run flash_self"
589
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100590#define CONFIG_OF_LIBFDT 1
591#define CONFIG_OF_BOARD_SETUP 1
John Rigbyef11df62008-08-05 17:38:57 -0600592#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100593
594#define OF_CPU "PowerPC,5121@0"
John Rigbyef11df62008-08-05 17:38:57 -0600595#define OF_SOC_COMPAT "fsl,mpc5121-immr"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100596#define OF_TBCLK (bd->bi_busfreq / 4)
John Rigbyac915282008-01-30 13:36:57 -0700597#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100598
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700599/*-----------------------------------------------------------------------
600 * IDE/ATA stuff
601 *-----------------------------------------------------------------------
602 */
603
604#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
605#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
606#undef CONFIG_IDE_LED /* LED for IDE not supported */
607
608#define CONFIG_IDE_RESET /* reset for IDE supported */
609#define CONFIG_IDE_PREINIT
610
611#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
612#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
613
614#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +0200615#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700616
617/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
618#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
619
620/* Offset for normal register accesses */
621#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
622
623/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
624#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
625
626/* Interval between registers */
627#define CONFIG_SYS_ATA_STRIDE 4
628
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +0200629#define ATA_BASE_ADDR get_pata_base()
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700630
631/*
632 * Control register bit definitions
633 */
634#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
635#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
636#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
637#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
638#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
639#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
640#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
641#define FSL_ATA_CTRL_IORDY_EN 0x01000000
642
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200643#endif /* __CONFIG_H */