blob: 3946607512dfec9e5737133663879284e6464c9f [file] [log] [blame]
Mike Dunn0dc0e842013-06-18 11:08:50 -07001/*
2 * Palm Treo 680 configuration file
3 *
4 * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
5 *
6 * This file is released under the terms of GPL v2 and any later version.
7 * See the file COPYING in the root directory of the source tree for details.
8 *
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Board Configuration Options
16 */
17#define CONFIG_CPU_PXA27X
18#define CONFIG_PALMTREO680
19#define CONFIG_MACH_TYPE MACH_TYPE_TREO680
20
21#define CONFIG_SYS_MALLOC_LEN (4096*1024)
22
23#define CONFIG_LZMA
24
25/*
26 * Serial Console Configuration
27 */
28#define CONFIG_PXA_SERIAL
29#define CONFIG_FFUART 1
30#define CONFIG_BAUDRATE 9600
31#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
32#define CONFIG_CONS_INDEX 3
33
34/* we have nand (although technically nand *is* flash...) */
35#define CONFIG_SYS_NO_FLASH
36
37#define CONFIG_LCD
38/* #define CONFIG_KEYBOARD */ /* TODO */
39
40/*
41 * Bootloader Components Configuration
42 */
Mike Dunn0dc0e842013-06-18 11:08:50 -070043#define CONFIG_CMD_ENV
44#define CONFIG_CMD_MMC
45#define CONFIG_CMD_NAND
46
47#define CONFIG_CMDLINE_TAG
48#define CONFIG_SETUP_MEMORY_TAGS
49
50/*
51 * MMC Card Configuration
52 */
53#ifdef CONFIG_CMD_MMC
54#define CONFIG_MMC
55#define CONFIG_GENERIC_MMC
56#define CONFIG_PXA_MMC_GENERIC
57
58#define CONFIG_CMD_FAT
59#define CONFIG_CMD_EXT2
60#define CONFIG_DOS_PARTITION
61#endif
62
63/*
64 * LCD
65 */
66#ifdef CONFIG_LCD
67#define CONFIG_PXA_LCD
68#define CONFIG_ACX544AKN
69#define CONFIG_LCD_LOGO
70#define CONFIG_SYS_LCD_PXA_NO_L_BIAS /* don't configure GPIO77 as L_BIAS */
71#define LCD_BPP LCD_COLOR16
72#define CONFIG_FB_ADDR 0x5c000000 /* internal SRAM */
73#define CONFIG_CMD_BMP
74#define CONFIG_SPLASH_SCREEN /* requires "splashimage" env var */
75#define CONFIG_SPLASH_SCREEN_ALIGN /* requires "splashpos" env var */
76#define CONFIG_VIDEO_BMP_GZIP
77#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
78
79#endif
80
81/*
82 * KGDB
83 */
84#ifdef CONFIG_CMD_KGDB
85#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
Mike Dunn0dc0e842013-06-18 11:08:50 -070086#endif
87
88/*
89 * HUSH Shell Configuration
90 */
91#define CONFIG_SYS_HUSH_PARSER 1
92#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
93
94#define CONFIG_SYS_LONGHELP
95#ifdef CONFIG_SYS_HUSH_PARSER
96#define CONFIG_SYS_PROMPT "$ "
97#else
Mike Dunn0dc0e842013-06-18 11:08:50 -070098#endif
99#define CONFIG_SYS_CBSIZE 256
100#define CONFIG_SYS_PBSIZE \
101 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
102#define CONFIG_SYS_MAXARGS 16
103#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
104#define CONFIG_SYS_DEVICE_NULLDEV 1
105
106/*
107 * Clock Configuration
108 */
Mike Dunn0dc0e842013-06-18 11:08:50 -0700109#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
110
111/*
112 * Stack sizes
113 */
114#define CONFIG_STACKSIZE (128*1024) /* regular stack */
115#ifdef CONFIG_USE_IRQ
116#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
117#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
118#endif
119
120/*
121 * DRAM Map
122 */
123#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
124#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
125#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
126
127#define CONFIG_SYS_DRAM_BASE 0xa0000000
128#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
129
130#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
131#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
132#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
133#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
134
135/*
136 * GPIO settings
137 */
138#define CONFIG_SYS_GAFR0_L_VAL 0x0E000000
139#define CONFIG_SYS_GAFR0_U_VAL 0xA500001A
140#define CONFIG_SYS_GAFR1_L_VAL 0x60000002
141#define CONFIG_SYS_GAFR1_U_VAL 0xAAA07959
142#define CONFIG_SYS_GAFR2_L_VAL 0x02AAAAAA
143#define CONFIG_SYS_GAFR2_U_VAL 0x41440F08
144#define CONFIG_SYS_GAFR3_L_VAL 0x56AA95FF
145#define CONFIG_SYS_GAFR3_U_VAL 0x00001401
146#define CONFIG_SYS_GPCR0_VAL 0x1FF80400
147#define CONFIG_SYS_GPCR1_VAL 0x03003FC1
148#define CONFIG_SYS_GPCR2_VAL 0x01C1E000
149#define CONFIG_SYS_GPCR3_VAL 0x01C1E000
150#define CONFIG_SYS_GPDR0_VAL 0xCFF90400
151#define CONFIG_SYS_GPDR1_VAL 0xFB22BFC1
152#define CONFIG_SYS_GPDR2_VAL 0x93CDFFDF
153#define CONFIG_SYS_GPDR3_VAL 0x0069FF81
154#define CONFIG_SYS_GPSR0_VAL 0x02000018
155#define CONFIG_SYS_GPSR1_VAL 0x00000000
156#define CONFIG_SYS_GPSR2_VAL 0x000C0000
157#define CONFIG_SYS_GPSR3_VAL 0x00080000
158
159#define CONFIG_SYS_PSSR_VAL 0x30
160
161/*
162 * Clock settings
163 */
164#define CONFIG_SYS_CKEN 0x01ffffff
165#define CONFIG_SYS_CCCR 0x02000210
166
167/*
168 * Memory settings
169 */
170#define CONFIG_SYS_MSC0_VAL 0x7ff844c8
171#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4
172#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
173#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd
174#define CONFIG_SYS_MDREFR_VAL 0x201fa031
175#define CONFIG_SYS_MDMRS_VAL 0x00320032
176#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
177#define CONFIG_SYS_SXCNFG_VAL 0x40044004
178#define CONFIG_SYS_MECR_VAL 0x00000003
179#define CONFIG_SYS_MCMEM0_VAL 0x0001c391
180#define CONFIG_SYS_MCMEM1_VAL 0x0001c391
181#define CONFIG_SYS_MCATT0_VAL 0x0001c391
182#define CONFIG_SYS_MCATT1_VAL 0x0001c391
183#define CONFIG_SYS_MCIO0_VAL 0x00014611
184#define CONFIG_SYS_MCIO1_VAL 0x0001c391
185
186/*
187 * USB
188 */
189#define CONFIG_USB_DEVICE
190#define CONFIG_USB_TTY
191#define CONFIG_USB_DEV_PULLUP_GPIO 114
192
193/*
194 * SPL
195 */
Mike Dunn0dc0e842013-06-18 11:08:50 -0700196#define CONFIG_SPL_TEXT_BASE 0xa1700000 /* IPL loads SPL here */
197#define CONFIG_SPL_STACK 0x5c040000 /* end of internal SRAM */
198#define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */
199#define CONFIG_SPL_NAND_DOCG4 /* use lean docg4 nand spl driver */
200#define CONFIG_SPL_LIBGENERIC_SUPPORT /* spl uses memcpy */
201
202/*
203 * NAND
204 */
205#define CONFIG_NAND_DOCG4
206#define CONFIG_SYS_NAND_SELF_INIT
207#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */
208#define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */
209#define CONFIG_SYS_NAND_PAGE_SIZE 0x200
210#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
211#define CONFIG_BITREVERSE /* needed by docg4 driver */
212#define CONFIG_BCH /* needed by docg4 driver */
213
214/*
215 * IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image. It
216 * will be rounded up to the next 64k boundary (the spl flash block size), so it
217 * does not have to be exact, but you must ensure that it is not less than the
218 * actual image size, or it may fail to boot (bricked phone)!
219 * (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.)
220*/
221#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */
222
223/*
224 * This is the byte offset into the flash at which the concatenated spl + u-boot
225 * image is placed. It must be at the start of a block (256k boundary). Blocks
226 * 0 - 5 are write-protected, so we start at block 6.
227 */
228#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000 /* block 6 */
229
230/* DRAM address to which u-boot proper is loaded (before it relocates itself) */
231#define CONFIG_SYS_NAND_U_BOOT_DST 0xa0000000
232#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
233
234/* passed to linker by Makefile as arg to -Ttext option */
235#define CONFIG_SYS_TEXT_BASE 0xa0000000
236
237#define CONFIG_SYS_INIT_SP_ADDR 0x5c040000 /* end of internal SRAM */
238
239/*
240 * environment
241 */
242#define CONFIG_ENV_IS_NOWHERE
243#define CONFIG_BUILD_ENVCRC
244#define CONFIG_ENV_SIZE 0x200
245#define CONFIG_SYS_CONSOLE_IS_IN_ENV
246#define CONFIG_EXTRA_ENV_SETTINGS \
247 "stdin=usbtty\0" \
248 "stdout=usbtty\0" \
249 "stderr=usbtty"
250#define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \
251ip=192.168.11.102:::255.255.255.0:treo:usb0"
252#define CONFIG_BOOTDELAY 3
253
254#if 0 /* example: try 2nd mmc partition, then nand */
255#define CONFIG_BOOTCOMMAND \
256 "mmc rescan; " \
257 "if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then " \
258 "bootm 0xa1000000; " \
259 "elif nand read 0xa1000000 0x280000 0x240000; then " \
260 "bootm 0xa1000000; " \
261 "fi; "
262#endif
263
264/* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */
265#define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000
266
267#define CONFIG_SYS_DCACHE_OFF
268#define CONFIG_SYS_ICACHE_OFF
269
270#endif /* __CONFIG_H */