blob: d90eed48f7858c177da2507dcdde422bb6c2fdb7 [file] [log] [blame]
Ian Campbell58358232014-05-05 11:52:28 +01001#include <common.h>
2#include <netdev.h>
3#include <miiphy.h>
4#include <asm/gpio.h>
5#include <asm/io.h>
6#include <asm/arch/clock.h>
7#include <asm/arch/gpio.h>
8
9int sunxi_gmac_initialize(bd_t *bis)
10{
11 int pin;
12 struct sunxi_ccm_reg *const ccm =
13 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
14
15 /* Set up clock gating */
Hans de Goedeeafec322014-11-21 17:19:45 +010016#ifndef CONFIG_MACH_SUN6I
Ian Campbell58358232014-05-05 11:52:28 +010017 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010018#else
19 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
20 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
21#endif
Ian Campbell58358232014-05-05 11:52:28 +010022
23 /* Set MII clock */
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020024#ifdef CONFIG_RGMII
Ian Campbell58358232014-05-05 11:52:28 +010025 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
26 CCM_GMAC_CTRL_GPIT_RGMII);
Hans de Goedec13f60d2015-01-25 12:10:48 +010027 setbits_le32(&ccm->gmac_clk_cfg,
28 CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020029#else
30 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
31 CCM_GMAC_CTRL_GPIT_MII);
32#endif
Ian Campbell58358232014-05-05 11:52:28 +010033
Hans de Goedeeafec322014-11-21 17:19:45 +010034#ifndef CONFIG_MACH_SUN6I
Ian Campbell58358232014-05-05 11:52:28 +010035 /* Configure pin mux settings for GMAC */
36 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020037#ifdef CONFIG_RGMII
Ian Campbell58358232014-05-05 11:52:28 +010038 /* skip unused pins in RGMII mode */
39 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
40 continue;
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020041#endif
Paul Kocialkowski487b3272015-03-22 18:12:22 +010042 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
Ian Campbell58358232014-05-05 11:52:28 +010043 sunxi_gpio_set_drv(pin, 3);
44 }
Hans de Goedeeafec322014-11-21 17:19:45 +010045#elif defined CONFIG_RGMII
46 /* Configure sun6i RGMII mode pin mux settings */
47 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +010048 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010049 sunxi_gpio_set_drv(pin, 3);
50 }
51 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +010052 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010053 sunxi_gpio_set_drv(pin, 3);
54 }
55 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +010056 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010057 sunxi_gpio_set_drv(pin, 3);
58 }
59 for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +010060 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010061 sunxi_gpio_set_drv(pin, 3);
62 }
63#elif defined CONFIG_GMII
64 /* Configure sun6i GMII mode pin mux settings */
65 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +010066 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010067 sunxi_gpio_set_drv(pin, 2);
68 }
69#else
70 /* Configure sun6i MII mode pin mux settings */
71 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010072 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010073 for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010074 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010075 for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010076 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010077 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010078 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010079 for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010080 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goedeeafec322014-11-21 17:19:45 +010081#endif
Ian Campbell58358232014-05-05 11:52:28 +010082
Simon Glass5b4c6f22015-04-05 16:07:42 -060083#ifdef CONFIG_DM_ETH
84 return 0;
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020085#else
Simon Glass5b4c6f22015-04-05 16:07:42 -060086# ifdef CONFIG_RGMII
87 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
88# elif defined CONFIG_GMII
89 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
90# else
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020091 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
Simon Glass5b4c6f22015-04-05 16:07:42 -060092# endif
Chen-Yu Tsaief7e7232014-06-09 11:37:01 +020093#endif
Ian Campbell58358232014-05-05 11:52:28 +010094}