| Tom Warren | d0edce4 | 2013-03-25 16:22:26 -0700 | [diff] [blame] | 1 | /* |
| Tom Warren | 2f5dac9 | 2014-01-24 12:46:16 -0700 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. |
| Tom Warren | d0edce4 | 2013-03-25 16:22:26 -0700 | [diff] [blame] | 3 | * |
| Tom Rini | 5b8031c | 2016-01-14 22:05:13 -0500 | [diff] [blame^] | 4 | * SPDX-License-Identifier: GPL-2.0 |
| Tom Warren | d0edce4 | 2013-03-25 16:22:26 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* Tegra cache routines */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <asm/io.h> |
| 11 | #include <asm/arch-tegra/ap.h> |
| 12 | #include <asm/arch/gp_padctrl.h> |
| 13 | |
| Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 14 | #ifndef CONFIG_ARM64 |
| Tom Warren | d0edce4 | 2013-03-25 16:22:26 -0700 | [diff] [blame] | 15 | void config_cache(void) |
| 16 | { |
| Tom Warren | d0edce4 | 2013-03-25 16:22:26 -0700 | [diff] [blame] | 17 | u32 reg = 0; |
| 18 | |
| 19 | /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ |
| 20 | asm volatile( |
| 21 | "mrc p15, 0, r0, c1, c0, 1\n" |
| 22 | "orr r0, r0, #0x41\n" |
| 23 | "mcr p15, 0, r0, c1, c0, 1\n"); |
| 24 | |
| Tom Warren | 2f5dac9 | 2014-01-24 12:46:16 -0700 | [diff] [blame] | 25 | /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */ |
| 26 | if (tegra_get_chip() < CHIPID_TEGRA114) |
| Tom Warren | d0edce4 | 2013-03-25 16:22:26 -0700 | [diff] [blame] | 27 | return; |
| Tom Warren | 2f5dac9 | 2014-01-24 12:46:16 -0700 | [diff] [blame] | 28 | |
| Tom Warren | d0edce4 | 2013-03-25 16:22:26 -0700 | [diff] [blame] | 29 | /* |
| 30 | * Systems with an architectural L2 cache must not use the PL310. |
| 31 | * Config L2CTLR here for a data RAM latency of 3 cycles. |
| 32 | */ |
| 33 | asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); |
| 34 | reg &= ~7; |
| 35 | reg |= 2; |
| 36 | asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); |
| 37 | } |
| Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 38 | #endif |