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Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +09001/*
2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board
3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __SH7785LCR_H
26#define __SH7785LCR_H
27
28#undef DEBUG
29#define CONFIG_SH 1
30#define CONFIG_SH4A 1
31#define CONFIG_CPU_SH7785 1
32#define CONFIG_SH7785LCR 1
33
34#define CONFIG_CMD_FLASH
35#define CONFIG_CMD_MEMORY
36#define CONFIG_CMD_PCI
37#define CONFIG_CMD_NET
38#define CONFIG_CMD_PING
39#define CONFIG_CMD_NFS
40#define CONFIG_CMD_DFL
41#define CONFIG_CMD_SDRAM
42#define CONFIG_CMD_RUN
Mike Frysingerbdab39d2009-01-28 19:08:14 -050043#define CONFIG_CMD_SAVEENV
Nobuhiro Iwamatsu93752532010-12-08 14:00:24 +090044#define CONFIG_CMD_SH_ZIMAGEBOOT
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090045
46#define CONFIG_CMD_USB
47#define CONFIG_USB_STORAGE
48#define CONFIG_CMD_EXT2
49#define CONFIG_CMD_FAT
50#define CONFIG_DOS_PARTITION
51#define CONFIG_MAC_PARTITION
52
53#define CONFIG_BAUDRATE 115200
54#define CONFIG_BOOTDELAY 3
55#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
56
57#define CONFIG_EXTRA_ENV_SETTINGS \
58 "bootdevice=0:1\0" \
59 "usbload=usb reset;usbboot;usb stop;bootm\0"
60
61#define CONFIG_VERSION_VARIABLE
62#undef CONFIG_SHOW_BOOT_PROGRESS
63
64/* MEMORY */
Yoshihiro Shimodaada93182009-03-03 15:11:17 +090065#if defined(CONFIG_SH_32BIT)
Nobuhiro Iwamatsu59272c62011-01-17 21:02:16 +090066#define CONFIG_SYS_TEXT_BASE 0x8FF80000
Nobuhiro Iwamatsu915d6b72010-10-05 16:58:05 +090067/* 0x40000000 - 0x47FFFFFF does not use */
68#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
69#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
70#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
Yoshihiro Shimodaada93182009-03-03 15:11:17 +090071#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
72#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
73#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
74#define SH7785LCR_USB_BASE (0xa6000000)
75#else
Nobuhiro Iwamatsu59272c62011-01-17 21:02:16 +090076#define CONFIG_SYS_TEXT_BASE 0x0FF80000
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090077#define SH7785LCR_SDRAM_BASE (0x08000000)
78#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
79#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
80#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
81#define SH7785LCR_USB_BASE (0xb4000000)
Yoshihiro Shimodaada93182009-03-03 15:11:17 +090082#endif
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_LONGHELP
85#define CONFIG_SYS_PROMPT "=> "
86#define CONFIG_SYS_CBSIZE 256
87#define CONFIG_SYS_PBSIZE 256
88#define CONFIG_SYS_MAXARGS 16
89#define CONFIG_SYS_BARGSIZE 512
90#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090091
92/* SCIF */
Nobuhiro Iwamatsu1c981722008-08-28 14:53:31 +090093#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090094#define CONFIG_CONS_SCIF1 1
95#define CONFIG_SCIF_EXT_CLOCK 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#undef CONFIG_SYS_CONSOLE_INFO_QUIET
97#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
98#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090099
100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
102#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900103 (SH7785LCR_SDRAM_SIZE) - \
104 4 * 1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#undef CONFIG_SYS_ALT_MEMTEST
106#undef CONFIG_SYS_MEMTEST_SCRATCH
107#undef CONFIG_SYS_LOADS_BAUD_CHANGE
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
110#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
111#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
114#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
115#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900117
118/* FLASH */
Nobuhiro Iwamatsu1c981722008-08-28 14:53:31 +0900119#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_CFI
121#undef CONFIG_SYS_FLASH_QUIET_TEST
122#define CONFIG_SYS_FLASH_EMPTY_INFO
123#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
124#define CONFIG_SYS_MAX_FLASH_SECT 512
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_MAX_FLASH_BANKS 1
127#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900128 (0 * SH7785LCR_FLASH_BANK_SIZE) }
129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
131#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
132#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
133#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#undef CONFIG_SYS_FLASH_PROTECTION
136#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900137
138/* R8A66597 */
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900139#define CONFIG_USB_R8A66597_HCD
140#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
141#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
142#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
143#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
144
145/* PCI Controller */
146#define CONFIG_PCI
147#define CONFIG_SH4_PCI
148#define CONFIG_SH7780_PCI
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900149#if defined(CONFIG_SH_32BIT)
150#define CONFIG_SH7780_PCI_LSR 0x1ff00001
151#define CONFIG_SH7780_PCI_LAR 0x5f000000
152#define CONFIG_SH7780_PCI_BAR 0x5f000000
153#else
Yoshihiro Shimoda06b18162009-02-25 14:26:42 +0900154#define CONFIG_SH7780_PCI_LSR 0x07f00001
155#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
156#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900157#endif
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900158#define CONFIG_PCI_PNP
159#define CONFIG_PCI_SCAN_SHOW 1
160
161#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
162#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
163#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
164
165#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
166#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
167#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
168
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900169#if defined(CONFIG_SH_32BIT)
170#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
171#else
Yoshihiro Shimodab3061b42009-02-25 14:26:55 +0900172#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900173#endif
174#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
Yoshihiro Shimodab3061b42009-02-25 14:26:55 +0900175#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
176
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900177/* Network device (RTL8169) support */
178#define CONFIG_NET_MULTI
179#define CONFIG_RTL8169
180
181/* ENV setting */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200182#define CONFIG_ENV_IS_IN_FLASH
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900183#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200184#define CONFIG_ENV_SECT_SIZE (256 * 1024)
185#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
187#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200188#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900189
190/* Board Clock */
191/* The SCIF used external clock. system clock only used timer. */
192#define CONFIG_SYS_CLK_FREQ 50000000
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +0200193#define CONFIG_SYS_TMU_CLK_DIV 4
Jean-Christophe PLAGNIOL-VILLARD8dd29c82009-06-04 12:06:47 +0200194#define CONFIG_SYS_HZ 1000
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900195
196#endif /* __SH7785LCR_H */