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wdenk03f5c552004-10-10 21:21:55 +00001/*
chenhui zhao568336e2011-09-15 14:52:34 +08002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk03f5c552004-10-10 21:21:55 +00003 *
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk03f5c552004-10-10 21:21:55 +00007 */
8
wdenk03f5c552004-10-10 21:21:55 +00009#include <common.h>
10#include <pci.h>
11#include <asm/processor.h>
Jon Loeligeraa11d852008-03-17 15:48:18 -050012#include <asm/mmu.h>
wdenk03f5c552004-10-10 21:21:55 +000013#include <asm/immap_85xx.h>
York Sun5614e712013-09-30 09:22:09 -070014#include <fsl_ddr_sdram.h>
Wolfgang Denk2d5df632005-07-21 16:14:36 +020015#include <ioports.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060016#include <spd_sdram.h>
Kumar Galab90d2542007-11-29 00:11:44 -060017#include <libfdt.h>
18#include <fdt_support.h>
wdenk03f5c552004-10-10 21:21:55 +000019
20#include "../common/cadmus.h"
21#include "../common/eeprom.h"
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -050022#include "../common/via.h"
wdenk03f5c552004-10-10 21:21:55 +000023
Jon Loeligerd9b94f22005-07-25 14:05:07 -050024#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk03f5c552004-10-10 21:21:55 +000025extern void ddr_enable_ecc(unsigned int dram_size);
26#endif
27
wdenk03f5c552004-10-10 21:21:55 +000028void local_bus_init(void);
wdenk03f5c552004-10-10 21:21:55 +000029
Wolfgang Denk2d5df632005-07-21 16:14:36 +020030/*
31 * I/O Port configuration table
32 *
33 * if conf is 1, then that port pin will be configured at boot time
34 * according to the five values podr/pdir/ppar/psor/pdat for that entry
35 */
36
37const iop_conf_t iop_conf_tab[4][32] = {
38
39 /* Port A configuration */
40 { /* conf ppar psor pdir podr pdat */
41 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
42 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
43 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
44 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
45 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
46 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
47 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
48 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
49 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
50 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
51 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
52 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
53 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
54 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
55 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
56 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
57 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
58 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
59 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
60 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
61 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
62 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
63 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
64 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
65 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
66 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
67 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
68 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
69 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
70 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
71 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
72 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
73 },
74
75 /* Port B configuration */
76 { /* conf ppar psor pdir podr pdat */
77 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
78 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
79 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
80 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
81 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
82 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
83 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
84 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
85 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
86 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
87 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
88 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
89 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
90 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
91 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
92 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
93 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
94 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
95 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
96 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
97 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
98 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
99 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
100 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
101 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
102 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
103 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
104 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
105 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
106 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
107 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
108 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
109 },
110
111 /* Port C */
112 { /* conf ppar psor pdir podr pdat */
113 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
114 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
115 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
116 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
117 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
118 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
119 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
120 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
121 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
122 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
123 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
124 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
125 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
126 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
127 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
128 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
129 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
130 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
131 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
132 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
133 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
134 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
135 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
136 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
137 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
138 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
139 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
140 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
141 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
142 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
143 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
144 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
145 },
146
147 /* Port D */
148 { /* conf ppar psor pdir podr pdat */
149 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
150 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
151 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
152 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
153 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
154 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
155 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
156 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
157 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
158 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
159 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
160 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
161 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
162 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
163 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
164 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
165 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
166 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
167 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
168 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
169 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
170 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
171 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
172 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
173 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
174 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
175 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
176 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
177 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
178 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
179 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
180 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
181 }
182};
183
wdenk5c952cf2004-10-10 21:27:30 +0000184int checkboard (void)
wdenk03f5c552004-10-10 21:21:55 +0000185{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
chenhui zhao568336e2011-09-15 14:52:34 +0800187 char buf[32];
wdenk03f5c552004-10-10 21:21:55 +0000188
wdenk5c952cf2004-10-10 21:27:30 +0000189 /* PCI slot in USER bits CSR[6:7] by convention. */
190 uint pci_slot = get_pci_slot ();
wdenk03f5c552004-10-10 21:21:55 +0000191
wdenk5c952cf2004-10-10 21:27:30 +0000192 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
193 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
194 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
195 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
wdenk03f5c552004-10-10 21:21:55 +0000196
wdenk5c952cf2004-10-10 21:27:30 +0000197 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
wdenk03f5c552004-10-10 21:21:55 +0000198
wdenk5c952cf2004-10-10 21:27:30 +0000199 uint cpu_board_rev = get_cpu_board_revision ();
wdenk03f5c552004-10-10 21:21:55 +0000200
wdenk5c952cf2004-10-10 21:27:30 +0000201 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
202 get_board_version (), pci_slot);
wdenk03f5c552004-10-10 21:21:55 +0000203
wdenk5c952cf2004-10-10 21:27:30 +0000204 printf ("CPU Board Revision %d.%d (0x%04x)\n",
205 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
206 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
wdenk03f5c552004-10-10 21:21:55 +0000207
Peter Tyser8ca78f22010-10-29 17:59:24 -0500208 printf("PCI1: %d bit, %s MHz, %s\n",
wdenk5c952cf2004-10-10 21:27:30 +0000209 (pci1_32) ? 32 : 64,
chenhui zhao568336e2011-09-15 14:52:34 +0800210 strmhz(buf, pci1_speed),
wdenk5c952cf2004-10-10 21:27:30 +0000211 pci1_clk_sel ? "sync" : "async");
wdenk03f5c552004-10-10 21:21:55 +0000212
wdenk5c952cf2004-10-10 21:27:30 +0000213 if (pci_dual) {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500214 printf("PCI2: 32 bit, 66 MHz, %s\n",
wdenk5c952cf2004-10-10 21:27:30 +0000215 pci2_clk_sel ? "sync" : "async");
216 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500217 printf("PCI2: disabled\n");
wdenk5c952cf2004-10-10 21:27:30 +0000218 }
wdenk03f5c552004-10-10 21:21:55 +0000219
wdenk5c952cf2004-10-10 21:27:30 +0000220 /*
221 * Initialize local bus.
222 */
223 local_bus_init ();
wdenk03f5c552004-10-10 21:21:55 +0000224
wdenk5c952cf2004-10-10 21:27:30 +0000225 return 0;
wdenk03f5c552004-10-10 21:21:55 +0000226}
227
wdenk03f5c552004-10-10 21:21:55 +0000228/*
229 * Initialize Local Bus
230 */
wdenk03f5c552004-10-10 21:21:55 +0000231void
232local_bus_init(void)
233{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -0500235 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
wdenk03f5c552004-10-10 21:21:55 +0000236
237 uint clkdiv;
238 uint lbc_hz;
239 sys_info_t sysinfo;
240 uint temp_lbcdll;
241
242 /*
243 * Errata LBC11.
244 * Fix Local Bus clock glitch when DLL is enabled.
245 *
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200246 * If localbus freq is < 66MHz, DLL bypass mode must be used.
247 * If localbus freq is > 133MHz, DLL can be safely enabled.
wdenk03f5c552004-10-10 21:21:55 +0000248 * Between 66 and 133, the DLL is enabled with an override workaround.
249 */
250
251 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800252 clkdiv = lbc->lcrr & LCRR_CLKDIV;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530253 lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
wdenk03f5c552004-10-10 21:21:55 +0000254
255 if (lbc_hz < 66) {
Paul Gortmakera2af6a72012-08-13 13:48:57 +0000256 lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
wdenk03f5c552004-10-10 21:21:55 +0000257
258 } else if (lbc_hz >= 133) {
Paul Gortmakera2af6a72012-08-13 13:48:57 +0000259 lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
wdenk03f5c552004-10-10 21:21:55 +0000260
261 } else {
Paul Gortmakera2af6a72012-08-13 13:48:57 +0000262 lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
wdenk03f5c552004-10-10 21:21:55 +0000263 udelay(200);
264
265 /*
266 * Sample LBC DLL ctrl reg, upshift it to set the
267 * override bits.
268 */
269 temp_lbcdll = gur->lbcdllcr;
270 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
271 asm("sync;isync;msync");
272 }
273}
274
wdenk03f5c552004-10-10 21:21:55 +0000275/*
276 * Initialize SDRAM memory on the Local Bus.
277 */
Becky Bruce70961ba2010-12-17 17:17:57 -0600278void lbc_sdram_init(void)
wdenk03f5c552004-10-10 21:21:55 +0000279{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
wdenk03f5c552004-10-10 21:21:55 +0000281
282 uint idx;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500283 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
wdenk03f5c552004-10-10 21:21:55 +0000285 uint cpu_board_rev;
286 uint lsdmr_common;
287
Becky Bruce7ea38712010-12-17 17:17:59 -0600288 puts("LBC SDRAM: ");
289 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
290 "\n ");
wdenk03f5c552004-10-10 21:21:55 +0000291
292 /*
293 * Setup SDRAM Base and Option Registers
294 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500295 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
296 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
wdenk03f5c552004-10-10 21:21:55 +0000298 asm("msync");
299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
301 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
wdenk03f5c552004-10-10 21:21:55 +0000302 asm("msync");
303
304 /*
305 * Determine which address lines to use baed on CPU board rev.
306 */
307 cpu_board_rev = get_cpu_board_revision();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
wdenk03f5c552004-10-10 21:21:55 +0000309 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500310 lsdmr_common |= LSDMR_BSMA1617;
wdenk03f5c552004-10-10 21:21:55 +0000311 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500312 lsdmr_common |= LSDMR_BSMA1516;
wdenk03f5c552004-10-10 21:21:55 +0000313 } else {
314 /*
315 * Assume something unable to identify itself is
316 * really old, and likely has lines 16/17 mapped.
317 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500318 lsdmr_common |= LSDMR_BSMA1617;
wdenk03f5c552004-10-10 21:21:55 +0000319 }
320
321 /*
322 * Issue PRECHARGE ALL command.
323 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500324 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
wdenk03f5c552004-10-10 21:21:55 +0000325 asm("sync;msync");
326 *sdram_addr = 0xff;
327 ppcDcbf((unsigned long) sdram_addr);
328 udelay(100);
329
330 /*
331 * Issue 8 AUTO REFRESH commands.
332 */
333 for (idx = 0; idx < 8; idx++) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500334 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
wdenk03f5c552004-10-10 21:21:55 +0000335 asm("sync;msync");
336 *sdram_addr = 0xff;
337 ppcDcbf((unsigned long) sdram_addr);
338 udelay(100);
339 }
340
341 /*
342 * Issue 8 MODE-set command.
343 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500344 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
wdenk03f5c552004-10-10 21:21:55 +0000345 asm("sync;msync");
346 *sdram_addr = 0xff;
347 ppcDcbf((unsigned long) sdram_addr);
348 udelay(100);
349
350 /*
351 * Issue NORMAL OP command.
352 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500353 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
wdenk03f5c552004-10-10 21:21:55 +0000354 asm("sync;msync");
355 *sdram_addr = 0xff;
356 ppcDcbf((unsigned long) sdram_addr);
357 udelay(200); /* Overkill. Must wait > 200 bus cycles */
358
359#endif /* enable SDRAM init */
360}
361
wdenk03f5c552004-10-10 21:21:55 +0000362#if defined(CONFIG_PCI)
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500363/* For some reason the Tundra PCI bridge shows up on itself as a
364 * different device. Work around that by refusing to configure it.
wdenk03f5c552004-10-10 21:21:55 +0000365 */
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500366void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
wdenk03f5c552004-10-10 21:21:55 +0000367
wdenk03f5c552004-10-10 21:21:55 +0000368static struct pci_config_table pci_mpc85xxcds_config_table[] = {
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500369 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700370 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
371 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
Andy Flemingffa621a2007-02-24 01:08:13 -0600372 mpc85xx_config_via_usbide, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700373 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
374 mpc85xx_config_via_usb, {0,0,0}},
375 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
376 mpc85xx_config_via_usb2, {0,0,0}},
377 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
Andy Flemingffa621a2007-02-24 01:08:13 -0600378 mpc85xx_config_via_power, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700379 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
380 mpc85xx_config_via_ac97, {0,0,0}},
Andy Flemingffa621a2007-02-24 01:08:13 -0600381 {},
wdenk03f5c552004-10-10 21:21:55 +0000382};
wdenk03f5c552004-10-10 21:21:55 +0000383
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500384static struct pci_controller hose[] = {
385 { config_table: pci_mpc85xxcds_config_table,},
386#ifdef CONFIG_MPC85XX_PCI2
387 {},
wdenk03f5c552004-10-10 21:21:55 +0000388#endif
389};
390
391#endif /* CONFIG_PCI */
392
wdenk03f5c552004-10-10 21:21:55 +0000393void
394pci_init_board(void)
395{
396#ifdef CONFIG_PCI
Matthew McClintock7376eb82006-10-11 15:13:01 -0500397 pci_mpc85xx_init(hose);
wdenk03f5c552004-10-10 21:21:55 +0000398#endif
399}
Kumar Galab90d2542007-11-29 00:11:44 -0600400
401#if defined(CONFIG_OF_BOARD_SETUP)
402void
403ft_pci_setup(void *blob, bd_t *bd)
404{
405 int node, tmp[2];
406 const char *path;
407
408 node = fdt_path_offset(blob, "/aliases");
409 tmp[0] = 0;
410 if (node >= 0) {
411#ifdef CONFIG_PCI1
412 path = fdt_getprop(blob, node, "pci0", NULL);
413 if (path) {
414 tmp[1] = hose[0].last_busno - hose[0].first_busno;
415 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
416 }
417#endif
418#ifdef CONFIG_MPC85XX_PCI2
419 path = fdt_getprop(blob, node, "pci1", NULL);
420 if (path) {
421 tmp[1] = hose[1].last_busno - hose[1].first_busno;
422 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
423 }
424#endif
425 }
426}
427#endif