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Priyanka Jain062ef1a2013-10-18 17:19:06 +05301/*
vijay raif4c39172014-03-31 11:46:34 +05302+ * Copyright 2014 Freescale Semiconductor, Inc.
3+ *
4+ * SPDX-License-Identifier: GPL-2.0+
5+ */
Priyanka Jain062ef1a2013-10-18 17:19:06 +05306
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10/*
vijay raif4c39172014-03-31 11:46:34 +053011 * T104x RDB board configuration file
Priyanka Jain062ef1a2013-10-18 17:19:06 +053012 */
13#define CONFIG_T104xRDB
Priyanka Jain062ef1a2013-10-18 17:19:06 +053014#define CONFIG_PHYS_64BIT
vijay rai2aea6612014-11-18 12:21:13 +053015#define CONFIG_SYS_GENERIC_BOARD
16#define CONFIG_DISPLAY_BOARDINFO
Priyanka Jain062ef1a2013-10-18 17:19:06 +053017
Prabhakar Kushwaha9f074e62014-10-29 22:33:09 +053018#define CONFIG_E500 /* BOOKE e500 family */
19#include <asm/config_mpc85xx.h>
20
Priyanka Jain062ef1a2013-10-18 17:19:06 +053021#ifdef CONFIG_RAMBOOT_PBL
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053022#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
23#ifdef CONFIG_T1040RDB
24#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
25#endif
26#ifdef CONFIG_T1042RDB_PI
vijay raid087e0e2014-07-23 18:25:47 +053027#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
28#endif
29#ifdef CONFIG_T1042RDB
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053030#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
31#endif
32
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053033#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
34#define CONFIG_SPL_ENV_SUPPORT
35#define CONFIG_SPL_SERIAL_SUPPORT
36#define CONFIG_SPL_FLUSH_IMAGE
37#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
38#define CONFIG_SPL_LIBGENERIC_SUPPORT
39#define CONFIG_SPL_LIBCOMMON_SUPPORT
40#define CONFIG_SPL_I2C_SUPPORT
41#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
42#define CONFIG_FSL_LAW /* Use common FSL init code */
Tang Yuantiance249d92014-07-23 17:27:53 +080043#define CONFIG_SYS_TEXT_BASE 0x30001000
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053044#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
45#define CONFIG_SPL_PAD_TO 0x40000
46#define CONFIG_SPL_MAX_SIZE 0x28000
47#ifdef CONFIG_SPL_BUILD
48#define CONFIG_SPL_SKIP_RELOCATE
49#define CONFIG_SPL_COMMON_INIT_DDR
50#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
51#define CONFIG_SYS_NO_FLASH
52#endif
53#define RESET_VECTOR_OFFSET 0x27FFC
54#define BOOT_PAGE_OFFSET 0x27000
55
56#ifdef CONFIG_NAND
57#define CONFIG_SPL_NAND_SUPPORT
58#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
Tang Yuantiance249d92014-07-23 17:27:53 +080059#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
60#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053061#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
62#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
63#define CONFIG_SPL_NAND_BOOT
64#endif
65
66#ifdef CONFIG_SPIFLASH
Tang Yuantiance249d92014-07-23 17:27:53 +080067#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053068#define CONFIG_SPL_SPI_SUPPORT
69#define CONFIG_SPL_SPI_FLASH_SUPPORT
70#define CONFIG_SPL_SPI_FLASH_MINIMAL
71#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
Tang Yuantiance249d92014-07-23 17:27:53 +080072#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
73#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053074#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
75#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
76#ifndef CONFIG_SPL_BUILD
77#define CONFIG_SYS_MPC85XX_NO_RESETVEC
78#endif
79#define CONFIG_SPL_SPI_BOOT
80#endif
81
82#ifdef CONFIG_SDCARD
Tang Yuantiance249d92014-07-23 17:27:53 +080083#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053084#define CONFIG_SPL_MMC_SUPPORT
85#define CONFIG_SPL_MMC_MINIMAL
86#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
Tang Yuantiance249d92014-07-23 17:27:53 +080087#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
88#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053089#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
90#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
91#ifndef CONFIG_SPL_BUILD
92#define CONFIG_SYS_MPC85XX_NO_RESETVEC
93#endif
94#define CONFIG_SPL_MMC_BOOT
95#endif
96
Priyanka Jain062ef1a2013-10-18 17:19:06 +053097#endif
98
99/* High Level Configuration Options */
100#define CONFIG_BOOKE
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530101#define CONFIG_E500MC /* BOOKE e500mc family */
102#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530103#define CONFIG_MP /* support multiple processors */
104
Tang Yuantian5303a3d2014-04-17 15:33:45 +0800105/* support deep sleep */
106#define CONFIG_DEEP_SLEEP
Tang Yuantian00233522014-11-21 11:17:16 +0800107#if defined(CONFIG_DEEP_SLEEP)
108#define CONFIG_BOARD_EARLY_INIT_F
Tang Yuantian5303a3d2014-04-17 15:33:45 +0800109#define CONFIG_SILENT_CONSOLE
Tang Yuantian00233522014-11-21 11:17:16 +0800110#endif
Tang Yuantian5303a3d2014-04-17 15:33:45 +0800111
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530112#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530113#define CONFIG_SYS_TEXT_BASE 0xeff40000
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530114#endif
115
116#ifndef CONFIG_RESET_VECTOR_ADDRESS
117#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
118#endif
119
120#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
121#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
122#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +0530123#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530124#define CONFIG_PCI /* Enable PCI/PCIE */
125#define CONFIG_PCI_INDIRECT_BRIDGE
126#define CONFIG_PCIE1 /* PCIE controler 1 */
127#define CONFIG_PCIE2 /* PCIE controler 2 */
128#define CONFIG_PCIE3 /* PCIE controler 3 */
129#define CONFIG_PCIE4 /* PCIE controler 4 */
130
131#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
132#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
133
134#define CONFIG_FSL_LAW /* Use common FSL init code */
135
136#define CONFIG_ENV_OVERWRITE
137
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530138#ifndef CONFIG_SYS_NO_FLASH
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530139#define CONFIG_FLASH_CFI_DRIVER
140#define CONFIG_SYS_FLASH_CFI
141#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
142#endif
143
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530144#if defined(CONFIG_SPIFLASH)
145#define CONFIG_SYS_EXTRA_ENV_RELOC
146#define CONFIG_ENV_IS_IN_SPI_FLASH
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530147#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
148#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
149#define CONFIG_ENV_SECT_SIZE 0x10000
150#elif defined(CONFIG_SDCARD)
151#define CONFIG_SYS_EXTRA_ENV_RELOC
152#define CONFIG_ENV_IS_IN_MMC
153#define CONFIG_SYS_MMC_ENV_DEV 0
154#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530155#define CONFIG_ENV_OFFSET (512 * 0x800)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530156#elif defined(CONFIG_NAND)
157#define CONFIG_SYS_EXTRA_ENV_RELOC
158#define CONFIG_ENV_IS_IN_NAND
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530159#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530160#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530161#else
162#define CONFIG_ENV_IS_IN_FLASH
163#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
164#define CONFIG_ENV_SIZE 0x2000
165#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
166#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530167
168#define CONFIG_SYS_CLK_FREQ 100000000
169#define CONFIG_DDR_CLK_FREQ 66666666
170
171/*
172 * These can be toggled for performance analysis, otherwise use default.
173 */
174#define CONFIG_SYS_CACHE_STASHING
175#define CONFIG_BACKSIDE_L2_CACHE
176#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
177#define CONFIG_BTB /* toggle branch predition */
178#define CONFIG_DDR_ECC
179#ifdef CONFIG_DDR_ECC
180#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
181#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
182#endif
183
184#define CONFIG_ENABLE_36BIT_PHYS
185
186#define CONFIG_ADDR_MAP
187#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
188
189#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
190#define CONFIG_SYS_MEMTEST_END 0x00400000
191#define CONFIG_SYS_ALT_MEMTEST
192#define CONFIG_PANIC_HANG /* do not reset board on panic */
193
194/*
195 * Config the L3 Cache as L3 SRAM
196 */
197#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530198#define CONFIG_SYS_L3_SIZE 256 << 10
199#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
200#ifdef CONFIG_RAMBOOT_PBL
201#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
202#endif
203#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
204#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
205#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
206#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530207
208#define CONFIG_SYS_DCSRBAR 0xf0000000
209#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
210
211/*
212 * DDR Setup
213 */
214#define CONFIG_VERY_BIG_RAM
215#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
216#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
217
218/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
219#define CONFIG_DIMM_SLOTS_PER_CTLR 1
Priyanka Jain96ac18c2014-02-26 09:38:37 +0530220#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530221
222#define CONFIG_DDR_SPD
York Sun5614e712013-09-30 09:22:09 -0700223#define CONFIG_SYS_FSL_DDR3
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530224
225#define CONFIG_SYS_SPD_BUS_NUM 0
226#define SPD_EEPROM_ADDRESS 0x51
227
228#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
229
230/*
231 * IFC Definitions
232 */
233#define CONFIG_SYS_FLASH_BASE 0xe8000000
234#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
235
236#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
237#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
238 CSPR_PORT_SIZE_16 | \
239 CSPR_MSEL_NOR | \
240 CSPR_V)
241#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
Sandeep Singh377ffcf2014-06-05 18:49:57 +0530242
243/*
244 * TDM Definition
245 */
246#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
247
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530248/* NOR Flash Timing Params */
249#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
250#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
251 FTIM0_NOR_TEADC(0x5) | \
252 FTIM0_NOR_TEAHC(0x5))
253#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
254 FTIM1_NOR_TRAD_NOR(0x1A) |\
255 FTIM1_NOR_TSEQRAD_NOR(0x13))
256#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
257 FTIM2_NOR_TCH(0x4) | \
258 FTIM2_NOR_TWPH(0x0E) | \
259 FTIM2_NOR_TWP(0x1c))
260#define CONFIG_SYS_NOR_FTIM3 0x0
261
262#define CONFIG_SYS_FLASH_QUIET_TEST
263#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
264
265#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
266#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
267#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
268#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
269
270#define CONFIG_SYS_FLASH_EMPTY_INFO
271#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
272
273/* CPLD on IFC */
Prabhakar Kushwaha55153d62014-04-03 16:50:05 +0530274#define CPLD_LBMAP_MASK 0x3F
275#define CPLD_BANK_SEL_MASK 0x07
276#define CPLD_BANK_OVERRIDE 0x40
277#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
278#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
279#define CPLD_LBMAP_RESET 0xFF
280#define CPLD_LBMAP_SHIFT 0x03
Jason Jincf8ddac2014-03-19 10:47:56 +0800281#ifdef CONFIG_T1042RDB_PI
282#define CPLD_DIU_SEL_DFP 0x80
283#endif
Prabhakar Kushwaha55153d62014-04-03 16:50:05 +0530284
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530285#define CONFIG_SYS_CPLD_BASE 0xffdf0000
286#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
Priyanka Jain9b444be2014-01-27 14:07:11 +0530287#define CONFIG_SYS_CSPR2_EXT (0xf)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530288#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
289 | CSPR_PORT_SIZE_8 \
290 | CSPR_MSEL_GPCM \
291 | CSPR_V)
292#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
293#define CONFIG_SYS_CSOR2 0x0
294/* CPLD Timing parameters for IFC CS2 */
295#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
296 FTIM0_GPCM_TEADC(0x0e) | \
297 FTIM0_GPCM_TEAHC(0x0e))
298#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
299 FTIM1_GPCM_TRAD(0x1f))
300#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800301 FTIM2_GPCM_TCH(0x8) | \
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530302 FTIM2_GPCM_TWP(0x1f))
303#define CONFIG_SYS_CS2_FTIM3 0x0
304
305/* NAND Flash on IFC */
306#define CONFIG_NAND_FSL_IFC
307#define CONFIG_SYS_NAND_BASE 0xff800000
308#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
309
310#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
311#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
312 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
313 | CSPR_MSEL_NAND /* MSEL = NAND */ \
314 | CSPR_V)
315#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
316
317#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
318 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
319 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
320 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
321 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
322 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
323 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
324
325#define CONFIG_SYS_NAND_ONFI_DETECTION
326
327/* ONFI NAND Flash mode0 Timing Params */
328#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
329 FTIM0_NAND_TWP(0x18) | \
330 FTIM0_NAND_TWCHT(0x07) | \
331 FTIM0_NAND_TWH(0x0a))
332#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
333 FTIM1_NAND_TWBE(0x39) | \
334 FTIM1_NAND_TRR(0x0e) | \
335 FTIM1_NAND_TRP(0x18))
336#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
337 FTIM2_NAND_TREH(0x0a) | \
338 FTIM2_NAND_TWHRE(0x1e))
339#define CONFIG_SYS_NAND_FTIM3 0x0
340
341#define CONFIG_SYS_NAND_DDR_LAW 11
342#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
343#define CONFIG_SYS_MAX_NAND_DEVICE 1
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530344#define CONFIG_CMD_NAND
345
346#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
347
348#if defined(CONFIG_NAND)
349#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
350#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
351#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
352#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
353#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
354#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
355#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
356#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
357#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
358#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
359#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
360#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
361#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
362#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
363#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
364#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
365#else
366#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
367#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
368#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
369#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
370#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
371#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
372#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
373#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
374#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
375#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
376#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
377#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
378#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
379#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
380#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
381#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
382#endif
383
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530384#ifdef CONFIG_SPL_BUILD
385#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
386#else
387#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
388#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530389
390#if defined(CONFIG_RAMBOOT_PBL)
391#define CONFIG_SYS_RAMBOOT
392#endif
393
Prabhakar Kushwaha9f074e62014-10-29 22:33:09 +0530394#ifdef CONFIG_SYS_FSL_ERRATUM_A008044
395#if defined(CONFIG_NAND)
396#define CONFIG_A008044_WORKAROUND
397#endif
398#endif
399
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530400#define CONFIG_BOARD_EARLY_INIT_R
401#define CONFIG_MISC_INIT_R
402
403#define CONFIG_HWCONFIG
404
405/* define to use L1 as initial stack */
406#define CONFIG_L1_INIT_RAM
407#define CONFIG_SYS_INIT_RAM_LOCK
408#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
409#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
410#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
411/* The assembler doesn't like typecast */
412#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
413 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
414 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
415#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
416
417#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
418 GENERATED_GBL_DATA_SIZE)
419#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
420
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530421#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530422#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
423
424/* Serial Port - controlled on board with jumper J8
425 * open - index 2
426 * shorted - index 1
427 */
428#define CONFIG_CONS_INDEX 1
429#define CONFIG_SYS_NS16550
430#define CONFIG_SYS_NS16550_SERIAL
431#define CONFIG_SYS_NS16550_REG_SIZE 1
432#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
433
434#define CONFIG_SYS_BAUDRATE_TABLE \
435 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
436
437#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
438#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
439#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
440#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
441#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530442#ifndef CONFIG_SPL_BUILD
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530443#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530444#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530445
446/* Use the HUSH parser */
447#define CONFIG_SYS_HUSH_PARSER
448#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
449
Jason Jincf8ddac2014-03-19 10:47:56 +0800450#ifdef CONFIG_T1042RDB_PI
451/* Video */
452#define CONFIG_FSL_DIU_FB
453
454#ifdef CONFIG_FSL_DIU_FB
455#define CONFIG_FSL_DIU_CH7301
456#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
457#define CONFIG_VIDEO
458#define CONFIG_CMD_BMP
459#define CONFIG_CFB_CONSOLE
460#define CONFIG_CFB_CONSOLE_ANSI
461#define CONFIG_VIDEO_SW_CURSOR
462#define CONFIG_VGA_AS_SINGLE_DEVICE
463#define CONFIG_VIDEO_LOGO
464#define CONFIG_VIDEO_BMP_LOGO
465#endif
466#endif
467
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530468/* pass open firmware flat tree */
469#define CONFIG_OF_LIBFDT
470#define CONFIG_OF_BOARD_SETUP
471#define CONFIG_OF_STDOUT_VIA_ALIAS
472
473/* new uImage format support */
474#define CONFIG_FIT
475#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
476
477/* I2C */
478#define CONFIG_SYS_I2C
479#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
480#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800481#define CONFIG_SYS_FSL_I2C2_SPEED 400000
482#define CONFIG_SYS_FSL_I2C3_SPEED 400000
483#define CONFIG_SYS_FSL_I2C4_SPEED 400000
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530484#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530485#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800486#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
487#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530488#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800489#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
490#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
491#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530492
493/* I2C bus multiplexer */
494#define I2C_MUX_PCA_ADDR 0x70
vijay rai363fb322014-08-19 12:46:53 +0530495#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530496#define I2C_MUX_CH_DEFAULT 0x8
vijay raif4c39172014-03-31 11:46:34 +0530497#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530498
vijay raif4c39172014-03-31 11:46:34 +0530499#ifdef CONFIG_T1042RDB_PI
Jason Jincf8ddac2014-03-19 10:47:56 +0800500/* LDI/DVI Encoder for display */
501#define CONFIG_SYS_I2C_LDI_ADDR 0x38
502#define CONFIG_SYS_I2C_DVI_ADDR 0x75
503
vijay raif4c39172014-03-31 11:46:34 +0530504/*
505 * RTC configuration
506 */
507#define RTC
508#define CONFIG_RTC_DS1337 1
509#define CONFIG_SYS_I2C_RTC_ADDR 0x68
510
511/*DVI encoder*/
512#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
513#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530514
515/*
516 * eSPI - Enhanced SPI
517 */
518#define CONFIG_FSL_ESPI
519#define CONFIG_SPI_FLASH
520#define CONFIG_SPI_FLASH_STMICRO
Zhiqiang Hou7172de32014-09-17 17:37:44 +0800521#define CONFIG_SPI_FLASH_BAR
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530522#define CONFIG_CMD_SF
523#define CONFIG_SF_DEFAULT_SPEED 10000000
524#define CONFIG_SF_DEFAULT_MODE 0
Priyanka Jain9b444be2014-01-27 14:07:11 +0530525#define CONFIG_ENV_SPI_BUS 0
526#define CONFIG_ENV_SPI_CS 0
527#define CONFIG_ENV_SPI_MAX_HZ 10000000
528#define CONFIG_ENV_SPI_MODE 0
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530529
530/*
531 * General PCI
532 * Memory space is mapped 1-1, but I/O space must start from 0.
533 */
534
535#ifdef CONFIG_PCI
536/* controller 1, direct to uli, tgtid 3, Base address 20000 */
537#ifdef CONFIG_PCIE1
538#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
539#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
540#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
541#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
542#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
543#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
544#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
545#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
546#endif
547
548/* controller 2, Slot 2, tgtid 2, Base address 201000 */
549#ifdef CONFIG_PCIE2
550#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
551#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
552#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
553#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
554#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
555#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
556#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
557#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
558#endif
559
560/* controller 3, Slot 1, tgtid 1, Base address 202000 */
561#ifdef CONFIG_PCIE3
562#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
563#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
564#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
565#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
566#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
567#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
568#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
569#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
570#endif
571
572/* controller 4, Base address 203000 */
573#ifdef CONFIG_PCIE4
574#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
575#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
576#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
577#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
578#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
579#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
580#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
581#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
582#endif
583
584#define CONFIG_PCI_PNP /* do pci plug-and-play */
585#define CONFIG_E1000
586
587#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
588#define CONFIG_DOS_PARTITION
589#endif /* CONFIG_PCI */
590
591/* SATA */
592#define CONFIG_FSL_SATA_V2
593#ifdef CONFIG_FSL_SATA_V2
594#define CONFIG_LIBATA
595#define CONFIG_FSL_SATA
596
597#define CONFIG_SYS_SATA_MAX_DEVICE 1
598#define CONFIG_SATA1
599#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
600#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
601
602#define CONFIG_LBA48
603#define CONFIG_CMD_SATA
604#define CONFIG_DOS_PARTITION
605#define CONFIG_CMD_EXT2
606#endif
607
608/*
609* USB
610*/
611#define CONFIG_HAS_FSL_DR_USB
612
613#ifdef CONFIG_HAS_FSL_DR_USB
614#define CONFIG_USB_EHCI
615
616#ifdef CONFIG_USB_EHCI
617#define CONFIG_CMD_USB
618#define CONFIG_USB_STORAGE
619#define CONFIG_USB_EHCI_FSL
620#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
621#define CONFIG_CMD_EXT2
622#endif
623#endif
624
625#define CONFIG_MMC
626
627#ifdef CONFIG_MMC
628#define CONFIG_FSL_ESDHC
629#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
630#define CONFIG_CMD_MMC
631#define CONFIG_GENERIC_MMC
632#define CONFIG_CMD_EXT2
633#define CONFIG_CMD_FAT
634#define CONFIG_DOS_PARTITION
635#endif
636
637/* Qman/Bman */
638#ifndef CONFIG_NOBQFMAN
639#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500640#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530641#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
642#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
643#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500644#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
645#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
646#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
647#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
648#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
649 CONFIG_SYS_BMAN_CENA_SIZE)
650#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
651#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500652#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530653#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
654#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
655#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500656#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
657#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
658#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
659#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
660#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
661 CONFIG_SYS_QMAN_CENA_SIZE)
662#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
663#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530664
665#define CONFIG_SYS_DPAA_FMAN
666#define CONFIG_SYS_DPAA_PME
667
vijay rai363fb322014-08-19 12:46:53 +0530668#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
Zhao Qiang59ff5d32014-03-14 10:11:03 +0800669#define CONFIG_QE
670#define CONFIG_U_QE
Prabhakar Kushwaha099b86b2014-04-21 10:47:25 +0530671#endif
Zhao Qiang59ff5d32014-03-14 10:11:03 +0800672
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530673/* Default address of microcode for the Linux Fman driver */
674#if defined(CONFIG_SPIFLASH)
675/*
676 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
677 * env, so we got 0x110000.
678 */
679#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800680#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530681#elif defined(CONFIG_SDCARD)
682/*
683 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530684 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
685 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530686 */
687#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530688#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530689#elif defined(CONFIG_NAND)
690#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530691#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530692#else
693#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800694#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530695#endif
696
vijay rai363fb322014-08-19 12:46:53 +0530697#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530698#if defined(CONFIG_SPIFLASH)
699#define CONFIG_SYS_QE_FW_ADDR 0x130000
700#elif defined(CONFIG_SDCARD)
701#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
702#elif defined(CONFIG_NAND)
703#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
704#else
Zhao Qiang59ff5d32014-03-14 10:11:03 +0800705#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530706#endif
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530707#endif
708
709
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530710#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
711#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
712#endif /* CONFIG_NOBQFMAN */
713
714#ifdef CONFIG_SYS_DPAA_FMAN
715#define CONFIG_FMAN_ENET
716#define CONFIG_PHY_VITESSE
717#define CONFIG_PHY_REALTEK
718#endif
719
720#ifdef CONFIG_FMAN_ENET
vijay rai363fb322014-08-19 12:46:53 +0530721#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
Priyanka Jain714fd402014-01-30 11:30:04 +0530722#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
vijay raif4c39172014-03-31 11:46:34 +0530723#endif
Priyanka Jain714fd402014-01-30 11:30:04 +0530724#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
725#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530726
Codrin Ciubotariudb4a1762015-01-21 11:54:12 +0200727/* Enable VSC9953 L2 Switch driver on T1040 SoC */
728#ifdef CONFIG_T1040RDB
729#define CONFIG_VSC9953
730#define CONFIG_VSC9953_CMD
731#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
732#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
733#endif
734
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530735#define CONFIG_MII /* MII PHY management */
Priyanka Jain714fd402014-01-30 11:30:04 +0530736#define CONFIG_ETHPRIME "FM1@DTSEC4"
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530737#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
738#endif
739
740/*
741 * Environment
742 */
743#define CONFIG_LOADS_ECHO /* echo on for serial download */
744#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
745
746/*
747 * Command line configuration.
748 */
749#include <config_cmd_default.h>
750
vijay raif4c39172014-03-31 11:46:34 +0530751#ifdef CONFIG_T1042RDB_PI
752#define CONFIG_CMD_DATE
753#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530754#define CONFIG_CMD_DHCP
755#define CONFIG_CMD_ELF
756#define CONFIG_CMD_ERRATA
757#define CONFIG_CMD_GREPENV
758#define CONFIG_CMD_IRQ
759#define CONFIG_CMD_I2C
760#define CONFIG_CMD_MII
761#define CONFIG_CMD_PING
762#define CONFIG_CMD_REGINFO
763#define CONFIG_CMD_SETEXPR
764
765#ifdef CONFIG_PCI
766#define CONFIG_CMD_PCI
767#define CONFIG_CMD_NET
768#endif
769
Ruchika Gupta737537e2014-10-15 11:35:31 +0530770/* Hash command with SHA acceleration supported in hardware */
771#ifdef CONFIG_FSL_CAAM
772#define CONFIG_CMD_HASH
773#define CONFIG_SHA_HW_ACCEL
774#endif
775
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530776/*
777 * Miscellaneous configurable options
778 */
779#define CONFIG_SYS_LONGHELP /* undef to save memory */
780#define CONFIG_CMDLINE_EDITING /* Command-line editing */
781#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
782#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530783#ifdef CONFIG_CMD_KGDB
784#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
785#else
786#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
787#endif
788#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
789#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
790#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530791
792/*
793 * For booting Linux, the board info and command line data
794 * have to be in the first 64 MB of memory, since this is
795 * the maximum mapped by the Linux kernel during initialization.
796 */
797#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
798#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
799
800#ifdef CONFIG_CMD_KGDB
801#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530802#endif
803
804/*
Prabhakar Kushwaha68b74732014-04-02 17:26:23 +0530805 * Dynamic MTD Partition support with mtdparts
806 */
807#ifndef CONFIG_SYS_NO_FLASH
808#define CONFIG_MTD_DEVICE
809#define CONFIG_MTD_PARTITIONS
810#define CONFIG_CMD_MTDPARTS
811#define CONFIG_FLASH_CFI_MTD
812#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
813 "spi0=spife110000.0"
814#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
815 "128k(dtb),96m(fs),-(user);"\
816 "fff800000.flash:2m(uboot),9m(kernel),"\
817 "128k(dtb),96m(fs),-(user);spife110000.0:" \
818 "2m(uboot),9m(kernel),128k(dtb),-(user)"
819#endif
820
821/*
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530822 * Environment Configuration
823 */
824#define CONFIG_ROOTPATH "/opt/nfsroot"
825#define CONFIG_BOOTFILE "uImage"
826#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
827
828/* default location for tftp and bootm */
829#define CONFIG_LOADADDR 1000000
830
831#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
832
833#define CONFIG_BAUDRATE 115200
834
835#define __USB_PHY_TYPE utmi
vijay rai363fb322014-08-19 12:46:53 +0530836#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530837
vijay raif4c39172014-03-31 11:46:34 +0530838#ifdef CONFIG_T1040RDB
839#define FDTFILE "t1040rdb/t1040rdb.dtb"
vijay rai363fb322014-08-19 12:46:53 +0530840#elif defined(CONFIG_T1042RDB_PI)
841#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
842#elif defined(CONFIG_T1042RDB)
843#define FDTFILE "t1042rdb/t1042rdb.dtb"
vijay raif4c39172014-03-31 11:46:34 +0530844#endif
845
Jason Jincf8ddac2014-03-19 10:47:56 +0800846#ifdef CONFIG_FSL_DIU_FB
847#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
848#else
849#define DIU_ENVIRONMENT
850#endif
851
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530852#define CONFIG_EXTRA_ENV_SETTINGS \
Priyanka Jain9b444be2014-01-27 14:07:11 +0530853 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
854 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
855 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530856 "netdev=eth0\0" \
Jason Jincf8ddac2014-03-19 10:47:56 +0800857 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530858 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
859 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
860 "tftpflash=tftpboot $loadaddr $uboot && " \
861 "protect off $ubootaddr +$filesize && " \
862 "erase $ubootaddr +$filesize && " \
863 "cp.b $loadaddr $ubootaddr $filesize && " \
864 "protect on $ubootaddr +$filesize && " \
865 "cmp.b $loadaddr $ubootaddr $filesize\0" \
866 "consoledev=ttyS0\0" \
867 "ramdiskaddr=2000000\0" \
vijay raif4c39172014-03-31 11:46:34 +0530868 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530869 "fdtaddr=c00000\0" \
vijay raif4c39172014-03-31 11:46:34 +0530870 "fdtfile=" __stringify(FDTFILE) "\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500871 "bdev=sda3\0"
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530872
873#define CONFIG_LINUX \
874 "setenv bootargs root=/dev/ram rw " \
875 "console=$consoledev,$baudrate $othbootargs;" \
876 "setenv ramdiskaddr 0x02000000;" \
877 "setenv fdtaddr 0x00c00000;" \
878 "setenv loadaddr 0x1000000;" \
879 "bootm $loadaddr $ramdiskaddr $fdtaddr"
880
881#define CONFIG_HDBOOT \
882 "setenv bootargs root=/dev/$bdev rw " \
883 "console=$consoledev,$baudrate $othbootargs;" \
884 "tftp $loadaddr $bootfile;" \
885 "tftp $fdtaddr $fdtfile;" \
886 "bootm $loadaddr - $fdtaddr"
887
888#define CONFIG_NFSBOOTCOMMAND \
889 "setenv bootargs root=/dev/nfs rw " \
890 "nfsroot=$serverip:$rootpath " \
891 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
892 "console=$consoledev,$baudrate $othbootargs;" \
893 "tftp $loadaddr $bootfile;" \
894 "tftp $fdtaddr $fdtfile;" \
895 "bootm $loadaddr - $fdtaddr"
896
897#define CONFIG_RAMBOOTCOMMAND \
898 "setenv bootargs root=/dev/ram rw " \
899 "console=$consoledev,$baudrate $othbootargs;" \
900 "tftp $ramdiskaddr $ramdiskfile;" \
901 "tftp $loadaddr $bootfile;" \
902 "tftp $fdtaddr $fdtfile;" \
903 "bootm $loadaddr $ramdiskaddr $fdtaddr"
904
905#define CONFIG_BOOTCOMMAND CONFIG_LINUX
906
907#ifdef CONFIG_SECURE_BOOT
908#include <asm/fsl_secure_boot.h>
Ruchika Gupta789490b2014-10-07 15:48:46 +0530909#define CONFIG_CMD_BLOB
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530910#endif
911
912#endif /* __CONFIG_H */