blob: 1973447a237c4e343f815287a73009dc4a1f60f0 [file] [log] [blame]
Anton Vorontsovfab6f552008-01-09 20:57:47 +03001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
7 *
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
Anton Vorontsovfab6f552008-01-09 20:57:47 +030012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Anton Vorontsovfab6f552008-01-09 20:57:47 +030017/*
18 * High Level Configuration Options
19 */
20#define CONFIG_E300 1 /* E300 family */
21#define CONFIG_QE 1 /* Has QE */
Peter Tyser0f898602009-05-22 17:23:24 -050022#define CONFIG_MPC83xx 1 /* MPC83xx family */
Anton Vorontsovfab6f552008-01-09 20:57:47 +030023#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
24#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
25
Wolfgang Denk2ae18242010-10-06 09:05:45 +020026#define CONFIG_SYS_TEXT_BASE 0xFF800000
27
Anton Vorontsovfab6f552008-01-09 20:57:47 +030028/*
29 * System Clock Setup
30 */
31#ifdef CONFIG_CLKIN_33MHZ
Anton Vorontsovf700e7d2008-03-24 20:47:05 +030032#define CONFIG_83XX_CLKIN 33333333
33#define CONFIG_SYS_CLK_FREQ 33333333
Wolfgang Denk2ae18242010-10-06 09:05:45 +020034#define CONFIG_PCI_33M 1
Anton Vorontsovfab6f552008-01-09 20:57:47 +030035#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
36#else
37#define CONFIG_83XX_CLKIN 66000000
38#define CONFIG_SYS_CLK_FREQ 66000000
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_PCI_66M 1
Anton Vorontsovfab6f552008-01-09 20:57:47 +030040#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
41#endif /* CONFIG_CLKIN_33MHZ */
42
43/*
44 * Hardware Reset Configuration Word
45 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_HRCW_LOW (\
Anton Vorontsovfab6f552008-01-09 20:57:47 +030047 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
48 HRCWL_DDR_TO_SCB_CLK_1X1 |\
49 HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
50 HRCWL_CORE_TO_CSB_2X1 |\
51 HRCWL_CE_TO_PLL_1X15)
52
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_HRCW_HIGH (\
Anton Vorontsovfab6f552008-01-09 20:57:47 +030054 HRCWH_PCI_HOST |\
55 HRCWH_PCI1_ARBITER_ENABLE |\
56 HRCWH_PCICKDRV_ENABLE |\
57 HRCWH_CORE_ENABLE |\
58 HRCWH_FROM_0X00000100 |\
59 HRCWH_BOOTSEQ_DISABLE |\
60 HRCWH_SW_WATCHDOG_DISABLE |\
61 HRCWH_ROM_LOC_LOCAL_16BIT |\
62 HRCWH_SECONDARY_DDR_DISABLE |\
63 HRCWH_BIG_ENDIAN |\
64 HRCWH_LALE_EARLY)
65
66/*
67 * System IO Config
68 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_SICRH 0x00000000
70#define CONFIG_SYS_SICRL 0x40000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +030071
Anton Vorontsovfab6f552008-01-09 20:57:47 +030072#define CONFIG_BOARD_EARLY_INIT_R
73
74/*
75 * IMMR new address
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_IMMR 0xE0000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +030078
79/*
80 * DDR Setup
81 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
83#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
84#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Joe Hershberger9a986552011-10-11 23:57:17 -050085#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
86 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Anton Vorontsovfab6f552008-01-09 20:57:47 +030087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_83XX_DDR_USES_CS0
Anton Vorontsovfab6f552008-01-09 20:57:47 +030089
Anton Vorontsovd892b2d2008-03-24 20:46:57 +030090#define CONFIG_DDR_ECC /* support DDR ECC function */
91#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
Anton Vorontsovfab6f552008-01-09 20:57:47 +030092
93/*
94 * DDRCDR - DDR Control Driver Register
95 */
Joe Hershberger2fef4022011-10-11 23:57:29 -050096#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
97 | DDRCDR_ODT \
98 | DDRCDR_Q_DRN)
99 /* 0x80080001 */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300100
101#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
102
103/*
104 * Manually set up DDR parameters
105 */
106#define CONFIG_DDR_II
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Joe Hershberger2fef4022011-10-11 23:57:29 -0500108#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
Joe Hershberger9a986552011-10-11 23:57:17 -0500109#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
110 | CSCONFIG_ROW_BIT_13 \
111 | CSCONFIG_COL_BIT_10 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500112 | CSCONFIG_ODT_WR_ONLY_CURRENT)
Joe Hershberger9a986552011-10-11 23:57:17 -0500113#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \
114 | SDRAM_CFG_ECC_EN)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
Joe Hershberger9a986552011-10-11 23:57:17 -0500116#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
117#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
118 | (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DDR_MODE 0x47800432
120#define CONFIG_SYS_DDR_MODE2 0x8000c000
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300123 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
124 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
125 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
126 (0 << TIMING_CFG0_WWT_SHIFT) | \
127 (0 << TIMING_CFG0_RRT_SHIFT) | \
128 (0 << TIMING_CFG0_WRT_SHIFT) | \
129 (0 << TIMING_CFG0_RWT_SHIFT))
130
Joe Hershberger9a986552011-10-11 23:57:17 -0500131#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \
132 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
133 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
134 (3 << TIMING_CFG1_WRREC_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300135 (10 << TIMING_CFG1_REFREC_SHIFT) | \
Joe Hershberger9a986552011-10-11 23:57:17 -0500136 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
137 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
138 (3 << TIMING_CFG1_PRETOACT_SHIFT))
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300141 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
142 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
143 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
144 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
145 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
146 (0 << TIMING_CFG2_CPO_SHIFT))
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300149
150/*
151 * Memory test
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
154#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
155#define CONFIG_SYS_MEMTEST_END 0x00100000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300156
157/*
158 * The reserved memory
159 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200160#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
164#define CONFIG_SYS_RAMBOOT
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300165#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#undef CONFIG_SYS_RAMBOOT
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300167#endif
168
Joe Hershberger9a986552011-10-11 23:57:17 -0500169#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500170#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300171
172/*
173 * Initial RAM Base Address Setup
174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_INIT_RAM_LOCK 1
176#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200177#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger9a986552011-10-11 23:57:17 -0500178#define CONFIG_SYS_GBL_DATA_OFFSET \
179 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300180
181/*
182 * Local Bus Configuration & Clock Setup
183 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500184#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
185#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Joe Hershberger9a986552011-10-11 23:57:17 -0500186#define CONFIG_SYS_LBC_LBCR 0x00000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300187
188/*
189 * FLASH on the Local Bus
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Joe Hershberger9a986552011-10-11 23:57:17 -0500192#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
194#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300195
Joe Hershberger9a986552011-10-11 23:57:17 -0500196 /* Window base at flash base */
197#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500198#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300199
Joe Hershberger9a986552011-10-11 23:57:17 -0500200#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500201 | BR_PS_16 /* 16 bit port */ \
202 | BR_MS_GPCM /* MSEL = GPCM */ \
203 | BR_V) /* valid */
204#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershberger9a986552011-10-11 23:57:17 -0500205 | OR_UPM_XAM \
206 | OR_GPCM_CSNT \
207 | OR_GPCM_ACS_DIV2 \
208 | OR_GPCM_XACS \
209 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500210 | OR_GPCM_TRLX_SET \
211 | OR_GPCM_EHTR_SET \
Joe Hershberger9a986552011-10-11 23:57:17 -0500212 | OR_GPCM_EAD)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
215#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#undef CONFIG_SYS_FLASH_CHECKSUM
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300218
219/*
220 * NAND flash on the local bus
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_NAND_BASE 0x60000000
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300223#define CONFIG_CMD_NAND 1
224#define CONFIG_NAND_FSL_UPM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_MAX_NAND_DEVICE 1
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300226#define CONFIG_MTD_NAND_VERIFY_WRITE
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500229/*
230 * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB
231 * ... What's correct?
232 */
233#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300234
235/* Port size 8 bit, UPMA */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500236#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
237 | BR_PS_8 \
238 | BR_MS_UPMA \
239 | BR_V)
240 /* 0x60000881 */
241#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD)
242 /* 0xFC000001 */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300243
244/*
245 * Fujitsu MB86277 (MINT) graphics controller
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_VIDEO_BASE 0x70000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500250#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300251
252/* Port size 32 bit, UPMB */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500253#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \
254 | BR_PS_32 \
255 | BR_MS_UPMB \
256 | BR_V)
257 /* 0x000018a1 */
258#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD)
259 /* 0xFC000001 */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300260
261/*
262 * Serial Port
263 */
264#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_NS16550
266#define CONFIG_SYS_NS16550_SERIAL
267#define CONFIG_SYS_NS16550_REG_SIZE 1
268#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger9a986552011-10-11 23:57:17 -0500271 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
274#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300275
276#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Joe Hershberger9a986552011-10-11 23:57:17 -0500277#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300278/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_HUSH_PARSER
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300280
281/* Pass open firmware flat tree */
282#define CONFIG_OF_LIBFDT 1
283#define CONFIG_OF_BOARD_SETUP 1
Anton Vorontsov3a0cfdd2008-03-24 20:47:02 +0300284#define CONFIG_OF_STDOUT_VIA_ALIAS
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300285
286/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200287#define CONFIG_SYS_I2C
288#define CONFIG_SYS_I2C_FSL
289#define CONFIG_SYS_FSL_I2C_SPEED 400000
290#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
291#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
292#define CONFIG_SYS_FSL_I2C2_SPEED 400000
293#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
294#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
295#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300296
297/*
298 * General PCI
299 * Addresses are mapped 1-1.
300 */
301#define CONFIG_PCI
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
304#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
305#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
306#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
307#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
308#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger9a986552011-10-11 23:57:17 -0500309#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
310#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
311#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300312
313#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000314#define CONFIG_PCI_INDIRECT_BRIDGE
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300315
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300316#define CONFIG_PCI_PNP /* do pci plug-and-play */
317
318#undef CONFIG_EEPRO100
319#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300321
322#endif /* CONFIG_PCI */
323
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300324/*
325 * QE UEC ethernet configuration
326 */
327#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500328#define CONFIG_ETHPRIME "UEC0"
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300329
330#define CONFIG_UEC_ETH1 /* GETH1 */
331
332#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
334#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
335#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
336#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
337#define CONFIG_SYS_UEC1_PHY_ADDR 2
Joe Hershberger9a986552011-10-11 23:57:17 -0500338#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
339#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300340#endif
341
342#define CONFIG_UEC_ETH2 /* GETH2 */
343
344#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
346#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
347#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
348#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
349#define CONFIG_SYS_UEC2_PHY_ADDR 4
Joe Hershberger9a986552011-10-11 23:57:17 -0500350#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
351#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300352#endif
353
354/*
355 * Environment
356 */
357
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200359#define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger9a986552011-10-11 23:57:17 -0500360#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200361#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
362#define CONFIG_ENV_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#else /* CONFIG_SYS_RAMBOOT */
Joe Hershberger9a986552011-10-11 23:57:17 -0500364#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200365#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200367#define CONFIG_ENV_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#endif /* CONFIG_SYS_RAMBOOT */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300369
370#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300372
373/*
374 * BOOTP options
375 */
376#define CONFIG_BOOTP_BOOTFILESIZE
377#define CONFIG_BOOTP_BOOTPATH
378#define CONFIG_BOOTP_GATEWAY
379#define CONFIG_BOOTP_HOSTNAME
380
381
382/*
383 * Command line configuration.
384 */
385#include <config_cmd_default.h>
386
387#define CONFIG_CMD_PING
388#define CONFIG_CMD_I2C
389#define CONFIG_CMD_ASKENV
Anton Vorontsov3419eb62008-03-24 20:47:00 +0300390#define CONFIG_CMD_DHCP
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300391
392#if defined(CONFIG_PCI)
393#define CONFIG_CMD_PCI
394#endif
395
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500397#undef CONFIG_CMD_SAVEENV
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300398#undef CONFIG_CMD_LOADS
399#endif
400
401#undef CONFIG_WATCHDOG /* watchdog disabled */
402
403/*
404 * Miscellaneous configurable options
405 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_LONGHELP /* undef to save memory */
407#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
408#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300409
410#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300412#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300414#endif
415
Joe Hershberger9a986552011-10-11 23:57:17 -0500416 /* Print Buffer Size */
417#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
418#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
419 /* Boot Argument Buffer Size */
420#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
421#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300422
423/*
424 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700425 * have to be in the first 256 MB of memory, since this is
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300426 * the maximum mapped by the Linux kernel during initialization.
427 */
Joe Hershberger9a986552011-10-11 23:57:17 -0500428#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300429
430/*
431 * Core HID Setup
432 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500433#define CONFIG_SYS_HID0_INIT 0x000000000
434#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
435 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_HID2 HID2_HBE
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300437
438/*
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300439 * MMU Setup
440 */
441
Becky Bruce31d82672008-05-08 19:02:12 -0500442#define CONFIG_HIGH_BATS 1 /* High BATs supported */
443
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300444/* DDR: cache cacheable */
Joe Hershberger9a986552011-10-11 23:57:17 -0500445#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500446 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500447 | BATL_MEMCOHERENCE)
448#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
449 | BATU_BL_256M \
450 | BATU_VS \
451 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
453#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300454
455/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Joe Hershberger9a986552011-10-11 23:57:17 -0500456#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500457 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500458 | BATL_CACHEINHIBIT \
459 | BATL_GUARDEDSTORAGE)
460#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
461 | BATU_BL_4M \
462 | BATU_VS \
463 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
465#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300466
467/* NAND: cache-inhibit and guarded */
Joe Hershberger9a986552011-10-11 23:57:17 -0500468#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500469 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500470 | BATL_CACHEINHIBIT \
471 | BATL_GUARDEDSTORAGE)
472#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \
473 | BATU_BL_64M \
474 | BATU_VS \
475 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
477#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300478
479/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger9a986552011-10-11 23:57:17 -0500480#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500481 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500482 | BATL_MEMCOHERENCE)
483#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
484 | BATU_BL_32M \
485 | BATU_VS \
486 | BATU_VP)
487#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500488 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500489 | BATL_CACHEINHIBIT \
490 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300492
493/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger9a986552011-10-11 23:57:17 -0500494#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500495 | BATL_PP_RW)
Joe Hershberger9a986552011-10-11 23:57:17 -0500496#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
497 | BATU_BL_128K \
498 | BATU_VS \
499 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
501#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300502
Joe Hershberger9a986552011-10-11 23:57:17 -0500503#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500504 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500505 | BATL_CACHEINHIBIT \
506 | BATL_GUARDEDSTORAGE)
507#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \
508 | BATU_BL_64M \
509 | BATU_VS \
510 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
512#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300513
514#ifdef CONFIG_PCI
515/* PCI MEM space: cacheable */
Joe Hershberger9a986552011-10-11 23:57:17 -0500516#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500517 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500518 | BATL_MEMCOHERENCE)
519#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
520 | BATU_BL_256M \
521 | BATU_VS \
522 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
524#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300525/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger9a986552011-10-11 23:57:17 -0500526#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500527 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500528 | BATL_CACHEINHIBIT \
529 | BATL_GUARDEDSTORAGE)
530#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
531 | BATU_BL_256M \
532 | BATU_VS \
533 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
535#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300536#else /* CONFIG_PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200537#define CONFIG_SYS_IBAT6L (0)
538#define CONFIG_SYS_IBAT6U (0)
539#define CONFIG_SYS_IBAT7L (0)
540#define CONFIG_SYS_IBAT7U (0)
541#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
542#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
543#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
544#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300545#endif /* CONFIG_PCI */
546
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300547#if defined(CONFIG_CMD_KGDB)
548#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
549#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
550#endif
551
552/*
553 * Environment Configuration
554 */
555#define CONFIG_ENV_OVERWRITE
556
557#if defined(CONFIG_UEC_ETH)
558#define CONFIG_HAS_ETH0
559#define CONFIG_HAS_ETH1
560#define CONFIG_HAS_ETH2
561#define CONFIG_HAS_ETH3
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300562#endif
563
564#define CONFIG_BAUDRATE 115200
565
566#define CONFIG_LOADADDR a00000
567#define CONFIG_HOSTNAME mpc8360erdk
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000568#define CONFIG_BOOTFILE "uImage"
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300569
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000570#define CONFIG_ROOTPATH "/nfsroot/"
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300571
572#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
573#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
574
575#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger9a986552011-10-11 23:57:17 -0500576 "netdev=eth0\0" \
577 "consoledev=ttyS0\0" \
578 "loadaddr=a00000\0" \
579 "fdtaddr=900000\0" \
580 "fdtfile=mpc836x_rdk.dtb\0" \
581 "fsfile=fs\0" \
582 "ubootfile=u-boot.bin\0" \
583 "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
584 "-(rootfs)\0" \
585 "setbootargs=setenv bootargs console=$consoledev,$baudrate " \
586 "$mtdparts panic=1\0" \
587 "adddhcpargs=setenv bootargs $bootargs ip=on\0" \
588 "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \
589 "$gatewayip:$netmask:$hostname:$netdev:off " \
590 "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
591 "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \
592 "rootfstype=jffs2 rw\0" \
593 "tftp_get_uboot=tftp 100000 $ubootfile\0" \
594 "tftp_get_kernel=tftp $loadaddr $bootfile\0" \
595 "tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \
596 "tftp_get_fs=tftp c00000 $fsfile\0" \
597 "nand_erase_kernel=nand erase 0 400000\0" \
598 "nand_erase_dtb=nand erase 400000 20000\0" \
599 "nand_erase_fs=nand erase 420000 3be0000\0" \
600 "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \
601 "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \
602 "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \
603 "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \
604 "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \
605 "nor_reflash=protect off ff800000 ff87ffff ; " \
606 "erase ff800000 ff87ffff ; " \
607 "cp.b 100000 ff800000 $filesize\0" \
608 "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \
609 "nand_write_kernel\0" \
610 "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
611 "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \
612 "nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \
613 "nand_reflash_fs\0" \
614 "boot_m=bootm $loadaddr - $fdtaddr\0" \
615 "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
616 "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
617 "boot_m\0" \
618 "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
619 "boot_m\0" \
620 ""
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300621
622#define CONFIG_BOOTCOMMAND "run dhcpboot"
623
624#endif /* __CONFIG_H */