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Kumar Gala129ba612008-08-12 11:13:08 -05001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
Kumar Gala129ba612008-08-12 11:13:08 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala129ba612008-08-12 11:13:08 -05005 */
6
7/*
8 * mpc8572ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Kumar Gala509c4c42010-05-21 04:05:14 -050014#include "../board/freescale/common/ics307_clk.h"
15
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020016#ifdef CONFIG_36BIT
Kumar Galaf9edcc12009-09-10 16:23:45 -050017#define CONFIG_PHYS_64BIT
18#endif
19
Kumar Galacb14e932010-11-12 08:22:01 -060020#ifdef CONFIG_NAND
21#define CONFIG_NAND_U_BOOT
22#define CONFIG_RAMBOOT_NAND
23#ifdef CONFIG_NAND_SPL
24#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
25#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
26#else
Kumar Gala00203c62011-01-31 15:57:01 -060027#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
Kumar Galacb14e932010-11-12 08:22:01 -060028#define CONFIG_SYS_TEXT_BASE 0xf8f82000
29#endif /* CONFIG_NAND_SPL */
30#endif
31
32#ifndef CONFIG_SYS_TEXT_BASE
33#define CONFIG_SYS_TEXT_BASE 0xeff80000
34#endif
35
Kumar Gala7a577fd2011-01-12 02:48:53 -060036#ifndef CONFIG_RESET_VECTOR_ADDRESS
37#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
38#endif
39
Kumar Galacb14e932010-11-12 08:22:01 -060040#ifndef CONFIG_SYS_MONITOR_BASE
41#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
42#endif
43
Kumar Gala129ba612008-08-12 11:13:08 -050044/* High Level Configuration Options */
45#define CONFIG_BOOKE 1 /* BOOKE */
46#define CONFIG_E500 1 /* BOOKE e500 family */
47#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
48#define CONFIG_MPC8572 1
49#define CONFIG_MPC8572DS 1
50#define CONFIG_MP 1 /* support multiple processors */
Kumar Gala129ba612008-08-12 11:13:08 -050051
Kumar Galac51fc5d2009-01-23 14:22:13 -060052#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Kumar Gala129ba612008-08-12 11:13:08 -050053#define CONFIG_PCI 1 /* Enable PCI/PCIE */
54#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
55#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
56#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
57#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000058#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala129ba612008-08-12 11:13:08 -050059#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050060#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala129ba612008-08-12 11:13:08 -050061
62#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
63
64#define CONFIG_TSEC_ENET /* tsec ethernet support */
65#define CONFIG_ENV_OVERWRITE
66
Kumar Gala509c4c42010-05-21 04:05:14 -050067#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
68#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
Haiying Wang4ca06602008-10-03 12:37:41 -040069#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala129ba612008-08-12 11:13:08 -050070
71/*
72 * These can be toggled for performance analysis, otherwise use default.
73 */
74#define CONFIG_L2_CACHE /* toggle L2 cache */
75#define CONFIG_BTB /* toggle branch predition */
Kumar Gala129ba612008-08-12 11:13:08 -050076
77#define CONFIG_ENABLE_36BIT_PHYS 1
78
Kumar Gala18af1c52009-01-23 14:22:14 -060079#ifdef CONFIG_PHYS_64BIT
80#define CONFIG_ADDR_MAP 1
81#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
82#endif
83
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
85#define CONFIG_SYS_MEMTEST_END 0x7fffffff
Kumar Gala129ba612008-08-12 11:13:08 -050086#define CONFIG_PANIC_HANG /* do not reset board on panic */
87
88/*
Kumar Galacb14e932010-11-12 08:22:01 -060089 * Config the L2 Cache as L2 SRAM
90 */
91#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
92#ifdef CONFIG_PHYS_64BIT
93#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
94#else
95#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
96#endif
97#define CONFIG_SYS_L2_SIZE (512 << 10)
98#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
99
Timur Tabie46fedf2011-08-04 18:03:41 -0500100#define CONFIG_SYS_CCSRBAR 0xffe00000
101#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala129ba612008-08-12 11:13:08 -0500102
Kumar Gala8d22ddc2011-11-09 09:10:49 -0600103#if defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -0500104#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Kumar Galacb14e932010-11-12 08:22:01 -0600105#endif
106
Kumar Gala129ba612008-08-12 11:13:08 -0500107/* DDR Setup */
Kumar Galaf8523cb2009-02-06 09:56:35 -0600108#define CONFIG_VERY_BIG_RAM
Kumar Gala129ba612008-08-12 11:13:08 -0500109#define CONFIG_FSL_DDR2
110#undef CONFIG_FSL_DDR_INTERACTIVE
111#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
112#define CONFIG_DDR_SPD
Kumar Gala129ba612008-08-12 11:13:08 -0500113
York Sund34897d2011-01-25 21:51:29 -0800114#define CONFIG_DDR_ECC
Dave Liu9b0ad1b2008-10-28 17:53:38 +0800115#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
Kumar Gala129ba612008-08-12 11:13:08 -0500116#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
119#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala129ba612008-08-12 11:13:08 -0500120
121#define CONFIG_NUM_DDR_CONTROLLERS 2
122#define CONFIG_DIMM_SLOTS_PER_CTLR 1
123#define CONFIG_CHIP_SELECTS_PER_CTRL 2
124
125/* I2C addresses of SPD EEPROMs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500127#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
128#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
129
130/* These are used when DDR doesn't use SPD. */
Dave Liudc889e82008-11-28 20:16:58 +0800131#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
132#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
133#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
134#define CONFIG_SYS_DDR_TIMING_3 0x00020000
135#define CONFIG_SYS_DDR_TIMING_0 0x00260802
136#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
137#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
138#define CONFIG_SYS_DDR_MODE_1 0x00440462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_DDR_MODE_2 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800140#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
Dave Liudc889e82008-11-28 20:16:58 +0800142#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
143#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800145#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
146#define CONFIG_SYS_DDR_CONTROL2 0x24400000
Kumar Gala129ba612008-08-12 11:13:08 -0500147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
149#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
150#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala129ba612008-08-12 11:13:08 -0500151
152/*
Kumar Gala129ba612008-08-12 11:13:08 -0500153 * Make sure required options are set
154 */
155#ifndef CONFIG_SPD_EEPROM
156#error ("CONFIG_SPD_EEPROM is required")
157#endif
158
159#undef CONFIG_CLOCKS_IN_MHZ
160
161/*
162 * Memory map
163 *
164 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
165 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
166 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
167 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
168 *
169 * Localbus cacheable (TBD)
170 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
171 *
172 * Localbus non-cacheable
173 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
174 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100175 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala129ba612008-08-12 11:13:08 -0500176 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
177 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
178 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
179 */
180
181/*
182 * Local Bus Definitions
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala18af1c52009-01-23 14:22:14 -0600185#ifdef CONFIG_PHYS_64BIT
186#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
187#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600188#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600189#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500190
Kumar Galacb14e932010-11-12 08:22:01 -0600191
192#define CONFIG_FLASH_BR_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000193 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
Kumar Galacb14e932010-11-12 08:22:01 -0600194#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500195
Kumar Galac953ddf2008-12-02 14:19:34 -0600196#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
197#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500198
Kumar Gala18af1c52009-01-23 14:22:14 -0600199#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala129ba612008-08-12 11:13:08 -0500201#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
204#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
205#undef CONFIG_SYS_FLASH_CHECKSUM
206#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
207#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala129ba612008-08-12 11:13:08 -0500208
Kumar Galacb14e932010-11-12 08:22:01 -0600209#if defined(CONFIG_RAMBOOT_NAND)
210#define CONFIG_SYS_RAMBOOT
211#define CONFIG_SYS_EXTRA_ENV_RELOC
212#else
213#undef CONFIG_SYS_RAMBOOT
214#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500215
216#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_FLASH_CFI
218#define CONFIG_SYS_FLASH_EMPTY_INFO
219#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala129ba612008-08-12 11:13:08 -0500220
221#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
222
Kumar Gala558710b2010-11-19 08:53:25 -0600223#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala129ba612008-08-12 11:13:08 -0500224#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
225#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala18af1c52009-01-23 14:22:14 -0600226#ifdef CONFIG_PHYS_64BIT
227#define PIXIS_BASE_PHYS 0xfffdf0000ull
228#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600229#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600230#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500231
Kumar Gala52b565f2008-12-02 14:19:33 -0600232#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala129ba612008-08-12 11:13:08 -0500234
235#define PIXIS_ID 0x0 /* Board ID at offset 0 */
236#define PIXIS_VER 0x1 /* Board version at offset 1 */
237#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
238#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
239#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
240#define PIXIS_PWR 0x5 /* PIXIS Power status register */
241#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
242#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
243#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
244#define PIXIS_VCTL 0x10 /* VELA Control Register */
245#define PIXIS_VSTAT 0x11 /* VELA Status Register */
246#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
247#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
248#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
249#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500250#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
251#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
252#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
253#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
254#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500255#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
256#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
257#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
258#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
259#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
260#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
261#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
262#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
263#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
264#define PIXIS_VWATCH 0x24 /* Watchdog Register */
265#define PIXIS_LED 0x25 /* LED Register */
266
Kumar Galacb14e932010-11-12 08:22:01 -0600267#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
268
Kumar Gala129ba612008-08-12 11:13:08 -0500269/* old pixis referenced names */
270#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
271#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
Liu Yu7e183ca2008-10-10 11:40:59 +0800273#define PIXIS_VSPEED2_TSEC1SER 0x8
274#define PIXIS_VSPEED2_TSEC2SER 0x4
275#define PIXIS_VSPEED2_TSEC3SER 0x2
276#define PIXIS_VSPEED2_TSEC4SER 0x1
277#define PIXIS_VCFGEN1_TSEC1SER 0x20
278#define PIXIS_VCFGEN1_TSEC2SER 0x20
279#define PIXIS_VCFGEN1_TSEC3SER 0x20
280#define PIXIS_VCFGEN1_TSEC4SER 0x20
281#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
282 | PIXIS_VSPEED2_TSEC2SER \
283 | PIXIS_VSPEED2_TSEC3SER \
284 | PIXIS_VSPEED2_TSEC4SER)
285#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
286 | PIXIS_VCFGEN1_TSEC2SER \
287 | PIXIS_VCFGEN1_TSEC3SER \
288 | PIXIS_VCFGEN1_TSEC4SER)
Kumar Gala129ba612008-08-12 11:13:08 -0500289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_INIT_RAM_LOCK 1
291#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200292#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala129ba612008-08-12 11:13:08 -0500293
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200294#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
298#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala129ba612008-08-12 11:13:08 -0500299
Kumar Galacb14e932010-11-12 08:22:01 -0600300#ifndef CONFIG_NAND_SPL
Haiying Wangc013b742008-10-29 13:32:59 -0400301#define CONFIG_SYS_NAND_BASE 0xffa00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600302#ifdef CONFIG_PHYS_64BIT
303#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
304#else
Haiying Wangc013b742008-10-29 13:32:59 -0400305#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600306#endif
Kumar Galacb14e932010-11-12 08:22:01 -0600307#else
308#define CONFIG_SYS_NAND_BASE 0xfff00000
309#ifdef CONFIG_PHYS_64BIT
310#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
311#else
312#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
313#endif
314#endif
315
Haiying Wangc013b742008-10-29 13:32:59 -0400316#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
317 CONFIG_SYS_NAND_BASE + 0x40000, \
318 CONFIG_SYS_NAND_BASE + 0x80000,\
319 CONFIG_SYS_NAND_BASE + 0xC0000}
320#define CONFIG_SYS_MAX_NAND_DEVICE 4
Haiying Wangc013b742008-10-29 13:32:59 -0400321#define CONFIG_MTD_NAND_VERIFY_WRITE
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100322#define CONFIG_CMD_NAND 1
323#define CONFIG_NAND_FSL_ELBC 1
Haiying Wangc013b742008-10-29 13:32:59 -0400324#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
325
Kumar Galacb14e932010-11-12 08:22:01 -0600326/* NAND boot: 4K NAND loader config */
327#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
328#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
329#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
330#define CONFIG_SYS_NAND_U_BOOT_START \
331 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
332#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
333#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
334#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
335
336
Haiying Wangc013b742008-10-29 13:32:59 -0400337/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500338#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100339 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
340 | BR_PS_8 /* Port Size = 8 bit */ \
341 | BR_MS_FCM /* MSEL = FCM */ \
342 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500343#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100344 | OR_FCM_PGS /* Large Page*/ \
345 | OR_FCM_CSCT \
346 | OR_FCM_CST \
347 | OR_FCM_CHT \
348 | OR_FCM_SCY_1 \
349 | OR_FCM_TRLX \
350 | OR_FCM_EHTR)
Haiying Wangc013b742008-10-29 13:32:59 -0400351
Kumar Galacb14e932010-11-12 08:22:01 -0600352#ifdef CONFIG_RAMBOOT_NAND
Matthew McClintocka3055c52011-04-05 14:39:33 -0500353#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
354#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Kumar Galacb14e932010-11-12 08:22:01 -0600355#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
356#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
357#else
358#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
359#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500360#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
361#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Kumar Galacb14e932010-11-12 08:22:01 -0600362#endif
Timur Tabi7ee41102012-07-06 07:39:26 +0000363#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100364 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
365 | BR_PS_8 /* Port Size = 8 bit */ \
366 | BR_MS_FCM /* MSEL = FCM */ \
367 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500368#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Timur Tabi7ee41102012-07-06 07:39:26 +0000369#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100370 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
371 | BR_PS_8 /* Port Size = 8 bit */ \
372 | BR_MS_FCM /* MSEL = FCM */ \
373 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500374#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400375
Timur Tabi7ee41102012-07-06 07:39:26 +0000376#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100377 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
378 | BR_PS_8 /* Port Size = 8 bit */ \
379 | BR_MS_FCM /* MSEL = FCM */ \
380 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500381#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400382
383
Kumar Gala129ba612008-08-12 11:13:08 -0500384/* Serial Port - controlled on board with jumper J8
385 * open - index 2
386 * shorted - index 1
387 */
388#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_NS16550
390#define CONFIG_SYS_NS16550_SERIAL
391#define CONFIG_SYS_NS16550_REG_SIZE 1
392#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Galacb14e932010-11-12 08:22:01 -0600393#ifdef CONFIG_NAND_SPL
394#define CONFIG_NS16550_MIN_FUNCTIONS
395#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500396
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala129ba612008-08-12 11:13:08 -0500398 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
399
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
401#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Kumar Gala129ba612008-08-12 11:13:08 -0500402
403/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_HUSH_PARSER
Kumar Gala129ba612008-08-12 11:13:08 -0500405
406/*
407 * Pass open firmware flat tree
408 */
409#define CONFIG_OF_LIBFDT 1
410#define CONFIG_OF_BOARD_SETUP 1
411#define CONFIG_OF_STDOUT_VIA_ALIAS 1
412
Kumar Gala129ba612008-08-12 11:13:08 -0500413/* new uImage format support */
414#define CONFIG_FIT 1
415#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
416
417/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200418#define CONFIG_SYS_I2C
419#define CONFIG_SYS_I2C_FSL
420#define CONFIG_SYS_FSL_I2C_SPEED 400000
421#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
422#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
423#define CONFIG_SYS_FSL_I2C2_SPEED 400000
424#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
425#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
426#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
Kumar Gala129ba612008-08-12 11:13:08 -0500428
429/*
Haiying Wang445a7b32008-10-03 11:47:30 -0400430 * I2C2 EEPROM
431 */
432#define CONFIG_ID_EEPROM
433#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_I2C_EEPROM_NXID
Haiying Wang445a7b32008-10-03 11:47:30 -0400435#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
437#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
438#define CONFIG_SYS_EEPROM_BUS_NUM 1
Haiying Wang445a7b32008-10-03 11:47:30 -0400439
440/*
Kumar Gala129ba612008-08-12 11:13:08 -0500441 * General PCI
442 * Memory space is mapped 1-1, but I/O space must start from 0.
443 */
444
Kumar Gala129ba612008-08-12 11:13:08 -0500445/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600446#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600447#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600448#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500449#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600450#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
451#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600452#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600453#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600454#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600456#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600457#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600458#ifdef CONFIG_PHYS_64BIT
459#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
460#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600462#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500464
465/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600466#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600467#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600468#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500469#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600470#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
471#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600472#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600473#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600474#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600476#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600477#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600478#ifdef CONFIG_PHYS_64BIT
479#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
480#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
Kumar Gala18af1c52009-01-23 14:22:14 -0600482#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500484
485/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600486#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600487#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600488#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500489#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600490#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
491#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600492#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600493#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600494#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600496#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600497#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600498#ifdef CONFIG_PHYS_64BIT
499#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
500#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
Kumar Gala18af1c52009-01-23 14:22:14 -0600502#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500504
505#if defined(CONFIG_PCI)
506
507/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600508#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Kumar Gala129ba612008-08-12 11:13:08 -0500509
510/* video */
511#define CONFIG_VIDEO
512
513#if defined(CONFIG_VIDEO)
514#define CONFIG_BIOSEMU
515#define CONFIG_CFB_CONSOLE
516#define CONFIG_VIDEO_SW_CURSOR
517#define CONFIG_VGA_AS_SINGLE_DEVICE
518#define CONFIG_ATI_RADEON_FB
519#define CONFIG_VIDEO_LOGO
520/*#define CONFIG_CONSOLE_CURSOR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500522#endif
523
Kumar Gala129ba612008-08-12 11:13:08 -0500524#define CONFIG_PCI_PNP /* do pci plug-and-play */
525
526#undef CONFIG_EEPRO100
527#undef CONFIG_TULIP
528#undef CONFIG_RTL8139
Kumar Gala16855ec2010-11-09 23:19:50 -0600529#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Kumar Gala129ba612008-08-12 11:13:08 -0500530
Kumar Gala129ba612008-08-12 11:13:08 -0500531#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600532 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
533 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
Kumar Gala129ba612008-08-12 11:13:08 -0500534 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
535#endif
536
537#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
538#define CONFIG_DOS_PARTITION
539#define CONFIG_SCSI_AHCI
540
541#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -0500542#define CONFIG_LIBATA
Kumar Gala129ba612008-08-12 11:13:08 -0500543#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
545#define CONFIG_SYS_SCSI_MAX_LUN 1
546#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
547#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Kumar Gala129ba612008-08-12 11:13:08 -0500548#endif /* SCSI */
549
550#endif /* CONFIG_PCI */
551
552
553#if defined(CONFIG_TSEC_ENET)
554
Kumar Gala129ba612008-08-12 11:13:08 -0500555#define CONFIG_MII 1 /* MII PHY management */
556#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
557#define CONFIG_TSEC1 1
558#define CONFIG_TSEC1_NAME "eTSEC1"
559#define CONFIG_TSEC2 1
560#define CONFIG_TSEC2_NAME "eTSEC2"
561#define CONFIG_TSEC3 1
562#define CONFIG_TSEC3_NAME "eTSEC3"
563#define CONFIG_TSEC4 1
564#define CONFIG_TSEC4_NAME "eTSEC4"
565
Liu Yu7e183ca2008-10-10 11:40:59 +0800566#define CONFIG_PIXIS_SGMII_CMD
567#define CONFIG_FSL_SGMII_RISER 1
568#define SGMII_RISER_PHY_OFFSET 0x1c
569
570#ifdef CONFIG_FSL_SGMII_RISER
571#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
572#endif
573
Kumar Gala129ba612008-08-12 11:13:08 -0500574#define TSEC1_PHY_ADDR 0
575#define TSEC2_PHY_ADDR 1
576#define TSEC3_PHY_ADDR 2
577#define TSEC4_PHY_ADDR 3
578
579#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
580#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
581#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
582#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
583
584#define TSEC1_PHYIDX 0
585#define TSEC2_PHYIDX 0
586#define TSEC3_PHYIDX 0
587#define TSEC4_PHYIDX 0
588
589#define CONFIG_ETHPRIME "eTSEC1"
590
591#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
592#endif /* CONFIG_TSEC_ENET */
593
594/*
595 * Environment
596 */
Kumar Galacb14e932010-11-12 08:22:01 -0600597
598#if defined(CONFIG_SYS_RAMBOOT)
599#if defined(CONFIG_RAMBOOT_NAND)
600#define CONFIG_ENV_IS_IN_NAND 1
601#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
602#define CONFIG_ENV_OFFSET ((512 * 1024)\
603 + CONFIG_SYS_NAND_BLOCK_SIZE)
Kumar Gala129ba612008-08-12 11:13:08 -0500604#endif
Kumar Galacb14e932010-11-12 08:22:01 -0600605
606#else
607 #define CONFIG_ENV_IS_IN_FLASH 1
608 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
609 #define CONFIG_ENV_ADDR 0xfff80000
610 #else
611 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
612 #endif
613 #define CONFIG_ENV_SIZE 0x2000
614 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
615#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500616
617#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala129ba612008-08-12 11:13:08 -0500619
620/*
621 * Command line configuration.
622 */
623#include <config_cmd_default.h>
624
York Sun67f94472011-01-26 00:14:57 -0600625#define CONFIG_CMD_ERRATA
Kumar Gala129ba612008-08-12 11:13:08 -0500626#define CONFIG_CMD_IRQ
627#define CONFIG_CMD_PING
628#define CONFIG_CMD_I2C
629#define CONFIG_CMD_MII
630#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500631#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500632#define CONFIG_CMD_REGINFO
Kumar Gala129ba612008-08-12 11:13:08 -0500633
634#if defined(CONFIG_PCI)
635#define CONFIG_CMD_PCI
Kumar Gala129ba612008-08-12 11:13:08 -0500636#define CONFIG_CMD_NET
637#define CONFIG_CMD_SCSI
638#define CONFIG_CMD_EXT2
639#endif
640
Zhao Chenhui863a3ea2011-03-04 16:31:41 +0800641/*
642 * USB
643 */
644#define CONFIG_USB_EHCI
645
646#ifdef CONFIG_USB_EHCI
647#define CONFIG_CMD_USB
648#define CONFIG_USB_EHCI_PCI
649#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
650#define CONFIG_USB_STORAGE
651#define CONFIG_PCI_EHCI_DEVICE 0
652#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
653#endif
654
Kumar Gala129ba612008-08-12 11:13:08 -0500655#undef CONFIG_WATCHDOG /* watchdog disabled */
656
657/*
658 * Miscellaneous configurable options
659 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200660#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500661#define CONFIG_CMDLINE_EDITING /* Command-line editing */
662#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200663#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
664#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Kumar Gala129ba612008-08-12 11:13:08 -0500665#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200666#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500667#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200668#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500669#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200670#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
671#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
672#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
673#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Kumar Gala129ba612008-08-12 11:13:08 -0500674
675/*
676 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500677 * have to be in the first 64 MB of memory, since this is
Kumar Gala129ba612008-08-12 11:13:08 -0500678 * the maximum mapped by the Linux kernel during initialization.
679 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500680#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
681#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala129ba612008-08-12 11:13:08 -0500682
Kumar Gala129ba612008-08-12 11:13:08 -0500683#if defined(CONFIG_CMD_KGDB)
684#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
685#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
686#endif
687
688/*
689 * Environment Configuration
690 */
691
692/* The mac addresses for all ethernet interface */
693#if defined(CONFIG_TSEC_ENET)
694#define CONFIG_HAS_ETH0
695#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
696#define CONFIG_HAS_ETH1
697#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
698#define CONFIG_HAS_ETH2
699#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
700#define CONFIG_HAS_ETH3
701#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
702#endif
703
704#define CONFIG_IPADDR 192.168.1.254
705
706#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000707#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000708#define CONFIG_BOOTFILE "uImage"
Kumar Gala129ba612008-08-12 11:13:08 -0500709#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
710
711#define CONFIG_SERVERIP 192.168.1.1
712#define CONFIG_GATEWAYIP 192.168.1.1
713#define CONFIG_NETMASK 255.255.255.0
714
715/* default location for tftp and bootm */
716#define CONFIG_LOADADDR 1000000
717
718#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
719#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
720
721#define CONFIG_BAUDRATE 115200
722
723#define CONFIG_EXTRA_ENV_SETTINGS \
Hongtao Jia238e1462012-12-20 19:36:12 +0000724"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200725"netdev=eth0\0" \
726"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
727"tftpflash=tftpboot $loadaddr $uboot; " \
728 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
729 " +$filesize; " \
730 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
731 " +$filesize; " \
732 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
733 " $filesize; " \
734 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
735 " +$filesize; " \
736 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
737 " $filesize\0" \
738"consoledev=ttyS0\0" \
739"ramdiskaddr=2000000\0" \
740"ramdiskfile=8572ds/ramdisk.uboot\0" \
741"fdtaddr=c00000\0" \
742"fdtfile=8572ds/mpc8572ds.dtb\0" \
743"bdev=sda3\0"
Kumar Gala129ba612008-08-12 11:13:08 -0500744
745#define CONFIG_HDBOOT \
746 "setenv bootargs root=/dev/$bdev rw " \
747 "console=$consoledev,$baudrate $othbootargs;" \
748 "tftp $loadaddr $bootfile;" \
749 "tftp $fdtaddr $fdtfile;" \
750 "bootm $loadaddr - $fdtaddr"
751
752#define CONFIG_NFSBOOTCOMMAND \
753 "setenv bootargs root=/dev/nfs rw " \
754 "nfsroot=$serverip:$rootpath " \
755 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
756 "console=$consoledev,$baudrate $othbootargs;" \
757 "tftp $loadaddr $bootfile;" \
758 "tftp $fdtaddr $fdtfile;" \
759 "bootm $loadaddr - $fdtaddr"
760
761#define CONFIG_RAMBOOTCOMMAND \
762 "setenv bootargs root=/dev/ram rw " \
763 "console=$consoledev,$baudrate $othbootargs;" \
764 "tftp $ramdiskaddr $ramdiskfile;" \
765 "tftp $loadaddr $bootfile;" \
766 "tftp $fdtaddr $fdtfile;" \
767 "bootm $loadaddr $ramdiskaddr $fdtaddr"
768
769#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
770
771#endif /* __CONFIG_H */