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wdenkc1896002003-12-28 11:44:59 +00001/*
2 * (C) Copyright 2003
wdenkd4ca31c2004-01-02 14:00:00 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
6 *
7 * TOP5200 differences from IceCube:
8 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
9 * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
10 * 1 SDRAM/DDRAM Bank up to 256 MB
11 * local VPD I2C Bus is software driven and uses
12 * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
13 * FLASH is re-located at 0xff000000
14 * Internal regs are at 0xf0000000
wdenkc1896002003-12-28 11:44:59 +000015 * Reset jumps to 0x00000100
16 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020017 * SPDX-License-Identifier: GPL-2.0+
wdenkc1896002003-12-28 11:44:59 +000018 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*
24 * High Level Configuration Options
25 * (easy to change)
26 */
27
wdenkcbd8a352004-02-24 02:00:03 +000028#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
wdenkc1896002003-12-28 11:44:59 +000029#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
30#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
31
Wolfgang Denk2ae18242010-10-06 09:05:45 +020032/*
33 * allowed and functional CONFIG_SYS_TEXT_BASE values:
34 * 0xff000000 low boot at 0x00000100 (default board setting)
35 * 0xfff00000 high boot at 0xfff00100 (board needs modification)
36 * 0x00100000 RAM load and test
37 */
38#define CONFIG_SYS_TEXT_BASE 0xff000000
39
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenkc1896002003-12-28 11:44:59 +000041
Becky Bruce31d82672008-05-08 19:02:12 -050042#define CONFIG_HIGH_BATS 1 /* High BATs supported */
43
wdenkc1896002003-12-28 11:44:59 +000044/*
45 * Serial console configuration
46 */
47#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
48#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkc1896002003-12-28 11:44:59 +000050
51
wdenk4d13cba2004-03-14 14:09:05 +000052#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
wdenkc1896002003-12-28 11:44:59 +000053/*
54 * PCI Mapping:
55 * 0x40000000 - 0x4fffffff - PCI Memory
56 * 0x50000000 - 0x50ffffff - PCI IO Space
57 */
58# define CONFIG_PCI 1
59# define CONFIG_PCI_PNP 1
60# define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050061# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenkc1896002003-12-28 11:44:59 +000062
63# define CONFIG_PCI_MEM_BUS 0x40000000
64# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
65# define CONFIG_PCI_MEM_SIZE 0x10000000
66
67# define CONFIG_PCI_IO_BUS 0x50000000
68# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
69# define CONFIG_PCI_IO_SIZE 0x01000000
70
wdenkc1896002003-12-28 11:44:59 +000071#endif
72
wdenk4d13cba2004-03-14 14:09:05 +000073/* USB */
74#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
75
76# define CONFIG_USB_OHCI
77# define CONFIG_USB_CLOCK 0x0001bbbb
wdenk498b8db2004-04-18 22:26:17 +000078# if defined (CONFIG_EVAL5200)
79# define CONFIG_USB_CONFIG 0x00005100
80# else
81# define CONFIG_USB_CONFIG 0x00001000
82# endif
wdenk4d13cba2004-03-14 14:09:05 +000083# define CONFIG_DOS_PARTITION
84# define CONFIG_USB_STORAGE
85
wdenk4d13cba2004-03-14 14:09:05 +000086#endif
87
88/* IDE */
89#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
wdenk4d13cba2004-03-14 14:09:05 +000090# define CONFIG_DOS_PARTITION
wdenk4d13cba2004-03-14 14:09:05 +000091#endif
92
wdenkc1896002003-12-28 11:44:59 +000093
Jon Loeligerd794cfe2007-07-04 22:31:15 -050094/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050095 * BOOTP options
96 */
97#define CONFIG_BOOTP_BOOTFILESIZE
98#define CONFIG_BOOTP_BOOTPATH
99#define CONFIG_BOOTP_GATEWAY
100#define CONFIG_BOOTP_HOSTNAME
101
102
103/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500104 * Command line configuration.
105 */
106#include <config_cmd_default.h>
107
108#define CONFIG_CMD_ASKENV
109#define CONFIG_CMD_BEDBUG
110#define CONFIG_CMD_DATE
111#define CONFIG_CMD_DHCP
112#define CONFIG_CMD_EEPROM
113#define CONFIG_CMD_ELF
114#define CONFIG_CMD_I2C
115#define CONFIG_CMD_IMMAP
116#define CONFIG_CMD_MII
117#define CONFIG_CMD_REGINFO
118
119#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
120#define CONFIG_CMD_FAT
121#define CONFIG_CMD_IDE
122#define CONFIG_CMD_USB
123#define CONFIG_CMD_PCI
124#endif
125
wdenkc1896002003-12-28 11:44:59 +0000126
127/*
wdenk4d13cba2004-03-14 14:09:05 +0000128 * MUST be low boot - HIGHBOOT is not supported anymore
wdenkd4ca31c2004-01-02 14:00:00 +0000129 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200130#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131# define CONFIG_SYS_LOWBOOT 1
132# define CONFIG_SYS_LOWBOOT16 1
wdenk4d13cba2004-03-14 14:09:05 +0000133#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200134# error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
wdenkd4ca31c2004-01-02 14:00:00 +0000135#endif
136
137/*
wdenkc1896002003-12-28 11:44:59 +0000138 * Autobooting
139 */
140#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkd4ca31c2004-01-02 14:00:00 +0000141
142#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100143 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkd4ca31c2004-01-02 14:00:00 +0000144 "echo"
145
146#undef CONFIG_BOOTARGS
147
148#define CONFIG_EXTRA_ENV_SETTINGS \
149 "netdev=eth0\0" \
150 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100151 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000152 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100153 "addip=setenv bootargs ${bootargs} " \
154 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
155 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000156 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100157 "bootm ${kernel_addr}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000158 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100159 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
160 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000161 "rootpath=/opt/eldk/ppc_82xx\0" \
162 "bootfile=/tftpboot/MPC5200/uImage\0" \
163 ""
164
165#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkc1896002003-12-28 11:44:59 +0000166
167/*
168 * IPB Bus clocking configuration.
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkd4ca31c2004-01-02 14:00:00 +0000171
wdenkc1896002003-12-28 11:44:59 +0000172/*
173 * I2C configuration
174 */
175/*
176 * EEPROM configuration
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
179#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
wdenkc1896002003-12-28 11:44:59 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
182#define CONFIG_SYS_EEPROM_SIZE 0x2000
wdenkd4ca31c2004-01-02 14:00:00 +0000183
wdenkc1896002003-12-28 11:44:59 +0000184#define CONFIG_ENV_OVERWRITE
185#define CONFIG_MISC_INIT_R
wdenkd4ca31c2004-01-02 14:00:00 +0000186
Heiko Schocherea818db2013-01-29 08:53:15 +0100187#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
wdenkd4ca31c2004-01-02 14:00:00 +0000188
Heiko Schocherea818db2013-01-29 08:53:15 +0100189#if defined(CONFIG_SYS_I2C_SOFT)
190# define CONFIG_SYS_I2C
191# define CONFIG_SYS_I2C_SOFT_SPEED 100000
192# define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
193/**/
wdenkc1896002003-12-28 11:44:59 +0000194# define SDA0 0x40
195# define SCL0 0x80
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196# define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
197# define DDR0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
198# define DVO0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
199# define DVI0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
200# define ODE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
wdenkc1896002003-12-28 11:44:59 +0000201# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
202# define I2C_READ ((DVI0&SDA0)?1:0)
203# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
204# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
205# define I2C_DELAY {udelay(5);}
206# define I2C_ACTIVE {DDR0|=SDA0;}
207# define I2C_TRISTATE {DDR0&=~SDA0;}
Heiko Schocherea818db2013-01-29 08:53:15 +0100208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
210#define CONFIG_SYS_I2C_FACT_ADDR 0x57
wdenkc1896002003-12-28 11:44:59 +0000211#endif
wdenkd4ca31c2004-01-02 14:00:00 +0000212
213#if defined (CONFIG_HARD_I2C)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214# define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
215# define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
216# define CONFIG_SYS_I2C_SLAVE 0x7F
217#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
218#define CONFIG_SYS_I2C_FACT_ADDR 0x54
wdenkd4ca31c2004-01-02 14:00:00 +0000219#endif
wdenkc1896002003-12-28 11:44:59 +0000220
221/*
222 * Flash configuration, expect one 16 Megabyte Bank at most
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_FLASH_BASE 0xff000000
225#define CONFIG_SYS_FLASH_SIZE 0x01000000
226#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
227#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0)
wdenkc1896002003-12-28 11:44:59 +0000228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
wdenkc1896002003-12-28 11:44:59 +0000230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
232#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenkc1896002003-12-28 11:44:59 +0000233
234#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
235
wdenkd4ca31c2004-01-02 14:00:00 +0000236/*
237 * DRAM configuration - will be read from VPD later... TODO!
238 */
239#if 0
240/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_DRAM_DDR 0
242#define CONFIG_SYS_DRAM_EMODE 0
243#define CONFIG_SYS_DRAM_MODE 0x008D
244#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
245#define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00
246#define CONFIG_SYS_DRAM_CONFIG2 0x88B70004
247#define CONFIG_SYS_DRAM_TAP_DEL 0x08
248#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
wdenkd4ca31c2004-01-02 14:00:00 +0000249#endif
250#if 1
251/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_DRAM_DDR 0
253#define CONFIG_SYS_DRAM_EMODE 0
254#define CONFIG_SYS_DRAM_MODE 0x00CD
255#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
256#define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00
257#define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004
258#define CONFIG_SYS_DRAM_TAP_DEL 0x08
259#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
wdenkd4ca31c2004-01-02 14:00:00 +0000260#endif
261
wdenkc1896002003-12-28 11:44:59 +0000262/*
263 * Environment settings
264 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200265#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200266#define CONFIG_ENV_OFFSET 0x1000
267#define CONFIG_ENV_SIZE 0x0700
wdenkc1896002003-12-28 11:44:59 +0000268
wdenkd4ca31c2004-01-02 14:00:00 +0000269/*
270 * VPD settings
271 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_FACT_OFFSET 0x1800
273#define CONFIG_SYS_FACT_SIZE 0x0800
wdenkd4ca31c2004-01-02 14:00:00 +0000274
wdenkc1896002003-12-28 11:44:59 +0000275/*
wdenkd4ca31c2004-01-02 14:00:00 +0000276 * Memory map
277 *
278 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
wdenkc1896002003-12-28 11:44:59 +0000279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
281#define CONFIG_SYS_SDRAM_BASE 0x00000000
282#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
wdenkc1896002003-12-28 11:44:59 +0000283
284/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200286#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
wdenkc1896002003-12-28 11:44:59 +0000287
288
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200289#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc1896002003-12-28 11:44:59 +0000291
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200292#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
294# define CONFIG_SYS_RAMBOOT 1
wdenkc1896002003-12-28 11:44:59 +0000295#endif
296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
298#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
299#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc1896002003-12-28 11:44:59 +0000300
301/*
302 * Ethernet configuration
303 */
wdenkcbd8a352004-02-24 02:00:03 +0000304#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800305#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */
wdenkd4ca31c2004-01-02 14:00:00 +0000306#define CONFIG_PHY_ADDR 0x1f
wdenkc1896002003-12-28 11:44:59 +0000307#define CONFIG_PHY_TYPE 0x79c874
308/*
wdenkd4ca31c2004-01-02 14:00:00 +0000309 * GPIO configuration:
310 * PSC1,2,3 predefined as UART
311 * PCI disabled
wdenkc1896002003-12-28 11:44:59 +0000312 * Ethernet 100 with MD
313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044
wdenkc1896002003-12-28 11:44:59 +0000315
316/*
317 * Miscellaneous configurable options
318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_LONGHELP /* undef to save memory */
320#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500321#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc1896002003-12-28 11:44:59 +0000323#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc1896002003-12-28 11:44:59 +0000325#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
327#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
328#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc1896002003-12-28 11:44:59 +0000329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
331#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
wdenkc1896002003-12-28 11:44:59 +0000332
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
wdenkc1896002003-12-28 11:44:59 +0000334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc1896002003-12-28 11:44:59 +0000336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500338#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500340#endif
341
342
wdenk63e73c92004-02-23 22:22:28 +0000343#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
344 #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
345 #define RTC(reg) (0xf0010000+reg)
346 /* setup CS2 for M48T08. Must MAP 64kB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347 #define CONFIG_SYS_CS2_START RTC(0)
348 #define CONFIG_SYS_CS2_SIZE 0x10000
wdenk63e73c92004-02-23 22:22:28 +0000349 /* setup CS2 configuration register: */
350 /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
351 /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352 #define CONFIG_SYS_CS2_CFG 0x00047800
wdenk63e73c92004-02-23 22:22:28 +0000353#else
354 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
355#endif
wdenk1c437712004-01-16 00:30:56 +0000356
wdenkc1896002003-12-28 11:44:59 +0000357/*
358 * Various low-level settings
359 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
361#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenkc1896002003-12-28 11:44:59 +0000362
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
364#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
365#define CONFIG_SYS_BOOTCS_CFG 0x00047801
366#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
367#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
wdenkc1896002003-12-28 11:44:59 +0000368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_CS_BURST 0x00000000
370#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenkc1896002003-12-28 11:44:59 +0000371
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_RESET_ADDRESS 0x7f000000
wdenkc1896002003-12-28 11:44:59 +0000373
wdenk4d13cba2004-03-14 14:09:05 +0000374/*-----------------------------------------------------------------------
375 * IDE/ATA stuff Supports IDE harddisk
376 *-----------------------------------------------------------------------
377 */
378
379#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
380
381#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
382#undef CONFIG_IDE_LED /* LED for ide not supported */
383
384#define CONFIG_IDE_RESET 1
385#define CONFIG_IDE_PREINIT
386
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
388#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk4d13cba2004-03-14 14:09:05 +0000389
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk4d13cba2004-03-14 14:09:05 +0000391
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
wdenk4d13cba2004-03-14 14:09:05 +0000393
394/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
wdenk4d13cba2004-03-14 14:09:05 +0000396
397/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
wdenk4d13cba2004-03-14 14:09:05 +0000399
400/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_ATA_ALT_OFFSET (0x005c)
wdenk4d13cba2004-03-14 14:09:05 +0000402
403/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_ATA_STRIDE 4
wdenk4d13cba2004-03-14 14:09:05 +0000405
wdenkc1896002003-12-28 11:44:59 +0000406#endif /* __CONFIG_H */