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wdenkf12e5682003-07-07 20:07:54 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf12e5682003-07-07 20:07:54 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
21#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
22
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0x40000000
24
wdenkf12e5682003-07-07 20:07:54 +000025#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020026#define CONFIG_SYS_SMC_RXBUFLEN 128
27#define CONFIG_SYS_MAXIDLE 10
wdenkf12e5682003-07-07 20:07:54 +000028#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
29
wdenkae3af052003-08-07 22:18:11 +000030#define CONFIG_BOOTCOUNT_LIMIT
wdenkf12e5682003-07-07 20:07:54 +000031
wdenkae3af052003-08-07 22:18:11 +000032#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000033
34#define CONFIG_BOARD_TYPES 1 /* support board types */
35
36#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010037 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkf12e5682003-07-07 20:07:54 +000038 "echo"
39
40#undef CONFIG_BOOTARGS
41
42#define CONFIG_EXTRA_ENV_SETTINGS \
43 "netdev=eth0\0" \
44 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010045 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000046 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010047 "addip=setenv bootargs ${bootargs} " \
48 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
49 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000050 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010051 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000052 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010053 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
54 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000055 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020056 "hostname=TQM855M\0" \
57 "bootfile=TQM855M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020058 "fdt_addr=40080000\0" \
59 "kernel_addr=400A0000\0" \
60 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020061 "u-boot=TQM855M/u-image.bin\0" \
62 "load=tftp 200000 ${u-boot}\0" \
63 "update=prot off 40000000 +${filesize};" \
64 "era 40000000 +${filesize};" \
65 "cp.b 200000 40000000 ${filesize};" \
66 "sete filesize;save\0" \
wdenkf12e5682003-07-07 20:07:54 +000067 ""
68#define CONFIG_BOOTCOMMAND "run flash_self"
69
70#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf12e5682003-07-07 20:07:54 +000072
73#undef CONFIG_WATCHDOG /* watchdog disabled */
74
75#define CONFIG_STATUS_LED 1 /* Status LED enabled */
76
77#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
78
wdenkd4ca31c2004-01-02 14:00:00 +000079/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010080#define CONFIG_SYS_I2C
81#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
82#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
83#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
wdenkd4ca31c2004-01-02 14:00:00 +000084/*
85 * Software (bit-bang) I2C driver configuration
86 */
87#define PB_SCL 0x00000020 /* PB 26 */
88#define PB_SDA 0x00000010 /* PB 27 */
89
90#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
91#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
92#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
93#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
94#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
95 else immr->im_cpm.cp_pbdat &= ~PB_SDA
96#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
97 else immr->im_cpm.cp_pbdat &= ~PB_SCL
98#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
wdenkd4ca31c2004-01-02 14:00:00 +000099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
101#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
wdenkd4ca31c2004-01-02 14:00:00 +0000102#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
104#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
105#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
wdenkd4ca31c2004-01-02 14:00:00 +0000106#endif
107
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500108/*
109 * BOOTP options
110 */
111#define CONFIG_BOOTP_SUBNETMASK
112#define CONFIG_BOOTP_GATEWAY
113#define CONFIG_BOOTP_HOSTNAME
114#define CONFIG_BOOTP_BOOTPATH
115#define CONFIG_BOOTP_BOOTFILESIZE
116
wdenkf12e5682003-07-07 20:07:54 +0000117
118#define CONFIG_MAC_PARTITION
119#define CONFIG_DOS_PARTITION
120
121#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
122
wdenkf12e5682003-07-07 20:07:54 +0000123
Jon Loeliger26946902007-07-04 22:30:50 -0500124/*
125 * Command line configuration.
126 */
127#include <config_cmd_default.h>
128
129#define CONFIG_CMD_ASKENV
130#define CONFIG_CMD_DATE
131#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200132#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100133#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500134#define CONFIG_CMD_EEPROM
135#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200136#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500137#define CONFIG_CMD_NFS
138#define CONFIG_CMD_SNTP
139
wdenkf12e5682003-07-07 20:07:54 +0000140
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200141#define CONFIG_NETCONSOLE
142
143
wdenkf12e5682003-07-07 20:07:54 +0000144/*
145 * Miscellaneous configurable options
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_LONGHELP /* undef to save memory */
148#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkf12e5682003-07-07 20:07:54 +0000149
Wolfgang Denk2751a952006-10-28 02:29:14 +0200150#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf12e5682003-07-07 20:07:54 +0000152
Jon Loeliger26946902007-07-04 22:30:50 -0500153#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000155#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000157#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
159#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
160#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
163#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf12e5682003-07-07 20:07:54 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf12e5682003-07-07 20:07:54 +0000166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf12e5682003-07-07 20:07:54 +0000168
wdenkf12e5682003-07-07 20:07:54 +0000169/*
170 * Low Level Configuration Settings
171 * (address mappings, register initial values, etc.)
172 * You should know what you are doing if you make changes here.
173 */
174/*-----------------------------------------------------------------------
175 * Internal Memory Mapped Register
176 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf12e5682003-07-07 20:07:54 +0000178
179/*-----------------------------------------------------------------------
180 * Definitions for initial stack pointer and data area (in DPRAM)
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200183#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200184#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf12e5682003-07-07 20:07:54 +0000186
187/*-----------------------------------------------------------------------
188 * Start addresses for the final memory configuration
189 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf12e5682003-07-07 20:07:54 +0000191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_SDRAM_BASE 0x00000000
193#define CONFIG_SYS_FLASH_BASE 0x40000000
194#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
195#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
196#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf12e5682003-07-07 20:07:54 +0000197
198/*
199 * For booting Linux, the board info and command line data
200 * have to be in the first 8 MB of memory, since this is
201 * the maximum mapped by the Linux kernel during initialization.
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf12e5682003-07-07 20:07:54 +0000204
205/*-----------------------------------------------------------------------
206 * FLASH organization
207 */
wdenkf12e5682003-07-07 20:07:54 +0000208
Martin Krausee318d9e2007-09-27 11:10:08 +0200209/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200211#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
213#define CONFIG_SYS_FLASH_EMPTY_INFO
214#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
215#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
216#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000217
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200218#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200219#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
220#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
221#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenkf12e5682003-07-07 20:07:54 +0000222
223/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200224#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
225#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf12e5682003-07-07 20:07:54 +0000226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200228
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200229#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
230
wdenkf12e5682003-07-07 20:07:54 +0000231/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200232 * Dynamic MTD partition support
233 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100234#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200235#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
236#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200237#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
238
239#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
240 "128k(dtb)," \
241 "1920k(kernel)," \
242 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200243 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200244
245/*-----------------------------------------------------------------------
wdenkf12e5682003-07-07 20:07:54 +0000246 * Hardware Information Block
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
249#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
250#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf12e5682003-07-07 20:07:54 +0000251
252/*-----------------------------------------------------------------------
253 * Cache Configuration
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500256#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf12e5682003-07-07 20:07:54 +0000258#endif
259
260/*-----------------------------------------------------------------------
261 * SYPCR - System Protection Control 11-9
262 * SYPCR can only be written once after reset!
263 *-----------------------------------------------------------------------
264 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
265 */
266#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf12e5682003-07-07 20:07:54 +0000268 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
269#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf12e5682003-07-07 20:07:54 +0000271#endif
272
273/*-----------------------------------------------------------------------
274 * SIUMCR - SIU Module Configuration 11-6
275 *-----------------------------------------------------------------------
276 * PCMCIA config., multi-function pin tri-state
277 */
278#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000280#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000282#endif /* CONFIG_CAN_DRIVER */
283
284/*-----------------------------------------------------------------------
285 * TBSCR - Time Base Status and Control 11-26
286 *-----------------------------------------------------------------------
287 * Clear Reference Interrupt Status, Timebase freezing enabled
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf12e5682003-07-07 20:07:54 +0000290
291/*-----------------------------------------------------------------------
292 * RTCSC - Real-Time Clock Status and Control Register 11-27
293 *-----------------------------------------------------------------------
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf12e5682003-07-07 20:07:54 +0000296
297/*-----------------------------------------------------------------------
298 * PISCR - Periodic Interrupt Status and Control 11-31
299 *-----------------------------------------------------------------------
300 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf12e5682003-07-07 20:07:54 +0000303
304/*-----------------------------------------------------------------------
305 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
306 *-----------------------------------------------------------------------
307 * Reset PLL lock status sticky bit, timer expired status bit and timer
308 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000309 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000311
312/*-----------------------------------------------------------------------
313 * SCCR - System Clock and reset Control Register 15-27
314 *-----------------------------------------------------------------------
315 * Set clock output, timebase and RTC source and divider,
316 * power management and some other internal clocks
317 */
318#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000320 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
321 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000322
323/*-----------------------------------------------------------------------
324 * PCMCIA stuff
325 *-----------------------------------------------------------------------
326 *
327 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
329#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
330#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
331#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
332#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
333#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
334#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
335#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf12e5682003-07-07 20:07:54 +0000336
337/*-----------------------------------------------------------------------
338 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
339 *-----------------------------------------------------------------------
340 */
341
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000342#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf12e5682003-07-07 20:07:54 +0000343#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
344
345#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
346#undef CONFIG_IDE_LED /* LED for ide not supported */
347#undef CONFIG_IDE_RESET /* reset for ide not supported */
348
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
350#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf12e5682003-07-07 20:07:54 +0000351
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf12e5682003-07-07 20:07:54 +0000353
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf12e5682003-07-07 20:07:54 +0000355
356/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000358
359/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000361
362/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf12e5682003-07-07 20:07:54 +0000364
365/*-----------------------------------------------------------------------
366 *
367 *-----------------------------------------------------------------------
368 *
369 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_DER 0
wdenkf12e5682003-07-07 20:07:54 +0000371
372/*
373 * Init Memory Controller:
374 *
375 * BR0/1 and OR0/1 (FLASH)
376 */
377
378#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
379#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
380
381/* used to re-map FLASH both when starting from SRAM or FLASH:
382 * restrict access enough to keep SRAM working (if any)
383 * but not too much to meddle with FLASH accesses
384 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
386#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf12e5682003-07-07 20:07:54 +0000387
388/*
389 * FLASH timing:
390 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf12e5682003-07-07 20:07:54 +0000392 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000393
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
395#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
396#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000397
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
399#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
400#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000401
402/*
403 * BR2/3 and OR2/3 (SDRAM)
404 *
405 */
406#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
407#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
408#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
409
410/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf12e5682003-07-07 20:07:54 +0000412
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
414#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000415
416#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
418#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000419#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
421#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
422#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
423#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf12e5682003-07-07 20:07:54 +0000424 BR_PS_8 | BR_MS_UPMB | BR_V )
425#endif /* CONFIG_CAN_DRIVER */
426
427/*
428 * Memory Periodic Timer Prescaler
429 *
430 * The Divider for PTA (refresh timer) configuration is based on an
431 * example SDRAM configuration (64 MBit, one bank). The adjustment to
432 * the number of chip selects (NCS) and the actually needed refresh
433 * rate is done by setting MPTPR.
434 *
435 * PTA is calculated from
436 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
437 *
438 * gclk CPU clock (not bus clock!)
439 * Trefresh Refresh cycle * 4 (four word bursts used)
440 *
441 * 4096 Rows from SDRAM example configuration
442 * 1000 factor s -> ms
443 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
444 * 4 Number of refresh cycles per period
445 * 64 Refresh cycle in ms per number of rows
446 * --------------------------------------------
447 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
448 *
449 * 50 MHz => 50.000.000 / Divider = 98
450 * 66 Mhz => 66.000.000 / Divider = 129
451 * 80 Mhz => 80.000.000 / Divider = 156
452 */
wdenke9132ea2004-04-24 23:23:30 +0000453
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
455#define CONFIG_SYS_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000456
457/*
458 * For 16 MBit, refresh rates could be 31.3 us
459 * (= 64 ms / 2K = 125 / quad bursts).
460 * For a simpler initialization, 15.6 us is used instead.
461 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
463 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf12e5682003-07-07 20:07:54 +0000464 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
466#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000467
468/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
470#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000471
472/*
473 * MAMR settings for SDRAM
474 */
475
476/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000478 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
479 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
480/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000482 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
483 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
484
wdenkf12e5682003-07-07 20:07:54 +0000485#define CONFIG_SCC1_ENET
486#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200487#define CONFIG_ETHPRIME "SCC"
wdenkf12e5682003-07-07 20:07:54 +0000488
Heiko Schocher7026ead2010-02-09 15:50:27 +0100489/* pass open firmware flat tree */
490#define CONFIG_OF_LIBFDT 1
491#define CONFIG_OF_BOARD_SETUP 1
492#define CONFIG_HWCONFIG 1
493
wdenkf12e5682003-07-07 20:07:54 +0000494#endif /* __CONFIG_H */