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wdenk15647dc2003-10-09 19:00:25 +00001/*
2 * (C) Copyright 2001, 2002
3 * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk15647dc2003-10-09 19:00:25 +00006 */
7
8/* ------------------------------------------------------------------------- */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Wolfgang Denk2ae18242010-10-06 09:05:45 +020017#define CONFIG_SYS_TEXT_BASE 0xFFF00000
18
wdenk15647dc2003-10-09 19:00:25 +000019/* Environments */
20
21/* bootargs */
22#define CONFIG_BOOTARGS \
23 "console=ttyS0,9600 init=/linuxrc " \
24 "root=/dev/nfs rw nfsroot=192.168.0.1:" \
25 "/tftpboot/target " \
26 "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
27 "255.255.255.0:debris:eth0:none " \
28 "mtdparts=phys:12m(root),-(kernel)"
29
30/* bootcmd */
31#define CONFIG_BOOTCOMMAND \
32 "tftp 800000 pImage; " \
33 "setenv bootargs console=ttyS0,9600 init=/linuxrc " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010034 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
35 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
36 "${netmask}:${hostname}:eth0:none " \
wdenk15647dc2003-10-09 19:00:25 +000037 "mtdparts=phys:12m(root),-(kernel); " \
38 "bootm 800000"
39
40/* bootdelay */
41#define CONFIG_BOOTDELAY 5 /* autoboot 5s */
42
43/* baudrate */
44#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
45
46/* loads_echo */
47#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
48
49/* ethaddr */
50#undef CONFIG_ETHADDR
51
52/* eth2addr */
53#undef CONFIG_ETH2ADDR
54
55/* eth3addr */
56#undef CONFIG_ETH3ADDR
57
58/* ipaddr */
59#define CONFIG_IPADDR 192.168.0.2
60
61/* serverip */
62#define CONFIG_SERVERIP 192.168.0.1
63
64/* autoload */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#undef CONFIG_SYS_AUTOLOAD
wdenk15647dc2003-10-09 19:00:25 +000066
67/* rootpath */
Joe Hershberger8b3637c2011-10-13 13:03:47 +000068#define CONFIG_ROOTPATH "/tftpboot/target"
wdenk15647dc2003-10-09 19:00:25 +000069
70/* gatewayip */
71#define CONFIG_GATEWAYIP 192.168.0.1
72
73/* netmask */
74#define CONFIG_NETMASK 255.255.255.0
75
76/* hostname */
77#define CONFIG_HOSTNAME debris
78
79/* bootfile */
Joe Hershbergerb3f44c22011-10-13 13:03:48 +000080#define CONFIG_BOOTFILE "pImage"
wdenk15647dc2003-10-09 19:00:25 +000081
82/* loadaddr */
83#define CONFIG_LOADADDR 800000
84
85/* preboot */
86#undef CONFIG_PREBOOT
87
88/* clocks_in_mhz */
89#undef CONFIG_CLOCKS_IN_MHZ
90
91
92/*
93 * High Level Configuration Options
94 * (easy to change)
95 */
96
97#define CONFIG_MPC824X 1
98#define CONFIG_MPC8245 1
99#define CONFIG_DEBRIS 1
100
101#if 0
102#define USE_DINK32 1
103#else
104#undef USE_DINK32
105#endif
106
107#define CONFIG_CONS_INDEX 1
108#define CONFIG_BAUDRATE 9600
109#define CONFIG_DRAM_SPEED 100 /* MHz */
110
Jon Loeligerab999ba2007-07-04 22:32:03 -0500111
112/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500113 * BOOTP options
114 */
115#define CONFIG_BOOTP_BOOTFILESIZE
116#define CONFIG_BOOTP_BOOTPATH
117#define CONFIG_BOOTP_GATEWAY
118#define CONFIG_BOOTP_HOSTNAME
119
120
121/*
Jon Loeligerab999ba2007-07-04 22:32:03 -0500122 * Command line configuration.
123 */
124#include <config_cmd_default.h>
125
126#define CONFIG_CMD_ASKENV
127#define CONFIG_CMD_CACHE
128#define CONFIG_CMD_DATE
129#define CONFIG_CMD_DHCP
130#define CONFIG_CMD_DIAG
131#define CONFIG_CMD_EEPROM
132#define CONFIG_CMD_ELF
133#define CONFIG_CMD_I2C
134#define CONFIG_CMD_JFFS2
Marek Vasutd060b002012-03-31 07:47:12 +0000135#define CONFIG_CMD_KGDB
Jon Loeligerab999ba2007-07-04 22:32:03 -0500136#define CONFIG_CMD_PCI
137#define CONFIG_CMD_PING
138#define CONFIG_CMD_SAVES
139#define CONFIG_CMD_SDRAM
wdenk15647dc2003-10-09 19:00:25 +0000140
141
142/*
143 * Miscellaneous configurable options
144 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
146#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
147#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
148#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
149#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
151#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
152#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk15647dc2003-10-09 19:00:25 +0000153
154/*-----------------------------------------------------------------------
155 * PCI stuff
156 *-----------------------------------------------------------------------
157 */
158#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000159#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenk15647dc2003-10-09 19:00:25 +0000160#define CONFIG_PCI_PNP
161
wdenk15647dc2003-10-09 19:00:25 +0000162#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk15647dc2003-10-09 19:00:25 +0000164#define CONFIG_EEPRO100_SROM_WRITE
165
166#define PCI_ENET0_IOADDR 0x80000000
167#define PCI_ENET0_MEMADDR 0x80000000
168#define PCI_ENET1_IOADDR 0x81000000
169#define PCI_ENET1_MEMADDR 0x81000000
170/*-----------------------------------------------------------------------
171 * Start addresses for the final memory configuration
172 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk15647dc2003-10-09 19:00:25 +0000174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_SDRAM_BASE 0x00000000
176#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
wdenk7abf0c52004-04-18 21:45:42 +0000177#define CONFIG_VERY_BIG_RAM
wdenk15647dc2003-10-09 19:00:25 +0000178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenk15647dc2003-10-09 19:00:25 +0000180
181#if defined (USE_DINK32)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_MONITOR_LEN 0x00040000
183#define CONFIG_SYS_MONITOR_BASE 0x00090000
184#define CONFIG_SYS_RAMBOOT 1
185#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Wolfgang Denk553f0982010-10-26 13:32:32 +0200186#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200187#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk15647dc2003-10-09 19:00:25 +0000189#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#undef CONFIG_SYS_RAMBOOT
191#define CONFIG_SYS_MONITOR_LEN 0x00040000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200192#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenk15647dc2003-10-09 19:00:25 +0000193
wdenk15647dc2003-10-09 19:00:25 +0000194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200196#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200197#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk15647dc2003-10-09 19:00:25 +0000198
199#endif
200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_FLASH_BASE 0x7C000000
202#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */
wdenk15647dc2003-10-09 19:00:25 +0000203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
wdenk15647dc2003-10-09 19:00:25 +0000205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
207#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
wdenk15647dc2003-10-09 19:00:25 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenk15647dc2003-10-09 19:00:25 +0000210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
212#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
wdenk15647dc2003-10-09 19:00:25 +0000213#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */
214
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200215/*
216 * JFFS2 partitions
217 *
218 */
219/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100220#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200221#define CONFIG_JFFS2_DEV "nor0"
222#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
223#define CONFIG_JFFS2_PART_OFFSET 0x00000000
224
225/* mtdparts command line support */
226
227/* Use first bank for JFFS2, second bank contains U-Boot.
228 *
229 * Note: fake mtd_id's used, no linux mtd map file.
230 */
231/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100232#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200233#define MTDIDS_DEFAULT "nor0=debris-0"
234#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)"
235*/
wdenk15647dc2003-10-09 19:00:25 +0000236
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200237#define CONFIG_ENV_IS_IN_NVRAM 1
wdenk15647dc2003-10-09 19:00:25 +0000238#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200240#define CONFIG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */
241#define CONFIG_ENV_SIZE 0x400 /* Size of the Environment - 8K */
242#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
wdenk15647dc2003-10-09 19:00:25 +0000243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_NVRAM_BASE_ADDR 0xff000000
wdenk15647dc2003-10-09 19:00:25 +0000245
246/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
wdenk15647dc2003-10-09 19:00:25 +0000248 * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900
wdenk15647dc2003-10-09 19:00:25 +0000251
252/*
253 * select i2c support configuration
254 *
255 * Supported configurations are {none, software, hardware} drivers.
256 * If the software driver is chosen, there are some additional
257 * configuration items that the driver uses to drive the port pins.
258 */
259#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Heiko Schocherea818db2013-01-29 08:53:15 +0100260#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
262#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk15647dc2003-10-09 19:00:25 +0000263
Heiko Schocherea818db2013-01-29 08:53:15 +0100264#ifdef CONFIG_SYS_I2C_SOFT
wdenk15647dc2003-10-09 19:00:25 +0000265#error "Soft I2C is not configured properly. Please review!"
Heiko Schocherea818db2013-01-29 08:53:15 +0100266#define CONFIG_SYS_I2C
267#define CONFIG_SYS_I2C_SOFT_SPEED 50000
268#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
wdenk15647dc2003-10-09 19:00:25 +0000269#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
270#define I2C_ACTIVE (iop->pdir |= 0x00010000)
271#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
272#define I2C_READ ((iop->pdat & 0x00010000) != 0)
273#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
274 else iop->pdat &= ~0x00010000
275#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
276 else iop->pdat &= ~0x00020000
277#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
Heiko Schocherea818db2013-01-29 08:53:15 +0100278#endif /* CONFIG_SYS_I2C_SOFT */
wdenk15647dc2003-10-09 19:00:25 +0000279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
281#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
282#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
283#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk15647dc2003-10-09 19:00:25 +0000284
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
wdenk15647dc2003-10-09 19:00:25 +0000286
287/*-----------------------------------------------------------------------
288 * Definitions for initial stack pointer and data area (in DPRAM)
289 */
290
291/*
292 * NS16550 Configuration
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_NS16550
295#define CONFIG_SYS_NS16550_SERIAL
wdenk15647dc2003-10-09 19:00:25 +0000296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenk15647dc2003-10-09 19:00:25 +0000298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_NS16550_CLK 7372800
wdenk15647dc2003-10-09 19:00:25 +0000300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_NS16550_COM1 0xFF080000
302#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8)
303#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16)
304#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24)
wdenk15647dc2003-10-09 19:00:25 +0000305
306/*
307 * Low Level Configuration Settings
308 * (address mappings, register initial values, etc.)
309 * You should know what you are doing if you make changes here.
310 */
311
312#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
313#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
314
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_DLL_EXTEND 0x00
316#define CONFIG_SYS_PCI_HOLD_DEL 0x20
wdenk15647dc2003-10-09 19:00:25 +0000317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_ROMNAL 15 /* rom/flash next access time */
319#define CONFIG_SYS_ROMFAL 31 /* rom/flash access time */
wdenk15647dc2003-10-09 19:00:25 +0000320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_REFINT 430 /* # of clocks between CBR refresh cycles */
wdenk15647dc2003-10-09 19:00:25 +0000322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
wdenk15647dc2003-10-09 19:00:25 +0000324
325/* the following are for SDRAM only*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
327#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
328#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
329#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
330#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
331#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
332#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
333#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
wdenk15647dc2003-10-09 19:00:25 +0000334#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
wdenk15647dc2003-10-09 19:00:25 +0000336#endif
337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
339#define CONFIG_SYS_EXTROM 1
340#define CONFIG_SYS_REGDIMM 0
wdenk15647dc2003-10-09 19:00:25 +0000341
342
343/* memory bank settings*/
344/*
345 * only bits 20-29 are actually used from these vales to set the
346 * start/end address the upper two bits will be 0, and the lower 20
347 * bits will be set to 0x00000 for a start address, or 0xfffff for an
348 * end address
349 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_BANK0_START 0x00000000
351#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
352#define CONFIG_SYS_BANK0_ENABLE 1
353#define CONFIG_SYS_BANK1_START 0x04000000
354#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
355#define CONFIG_SYS_BANK1_ENABLE 1
356#define CONFIG_SYS_BANK2_START 0x3ff00000
357#define CONFIG_SYS_BANK2_END 0x3fffffff
358#define CONFIG_SYS_BANK2_ENABLE 0
359#define CONFIG_SYS_BANK3_START 0x3ff00000
360#define CONFIG_SYS_BANK3_END 0x3fffffff
361#define CONFIG_SYS_BANK3_ENABLE 0
362#define CONFIG_SYS_BANK4_START 0x00000000
363#define CONFIG_SYS_BANK4_END 0x00000000
364#define CONFIG_SYS_BANK4_ENABLE 0
365#define CONFIG_SYS_BANK5_START 0x00000000
366#define CONFIG_SYS_BANK5_END 0x00000000
367#define CONFIG_SYS_BANK5_ENABLE 0
368#define CONFIG_SYS_BANK6_START 0x00000000
369#define CONFIG_SYS_BANK6_END 0x00000000
370#define CONFIG_SYS_BANK6_ENABLE 0
371#define CONFIG_SYS_BANK7_START 0x00000000
372#define CONFIG_SYS_BANK7_END 0x00000000
373#define CONFIG_SYS_BANK7_ENABLE 0
wdenk15647dc2003-10-09 19:00:25 +0000374/*
375 * Memory bank enable bitmask, specifying which of the banks defined above
376 are actually present. MSB is for bank #7, LSB is for bank #0.
377 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_BANK_ENABLE 0x01
wdenk15647dc2003-10-09 19:00:25 +0000379
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_ODCR 0x75 /* configures line driver impedances, */
wdenk15647dc2003-10-09 19:00:25 +0000381 /* see 8240 book for bit definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
wdenk15647dc2003-10-09 19:00:25 +0000383 /* currently accessed page in memory */
384 /* see 8240 book for details */
385
386/* SDRAM 0 - 256MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
388#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk15647dc2003-10-09 19:00:25 +0000389
390/* stack in DCACHE @ 1GB (no backing mem) */
391#if defined(USE_DINK32)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
393#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
wdenk15647dc2003-10-09 19:00:25 +0000394#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
396#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenk15647dc2003-10-09 19:00:25 +0000397#endif
398
399/* PCI memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
401#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk15647dc2003-10-09 19:00:25 +0000402
403/* Flash, config addrs, etc */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
405#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk15647dc2003-10-09 19:00:25 +0000406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
408#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
409#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
410#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
411#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
412#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
413#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
414#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenk15647dc2003-10-09 19:00:25 +0000415
416/*
417 * For booting Linux, the board info and command line data
418 * have to be in the first 8 MB of memory, since this is
419 * the maximum mapped by the Linux kernel during initialization.
420 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk15647dc2003-10-09 19:00:25 +0000422/*-----------------------------------------------------------------------
423 * FLASH organization
424 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
426#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk15647dc2003-10-09 19:00:25 +0000427
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
429#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk15647dc2003-10-09 19:00:25 +0000430
431/*-----------------------------------------------------------------------
432 * Cache Configuration
433 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
Jon Loeligerab999ba2007-07-04 22:32:03 -0500435#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk15647dc2003-10-09 19:00:25 +0000437#endif
438
wdenk15647dc2003-10-09 19:00:25 +0000439/* values according to the manual */
440
441#define CONFIG_DRAM_50MHZ 1
442#define CONFIG_SDRAM_50MHZ
443
444#define CONFIG_DISK_SPINUP_TIME 1000000
445
446#endif /* __CONFIG_H */