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Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +01001/*
2 * ti_omap3_common.h
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * For more details, please see the technical documents listed at
9 * http://www.ti.com/product/omap3530
10 * http://www.ti.com/product/omap3630
11 * http://www.ti.com/product/dm3730
12 */
13
14#ifndef __CONFIG_TI_OMAP3_COMMON_H__
15#define __CONFIG_TI_OMAP3_COMMON_H__
16
Albert ARIBAUD37098442016-01-27 08:46:11 +010017/*
18 * High Level Configuration Options
19 */
20
Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +010021#include <asm/arch/cpu.h>
Nishanth Menon987ec582015-03-09 17:12:04 -050022#include <asm/arch/omap.h>
Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +010023
Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +010024/* Clock Defines */
25#define V_OSCK 26000000 /* Clock output from T2 */
26#define V_SCLK (V_OSCK >> 1)
27
28/* NS16550 Configuration */
29#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
Thomas Chouc7b96862015-11-19 21:48:12 +080030#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
Simon Glassb3f4ca12014-10-22 21:37:15 -060031#ifdef CONFIG_SPL_BUILD
32# define CONFIG_SYS_NS16550_SERIAL
33# define CONFIG_SYS_NS16550_REG_SIZE (-4)
Simon Glassb3f4ca12014-10-22 21:37:15 -060034#endif
Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +010035#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
36 115200}
37
38/* Select serial console configuration */
39#define CONFIG_CONS_INDEX 3
Simon Glassb3f4ca12014-10-22 21:37:15 -060040#ifdef CONFIG_SPL_BUILD
Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +010041#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
42#define CONFIG_SERIAL3 3
Simon Glassb3f4ca12014-10-22 21:37:15 -060043#endif
Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +010044
45/* Physical Memory Map */
46#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
47#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
48
49/*
50 * OMAP3 has 12 GP timers, they can be driven by the system clock
51 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
52 * This rate is divided by a local divisor.
53 */
54#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
55
56#define CONFIG_SYS_MONITOR_LEN (256 << 10)
57
Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +010058/* SPL */
59#define CONFIG_SPL_TEXT_BASE 0x40200800
Tom Rinid3289aa2014-04-03 07:52:53 -040060#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
61 (64 << 20))
62
Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +010063#ifdef CONFIG_NAND
Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +010064#define CONFIG_SPL_NAND_SIMPLE
Tom Rinidf4dbb52014-04-03 15:17:15 -040065#define CONFIG_SYS_NAND_BASE 0x30000000
Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +010066#endif
67
68/* Now bring in the rest of the common code. */
Nishanth Menon9a0f4002015-07-22 18:05:41 -050069#include <configs/ti_armv7_omap.h>
Enric Balletbò i Serrac7964f82013-12-06 21:30:23 +010070
71#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */