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wdenk42d1f032003-10-15 23:53:47 +00001/*
Dipen Dudhatbeba93e2011-01-19 12:46:27 +05302 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +000010 */
11
Andy Fleming75b9d4a2008-08-31 16:33:26 -050012#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000013#include <common.h>
14#include <watchdog.h>
15#include <command.h>
Andy Fleming80522dc2008-10-30 16:51:33 -050016#include <fsl_esdhc.h>
wdenk42d1f032003-10-15 23:53:47 +000017#include <asm/cache.h>
Sergei Poselenov740280e2008-06-06 15:42:40 +020018#include <asm/io.h>
Becky Bruce199e2622010-06-17 11:37:25 -050019#include <asm/mmu.h>
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053020#include <asm/fsl_ifc.h>
Becky Bruce199e2622010-06-17 11:37:25 -050021#include <asm/fsl_law.h>
Becky Bruce38dba0c2010-12-17 17:17:56 -060022#include <asm/fsl_lbc.h>
York Sunebbe11d2010-09-28 15:20:33 -070023#include <post.h>
24#include <asm/processor.h>
25#include <asm/fsl_ddr_sdram.h>
wdenk42d1f032003-10-15 23:53:47 +000026
James Yang591933c2008-02-08 16:44:53 -060027DECLARE_GLOBAL_DATA_PTR;
28
Ira W. Snyderc18de0d2011-11-21 13:20:32 -080029/*
30 * Default board reset function
31 */
32static void
33__board_reset(void)
34{
35 /* Do nothing */
36}
37void board_reset(void) __attribute__((weak, alias("__board_reset")));
38
wdenk42d1f032003-10-15 23:53:47 +000039int checkcpu (void)
40{
wdenk97d80fc2004-06-09 00:34:46 +000041 sys_info_t sysinfo;
wdenk97d80fc2004-06-09 00:34:46 +000042 uint pvr, svr;
43 uint ver;
44 uint major, minor;
Kumar Gala4dbdb762008-06-10 16:53:46 -050045 struct cpu_type *cpu;
Wolfgang Denk08ef89e2008-10-19 02:35:49 +020046 char buf1[32], buf2[32];
York Sunf165bc32013-06-25 11:37:43 -070047#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
48 ccsr_gur_t __iomem *gur =
49 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50#endif
York Sun98ffa192012-10-08 07:44:31 +000051
52 /*
53 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
54 * mode. Previous platform use ddr ratio to do the same. This
55 * information is only for display here.
56 */
57#ifdef CONFIG_FSL_CORENET
58#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
59 u32 ddr_sync = 0; /* only async mode is supported */
60#else
61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
63#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
64#else /* CONFIG_FSL_CORENET */
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080065#ifdef CONFIG_DDR_CLK_FREQ
66 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
67 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
68#else
Kumar Galaee1e35b2008-05-29 01:21:24 -050069 u32 ddr_ratio = 0;
Kumar Gala39aaca12009-03-19 02:46:19 -050070#endif /* CONFIG_DDR_CLK_FREQ */
York Sun98ffa192012-10-08 07:44:31 +000071#endif /* CONFIG_FSL_CORENET */
72
Timur Tabifbb9ecf2011-08-05 16:15:24 -050073 unsigned int i, core, nr_cores = cpu_numcores();
74 u32 mask = cpu_mask();
wdenk42d1f032003-10-15 23:53:47 +000075
wdenk97d80fc2004-06-09 00:34:46 +000076 svr = get_svr();
wdenk97d80fc2004-06-09 00:34:46 +000077 major = SVR_MAJ(svr);
78 minor = SVR_MIN(svr);
79
Poonam Aggrwal0e870982009-07-31 12:08:14 +053080 if (cpu_numcores() > 1) {
Poonam Aggrwal21170c82009-09-03 19:42:40 +053081#ifndef CONFIG_MP
82 puts("Unicore software on multiprocessor system!!\n"
83 "To enable mutlticore build define CONFIG_MP\n");
84#endif
Kim Phillips680c6132010-08-09 18:39:57 -050085 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Poonam Aggrwal0e870982009-07-31 12:08:14 +053086 printf("CPU%d: ", pic->whoami);
87 } else {
88 puts("CPU: ");
89 }
Andy Fleming1ced1212008-02-06 01:19:40 -060090
Simon Glass67ac13b2012-12-13 20:48:48 +000091 cpu = gd->arch.cpu;
Poonam Aggrwal0e870982009-07-31 12:08:14 +053092
Poonam Aggrwal58442dc2009-09-02 13:35:21 +053093 puts(cpu->name);
94 if (IS_E_PROCESSOR(svr))
95 puts("E");
Andy Fleming1ced1212008-02-06 01:19:40 -060096
wdenk97d80fc2004-06-09 00:34:46 +000097 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk42d1f032003-10-15 23:53:47 +000098
wdenk6c9e7892005-03-15 22:56:53 +000099 pvr = get_pvr();
100 ver = PVR_VER(pvr);
101 major = PVR_MAJ(pvr);
102 minor = PVR_MIN(pvr);
103
104 printf("Core: ");
Kumar Gala89927382011-07-25 09:28:39 -0500105 switch(ver) {
106 case PVR_VER_E500_V1:
107 case PVR_VER_E500_V2:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300108 puts("e500");
Kumar Gala89927382011-07-25 09:28:39 -0500109 break;
110 case PVR_VER_E500MC:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300111 puts("e500mc");
Kumar Gala89927382011-07-25 09:28:39 -0500112 break;
113 case PVR_VER_E5500:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300114 puts("e5500");
Kumar Gala89927382011-07-25 09:28:39 -0500115 break;
Kumar Gala5b6b85a2012-08-17 08:20:23 +0000116 case PVR_VER_E6500:
Fabio Estevam6770c5e2013-04-21 13:11:02 -0300117 puts("e6500");
Kumar Gala5b6b85a2012-08-17 08:20:23 +0000118 break;
Kumar Gala89927382011-07-25 09:28:39 -0500119 default:
Kumar Gala2a3a96c2009-10-21 13:23:54 -0500120 puts("Unknown");
Kumar Gala89927382011-07-25 09:28:39 -0500121 break;
wdenk6c9e7892005-03-15 22:56:53 +0000122 }
Kumar Gala0f060c32008-10-23 01:47:38 -0500123
wdenk6c9e7892005-03-15 22:56:53 +0000124 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
125
York Sun2f1712b2012-10-08 07:44:10 +0000126 if (nr_cores > CONFIG_MAX_CPUS) {
127 panic("\nUnexpected number of cores: %d, max is %d\n",
128 nr_cores, CONFIG_MAX_CPUS);
129 }
130
wdenk97d80fc2004-06-09 00:34:46 +0000131 get_sys_info(&sysinfo);
132
Kumar Galab29dee32009-02-04 09:35:57 -0600133 puts("Clock Configuration:");
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500134 for_each_cpu(i, core, nr_cores, mask) {
Wolfgang Denk1bba30e2009-02-19 00:41:08 +0100135 if (!(i & 3))
136 printf ("\n ");
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500137 printf("CPU%d:%-4s MHz, ", core,
138 strmhz(buf1, sysinfo.freqProcessor[core]));
Kumar Galab29dee32009-02-04 09:35:57 -0600139 }
140 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
Kumar Galaee1e35b2008-05-29 01:21:24 -0500141
Kumar Gala39aaca12009-03-19 02:46:19 -0500142#ifdef CONFIG_FSL_CORENET
143 if (ddr_sync == 1) {
144 printf(" DDR:%-4s MHz (%s MT/s data rate) "
145 "(Synchronous), ",
146 strmhz(buf1, sysinfo.freqDDRBus/2),
147 strmhz(buf2, sysinfo.freqDDRBus));
148 } else {
149 printf(" DDR:%-4s MHz (%s MT/s data rate) "
150 "(Asynchronous), ",
151 strmhz(buf1, sysinfo.freqDDRBus/2),
152 strmhz(buf2, sysinfo.freqDDRBus));
153 }
154#else
Kumar Galad4357932007-12-07 04:59:26 -0600155 switch (ddr_ratio) {
156 case 0x0:
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200157 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
158 strmhz(buf1, sysinfo.freqDDRBus/2),
159 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600160 break;
161 case 0x7:
Kumar Gala39aaca12009-03-19 02:46:19 -0500162 printf(" DDR:%-4s MHz (%s MT/s data rate) "
163 "(Synchronous), ",
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200164 strmhz(buf1, sysinfo.freqDDRBus/2),
165 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600166 break;
167 default:
Kumar Gala39aaca12009-03-19 02:46:19 -0500168 printf(" DDR:%-4s MHz (%s MT/s data rate) "
169 "(Asynchronous), ",
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200170 strmhz(buf1, sysinfo.freqDDRBus/2),
171 strmhz(buf2, sysinfo.freqDDRBus));
Kumar Galad4357932007-12-07 04:59:26 -0600172 break;
173 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500174#endif
wdenk97d80fc2004-06-09 00:34:46 +0000175
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530176#if defined(CONFIG_FSL_LBC)
Kumar Gala39aaca12009-03-19 02:46:19 -0500177 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
Trent Piephoada591d2008-12-03 15:16:37 -0800178 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
Kumar Gala39aaca12009-03-19 02:46:19 -0500179 } else {
Trent Piephoada591d2008-12-03 15:16:37 -0800180 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
181 sysinfo.freqLocalBus);
Kumar Gala39aaca12009-03-19 02:46:19 -0500182 }
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530183#endif
wdenk97d80fc2004-06-09 00:34:46 +0000184
Kumar Gala800c73c2012-10-08 07:44:06 +0000185#if defined(CONFIG_FSL_IFC)
186 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
187#endif
188
Andy Fleming1ced1212008-02-06 01:19:40 -0600189#ifdef CONFIG_CPM2
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200190 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
Andy Fleming1ced1212008-02-06 01:19:40 -0600191#endif
wdenk97d80fc2004-06-09 00:34:46 +0000192
Haiying Wangb3d7f202009-05-20 12:30:29 -0400193#ifdef CONFIG_QE
194 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
195#endif
196
Kumar Gala39aaca12009-03-19 02:46:19 -0500197#ifdef CONFIG_SYS_DPAA_FMAN
198 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
Emil Medve7eda1f82010-06-17 00:08:29 -0500199 printf(" FMAN%d: %s MHz\n", i + 1,
Kumar Gala39aaca12009-03-19 02:46:19 -0500200 strmhz(buf1, sysinfo.freqFMan[i]));
201 }
202#endif
203
Haiying Wang990e1a82012-10-11 07:13:39 +0000204#ifdef CONFIG_SYS_DPAA_QBMAN
205 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN));
206#endif
207
Kumar Gala39aaca12009-03-19 02:46:19 -0500208#ifdef CONFIG_SYS_DPAA_PME
209 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
210#endif
211
wdenk6c9e7892005-03-15 22:56:53 +0000212 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000213
York Sunf165bc32013-06-25 11:37:43 -0700214#ifdef CONFIG_FSL_CORENET
215 /* Display the RCW, so that no one gets confused as to what RCW
216 * we're actually using for this boot.
217 */
218 puts("Reset Configuration Word (RCW):");
219 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
220 u32 rcw = in_be32(&gur->rcwsr[i]);
221
222 if ((i % 4) == 0)
223 printf("\n %08x:", i * 4);
224 printf(" %08x", rcw);
225 }
226 puts("\n");
227#endif
228
wdenk42d1f032003-10-15 23:53:47 +0000229 return 0;
230}
231
232
233/* ------------------------------------------------------------------------- */
234
Mike Frysinger882b7d72010-10-20 03:41:17 -0400235int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenk42d1f032003-10-15 23:53:47 +0000236{
Kumar Galac3483222009-09-08 13:46:46 -0500237/* Everything after the first generation of PQ3 parts has RSTCR */
238#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
239 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
Sergei Poselenov793670c2008-05-08 14:17:08 +0200240 unsigned long val, msr;
241
wdenk42d1f032003-10-15 23:53:47 +0000242 /*
243 * Initiate hard reset in debug control register DBCR0
Kumar Galac3483222009-09-08 13:46:46 -0500244 * Make sure MSR[DE] = 1. This only resets the core.
wdenk42d1f032003-10-15 23:53:47 +0000245 */
Sergei Poselenov793670c2008-05-08 14:17:08 +0200246 msr = mfmsr ();
247 msr |= MSR_DE;
248 mtmsr (msr);
urwithsughosh@gmail.comdf909682007-09-24 13:32:13 -0400249
Sergei Poselenov793670c2008-05-08 14:17:08 +0200250 val = mfspr(DBCR0);
251 val |= 0x70000000;
252 mtspr(DBCR0,val);
Kumar Galac3483222009-09-08 13:46:46 -0500253#else
254 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Ira W. Snyderc18de0d2011-11-21 13:20:32 -0800255
256 /* Attempt board-specific reset */
257 board_reset();
258
259 /* Next try asserting HRESET_REQ */
260 out_be32(&gur->rstcr, 0x2);
Kumar Galac3483222009-09-08 13:46:46 -0500261 udelay(100);
262#endif
Sergei Poselenov793670c2008-05-08 14:17:08 +0200263
wdenk42d1f032003-10-15 23:53:47 +0000264 return 1;
265}
266
267
268/*
269 * Get timebase clock frequency
270 */
Kumar Gala66412c62011-02-18 05:40:54 -0600271#ifndef CONFIG_SYS_FSL_TBCLK_DIV
272#define CONFIG_SYS_FSL_TBCLK_DIV 8
273#endif
wdenk42d1f032003-10-15 23:53:47 +0000274unsigned long get_tbclk (void)
275{
Kumar Gala66412c62011-02-18 05:40:54 -0600276 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
277
278 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
wdenk42d1f032003-10-15 23:53:47 +0000279}
280
281
282#if defined(CONFIG_WATCHDOG)
283void
wdenk42d1f032003-10-15 23:53:47 +0000284reset_85xx_watchdog(void)
285{
286 /*
287 * Clear TSR(WIS) bit by writing 1
288 */
Mark Marshall320d53d2012-09-09 23:06:03 +0000289 mtspr(SPRN_TSR, TSR_WIS);
wdenk42d1f032003-10-15 23:53:47 +0000290}
Horst Kronstorferdf616ca2013-03-13 10:14:05 +0000291
292void
293watchdog_reset(void)
294{
295 int re_enable = disable_interrupts();
296
297 reset_85xx_watchdog();
298 if (re_enable)
299 enable_interrupts();
300}
wdenk42d1f032003-10-15 23:53:47 +0000301#endif /* CONFIG_WATCHDOG */
302
Sergei Poselenov740280e2008-06-06 15:42:40 +0200303/*
Andy Fleming80522dc2008-10-30 16:51:33 -0500304 * Initializes on-chip MMC controllers.
305 * to override, implement board_mmc_init()
306 */
307int cpu_mmc_init(bd_t *bis)
308{
309#ifdef CONFIG_FSL_ESDHC
310 return fsl_esdhc_mmc_init(bis);
311#else
312 return 0;
313#endif
314}
Becky Bruce199e2622010-06-17 11:37:25 -0500315
316/*
317 * Print out the state of various machine registers.
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530318 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
319 * parameters for IFC and TLBs
Becky Bruce199e2622010-06-17 11:37:25 -0500320 */
321void mpc85xx_reginfo(void)
322{
323 print_tlbcam();
324 print_laws();
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530325#if defined(CONFIG_FSL_LBC)
Becky Bruce199e2622010-06-17 11:37:25 -0500326 print_lbc_regs();
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530327#endif
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530328#ifdef CONFIG_FSL_IFC
329 print_ifc_regs();
330#endif
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530331
Becky Bruce199e2622010-06-17 11:37:25 -0500332}
York Sunebbe11d2010-09-28 15:20:33 -0700333
Becky Bruce38dba0c2010-12-17 17:17:56 -0600334/* Common ddr init for non-corenet fsl 85xx platforms */
335#ifndef CONFIG_FSL_CORENET
Scott Woodc97cd1b2012-09-20 19:02:18 -0500336#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
337 !defined(CONFIG_SYS_INIT_L2_ADDR)
Zhao Chenhuic1fc2d42011-01-28 17:58:37 +0800338phys_size_t initdram(int board_type)
339{
340#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
341 return fsl_ddr_sdram_size();
342#else
Mingkai Hu76d354f2013-04-12 15:56:28 +0800343 return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Zhao Chenhuic1fc2d42011-01-28 17:58:37 +0800344#endif
345}
346#else /* CONFIG_SYS_RAMBOOT */
Becky Bruce38dba0c2010-12-17 17:17:56 -0600347phys_size_t initdram(int board_type)
348{
349 phys_size_t dram_size = 0;
350
Becky Bruce810c4422010-12-17 17:17:58 -0600351#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
Becky Bruce38dba0c2010-12-17 17:17:56 -0600352 {
353 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
354 unsigned int x = 10;
355 unsigned int i;
356
357 /*
358 * Work around to stabilize DDR DLL
359 */
360 out_be32(&gur->ddrdllcr, 0x81000000);
361 asm("sync;isync;msync");
362 udelay(200);
363 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
364 setbits_be32(&gur->devdisr, 0x00010000);
365 for (i = 0; i < x; i++)
366 ;
367 clrbits_be32(&gur->devdisr, 0x00010000);
368 x++;
369 }
370 }
371#endif
372
York Sun1b3e3c42011-06-07 09:42:16 +0800373#if defined(CONFIG_SPD_EEPROM) || \
374 defined(CONFIG_DDR_SPD) || \
375 defined(CONFIG_SYS_DDR_RAW_TIMING)
Becky Bruce38dba0c2010-12-17 17:17:56 -0600376 dram_size = fsl_ddr_sdram();
377#else
378 dram_size = fixed_sdram();
379#endif
380 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
381 dram_size *= 0x100000;
382
383#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
384 /*
385 * Initialize and enable DDR ECC.
386 */
387 ddr_enable_ecc(dram_size);
388#endif
389
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530390#if defined(CONFIG_FSL_LBC)
Becky Bruce38dba0c2010-12-17 17:17:56 -0600391 /* Some boards also have sdram on the lbc */
Becky Bruce70961ba2010-12-17 17:17:57 -0600392 lbc_sdram_init();
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530393#endif
Becky Bruce38dba0c2010-12-17 17:17:56 -0600394
Wolfgang Denk21cd5812011-07-25 10:13:53 +0200395 debug("DDR: ");
Becky Bruce38dba0c2010-12-17 17:17:56 -0600396 return dram_size;
397}
Zhao Chenhuic1fc2d42011-01-28 17:58:37 +0800398#endif /* CONFIG_SYS_RAMBOOT */
Becky Bruce38dba0c2010-12-17 17:17:56 -0600399#endif
400
York Sunebbe11d2010-09-28 15:20:33 -0700401#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
402
403/* Board-specific functions defined in each board's ddr.c */
404void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
405 unsigned int ctrl_num);
406void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
407 phys_addr_t *rpn);
408unsigned int
409 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
410
Becky Bruce9cdfe282011-07-18 18:49:15 -0500411void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
412
York Sunebbe11d2010-09-28 15:20:33 -0700413static void dump_spd_ddr_reg(void)
414{
415 int i, j, k, m;
416 u8 *p_8;
417 u32 *p_32;
418 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
419 generic_spd_eeprom_t
420 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
421
422 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
423 fsl_ddr_get_spd(spd[i], i);
424
425 puts("SPD data of all dimms (zero vaule is omitted)...\n");
426 puts("Byte (hex) ");
427 k = 1;
428 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
429 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
430 printf("Dimm%d ", k++);
431 }
432 puts("\n");
433 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
434 m = 0;
435 printf("%3d (0x%02x) ", k, k);
436 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
437 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
438 p_8 = (u8 *) &spd[i][j];
439 if (p_8[k]) {
440 printf("0x%02x ", p_8[k]);
441 m++;
442 } else
443 puts(" ");
444 }
445 }
446 if (m)
447 puts("\n");
448 else
449 puts("\r");
450 }
451
452 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
453 switch (i) {
454 case 0:
Andy Fleminge76cd5d2012-10-23 19:03:46 -0500455 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
York Sunebbe11d2010-09-28 15:20:33 -0700456 break;
Andy Fleminge76cd5d2012-10-23 19:03:46 -0500457#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
York Sunebbe11d2010-09-28 15:20:33 -0700458 case 1:
Andy Fleminge76cd5d2012-10-23 19:03:46 -0500459 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
York Sunebbe11d2010-09-28 15:20:33 -0700460 break;
461#endif
Andy Fleminge76cd5d2012-10-23 19:03:46 -0500462#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
York Suna4c66502012-08-17 08:22:39 +0000463 case 2:
Andy Fleminge76cd5d2012-10-23 19:03:46 -0500464 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
York Suna4c66502012-08-17 08:22:39 +0000465 break;
466#endif
Andy Fleminge76cd5d2012-10-23 19:03:46 -0500467#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
York Suna4c66502012-08-17 08:22:39 +0000468 case 3:
Andy Fleminge76cd5d2012-10-23 19:03:46 -0500469 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
York Suna4c66502012-08-17 08:22:39 +0000470 break;
471#endif
York Sunebbe11d2010-09-28 15:20:33 -0700472 default:
473 printf("%s unexpected controller number = %u\n",
474 __func__, i);
475 return;
476 }
477 }
478 printf("DDR registers dump for all controllers "
479 "(zero vaule is omitted)...\n");
480 puts("Offset (hex) ");
481 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
482 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
483 puts("\n");
484 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
485 m = 0;
486 printf("%6d (0x%04x)", k * 4, k * 4);
487 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
488 p_32 = (u32 *) ddr[i];
489 if (p_32[k]) {
490 printf(" 0x%08x", p_32[k]);
491 m++;
492 } else
493 puts(" ");
494 }
495 if (m)
496 puts("\n");
497 else
498 puts("\r");
499 }
500 puts("\n");
501}
502
503/* invalid the TLBs for DDR and setup new ones to cover p_addr */
504static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
505{
506 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
507 unsigned long epn;
508 u32 tsize, valid, ptr;
York Sunebbe11d2010-09-28 15:20:33 -0700509 int ddr_esel;
510
Becky Bruce9cdfe282011-07-18 18:49:15 -0500511 clear_ddr_tlbs_phys(p_addr, size>>20);
York Sunebbe11d2010-09-28 15:20:33 -0700512
513 /* Setup new tlb to cover the physical address */
514 setup_ddr_tlbs_phys(p_addr, size>>20);
515
516 ptr = vstart;
517 ddr_esel = find_tlb_idx((void *)ptr, 1);
518 if (ddr_esel != -1) {
519 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
520 } else {
521 printf("TLB error in function %s\n", __func__);
522 return -1;
523 }
524
525 return 0;
526}
527
528/*
529 * slide the testing window up to test another area
530 * for 32_bit system, the maximum testable memory is limited to
531 * CONFIG_MAX_MEM_MAPPED
532 */
533int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
534{
535 phys_addr_t test_cap, p_addr;
536 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
537
538#if !defined(CONFIG_PHYS_64BIT) || \
539 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
540 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
541 test_cap = p_size;
542#else
543 test_cap = gd->ram_size;
544#endif
545 p_addr = (*vstart) + (*size) + (*phys_offset);
546 if (p_addr < test_cap - 1) {
547 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
548 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
549 return -1;
550 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
551 *size = (u32) p_size;
552 printf("Testing 0x%08llx - 0x%08llx\n",
553 (u64)(*vstart) + (*phys_offset),
554 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
555 } else
556 return 1;
557
558 return 0;
559}
560
561/* initialization for testing area */
562int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
563{
564 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
565
566 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
567 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
568 *phys_offset = 0;
569
570#if !defined(CONFIG_PHYS_64BIT) || \
571 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
572 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
573 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
574 puts("Cannot test more than ");
575 print_size(CONFIG_MAX_MEM_MAPPED,
576 " without proper 36BIT support.\n");
577 }
578#endif
579 printf("Testing 0x%08llx - 0x%08llx\n",
580 (u64)(*vstart) + (*phys_offset),
581 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
582
583 return 0;
584}
585
586/* invalid TLBs for DDR and remap as normal after testing */
587int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
588{
589 unsigned long epn;
590 u32 tsize, valid, ptr;
591 phys_addr_t rpn = 0;
592 int ddr_esel;
593
594 /* disable the TLBs for this testing */
595 ptr = *vstart;
596
597 while (ptr < (*vstart) + (*size)) {
598 ddr_esel = find_tlb_idx((void *)ptr, 1);
599 if (ddr_esel != -1) {
600 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
601 disable_tlb(ddr_esel);
602 }
603 ptr += TSIZE_TO_BYTES(tsize);
604 }
605
606 puts("Remap DDR ");
607 setup_ddr_tlbs(gd->ram_size>>20);
608 puts("\n");
609
610 return 0;
611}
612
613void arch_memory_failure_handle(void)
614{
615 dump_spd_ddr_reg();
616}
617#endif