blob: 3c075aa09ec78b8f63cf6254188d407b38e1653f [file] [log] [blame]
Lukasz Majewski1d7993d2019-06-24 15:50:45 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 *
6 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
8 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
9 *
10 * Simple multiplexer clock implementation
11 */
12
13/*
14 * U-Boot CCF porting node:
15 *
16 * The Linux kernel - as of tag: 5.0-rc3 is using also the imx_clk_fixup_mux()
17 * version of CCF mux. It is used on e.g. imx6q to provide fixes (like
18 * imx_cscmr1_fixup) for broken HW.
19 *
20 * At least for IMX6Q (but NOT IMX6QP) it is important when we set the parent
21 * clock.
22 */
23
24#include <common.h>
25#include <asm/io.h>
26#include <malloc.h>
27#include <clk-uclass.h>
28#include <dm/device.h>
29#include <linux/clk-provider.h>
30#include <clk.h>
31#include "clk.h"
32
33#define UBOOT_DM_CLK_CCF_MUX "ccf_clk_mux"
34
35int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
36 unsigned int val)
37{
38 struct clk_mux *mux = to_clk_mux(clk);
39 int num_parents = mux->num_parents;
40
41 if (table) {
42 int i;
43
44 for (i = 0; i < num_parents; i++)
45 if (table[i] == val)
46 return i;
47 return -EINVAL;
48 }
49
50 if (val && (flags & CLK_MUX_INDEX_BIT))
51 val = ffs(val) - 1;
52
53 if (val && (flags & CLK_MUX_INDEX_ONE))
54 val--;
55
56 if (val >= num_parents)
57 return -EINVAL;
58
59 return val;
60}
61
62static u8 clk_mux_get_parent(struct clk *clk)
63{
64 struct clk_mux *mux = to_clk_mux(clk);
65 u32 val;
66
Lukasz Majewski5da00952019-06-24 15:50:49 +020067#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
68 val = mux->io_mux_val;
69#else
70 val = readl(mux->reg);
71#endif
72 val >>= mux->shift;
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020073 val &= mux->mask;
74
75 return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
76}
77
78const struct clk_ops clk_mux_ops = {
79 .get_rate = clk_generic_get_rate,
80};
81
82struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
83 const char * const *parent_names, u8 num_parents,
84 unsigned long flags,
85 void __iomem *reg, u8 shift, u32 mask,
86 u8 clk_mux_flags, u32 *table)
87{
88 struct clk_mux *mux;
89 struct clk *clk;
90 u8 width = 0;
91 int ret;
92
93 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
94 width = fls(mask) - ffs(mask) + 1;
95 if (width + shift > 16) {
96 pr_err("mux value exceeds LOWORD field\n");
97 return ERR_PTR(-EINVAL);
98 }
99 }
100
101 /* allocate the mux */
102 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
103 if (!mux)
104 return ERR_PTR(-ENOMEM);
105
106 /* U-boot specific assignments */
107 mux->parent_names = parent_names;
108 mux->num_parents = num_parents;
109
110 /* struct clk_mux assignments */
111 mux->reg = reg;
112 mux->shift = shift;
113 mux->mask = mask;
114 mux->flags = clk_mux_flags;
115 mux->table = table;
Lukasz Majewski5da00952019-06-24 15:50:49 +0200116#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
117 mux->io_mux_val = *(u32 *)reg;
118#endif
Lukasz Majewski1d7993d2019-06-24 15:50:45 +0200119
120 clk = &mux->clk;
121
122 /*
123 * Read the current mux setup - so we assign correct parent.
124 *
125 * Changing parent would require changing internals of udevice struct
126 * for the corresponding clock (to do that define .set_parent() method.
127 */
128 ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name,
129 parent_names[clk_mux_get_parent(clk)]);
130 if (ret) {
131 kfree(mux);
132 return ERR_PTR(ret);
133 }
134
135 return clk;
136}
137
138struct clk *clk_register_mux_table(struct device *dev, const char *name,
139 const char * const *parent_names, u8 num_parents,
140 unsigned long flags,
141 void __iomem *reg, u8 shift, u32 mask,
142 u8 clk_mux_flags, u32 *table)
143{
144 struct clk *clk;
145
146 clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
147 flags, reg, shift, mask, clk_mux_flags,
148 table);
149 if (IS_ERR(clk))
150 return ERR_CAST(clk);
151 return clk;
152}
153
154struct clk *clk_register_mux(struct device *dev, const char *name,
155 const char * const *parent_names, u8 num_parents,
156 unsigned long flags,
157 void __iomem *reg, u8 shift, u8 width,
158 u8 clk_mux_flags)
159{
160 u32 mask = BIT(width) - 1;
161
162 return clk_register_mux_table(dev, name, parent_names, num_parents,
163 flags, reg, shift, mask, clk_mux_flags,
164 NULL);
165}
166
167U_BOOT_DRIVER(ccf_clk_mux) = {
168 .name = UBOOT_DM_CLK_CCF_MUX,
169 .id = UCLASS_CLK,
170 .ops = &clk_mux_ops,
171 .flags = DM_FLAG_PRE_RELOC,
172};