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Michal Simek6ded73a2016-09-19 10:41:55 +02001menu "FPGA support"
2
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +05303config FPGA
4 bool
5
Patrick Bruenn98d62e62016-11-04 11:57:02 +01006config FPGA_ALTERA
7 bool "Enable Altera FPGA drivers"
8 select FPGA
9 help
10 Say Y here to enable the Altera FPGA driver
11
12 This provides basic infrastructure to support Altera FPGA devices.
13 Enable Altera FPGA specific functions which includes bitstream
14 (in BIT format), fpga and device validation.
15
Tien Fong Cheefa23ba12017-07-26 13:05:40 +080016config FPGA_SOCFPGA
17 bool "Enable Gen5 and Arria10 common FPGA drivers"
18 select FPGA_ALTERA
19 help
20 Say Y here to enable the Gen5 and Arria10 common FPGA driver
21
22 This provides common functionality for Gen5 and Arria10 devices.
23
Tom Rini6e52cb22022-06-12 20:02:00 -040024config FPGA_STRATIX_V
25 bool "Enable Stratix V FPGA drivers"
26 depends on FPGA_ALTERA
27 help
28 Say Y here to enable the Altera Stratix V FPGA specific driver.
29
Alexander Dahl312c4b12022-10-07 14:19:54 +020030config FPGA_ACEX1K
31 bool "Enable Altera ACEX 1K driver"
32 depends on FPGA_ALTERA
33 help
34 Say Y here to enable the Altera ACEX 1K FPGA specific driver.
35
Patrick Bruenn98d62e62016-11-04 11:57:02 +010036config FPGA_CYCLON2
37 bool "Enable Altera FPGA driver for Cyclone II"
38 depends on FPGA_ALTERA
39 help
40 Say Y here to enable the Altera Cyclone II FPGA specific driver
41
42 This provides common functionality for Altera Cyclone II devices.
43 Enable FPGA driver for loading bitstream in BIT and BIN format
44 on Altera Cyclone II device.
45
Chee Hong Angd2170162020-08-07 11:50:03 +080046config FPGA_INTEL_SDM_MAILBOX
47 bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
Siew Chin Lim9a5bbdf2021-03-01 20:04:10 +080048 depends on TARGET_SOCFPGA_SOC64
Ang, Chee Hongc41e6602018-12-19 18:35:14 -080049 select FPGA_ALTERA
50 help
Chee Hong Angd2170162020-08-07 11:50:03 +080051 Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
Ang, Chee Hongc41e6602018-12-19 18:35:14 -080052
Chee Hong Angd2170162020-08-07 11:50:03 +080053 This provides common functionality for Intel FPGA devices.
54 Enable FPGA driver for writing full bitstream into Intel FPGA
55 devices through SDM (Secure Device Manager) Mailbox.
Ang, Chee Hongc41e6602018-12-19 18:35:14 -080056
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053057config FPGA_XILINX
58 bool "Enable Xilinx FPGA drivers"
59 select FPGA
60 help
61 Enable Xilinx FPGA specific functions which includes bitstream
62 (in BIT format), fpga and device validation.
63
64config FPGA_ZYNQMPPL
65 bool "Enable Xilinx FPGA driver for ZynqMP"
66 depends on FPGA_XILINX
67 help
68 Enable FPGA driver for loading bitstream in BIT and BIN format
69 on Xilinx Zynq UltraScale+ (ZynqMP) device.
70
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +053071config FPGA_VERSALPL
72 bool "Enable Xilinx FPGA driver for Versal"
73 depends on FPGA_XILINX
74 help
75 Enable FPGA driver for loading bitstream in PDI format on Xilinx
76 Versal device. PDI is a new programmable device image format for
77 Versal. The bitstream will only be generated as PDI for Versal
78 platform.
79
Alexander Dahl312c4b12022-10-07 14:19:54 +020080config FPGA_SPARTAN2
81 bool "Enable Spartan2 FPGA driver"
82 depends on FPGA_XILINX
83 help
84 Enable Spartan2 FPGA driver.
85
Vipul Kumarf4158342018-02-16 18:02:49 +053086config FPGA_SPARTAN3
Michal Simeka225f812018-07-23 15:59:55 +020087 bool "Enable Spartan3 FPGA driver"
Robert Hancock25d63a32019-06-18 09:47:13 -060088 depends on FPGA_XILINX
Michal Simeka225f812018-07-23 15:59:55 +020089 help
90 Enable Spartan3 FPGA driver for loading in BIT format.
Vipul Kumarf4158342018-02-16 18:02:49 +053091
Robert Hancock25d63a32019-06-18 09:47:13 -060092config FPGA_VIRTEX2
93 bool "Enable Xilinx Virtex-II and later FPGA driver"
94 depends on FPGA_XILINX
95 help
96 Enable Virtex-II FPGA driver for loading in BIT format. This driver
97 also supports many newer Xilinx FPGA families.
98
Vipul Kumar3990c9d2018-02-16 18:02:51 +053099config FPGA_ZYNQPL
Michal Simeka225f812018-07-23 15:59:55 +0200100 bool "Enable Xilinx FPGA for Zynq"
101 depends on ARCH_ZYNQ
102 help
103 Enable FPGA driver for loading bitstream in BIT and BIN format
104 on Xilinx Zynq devices.
Vipul Kumar3990c9d2018-02-16 18:02:51 +0530105
Alexander Dahle8ffc1d2022-07-21 15:31:21 +0200106config SYS_FPGA_CHECK_CTRLC
107 bool "Allow Control-C to interrupt FPGA configuration"
108 depends on FPGA
109 help
110 User can interrupt FPGA configuration by pressing CTRL+C.
111
Alexander Dahl8c09cb62022-07-21 15:31:22 +0200112config SYS_FPGA_PROG_FEEDBACK
113 bool "Progress output during FPGA configuration"
114 depends on FPGA
115 default y if FPGA_VIRTEX2
116 help
117 Enable printing of hash marks during FPGA configuration.
118
Oleksandr Suvorovfb2b8852022-07-22 17:16:02 +0300119config FPGA_LOAD_SECURE
120 bool "Enable loading secure bitstreams"
121 depends on FPGA
122 help
123 Enables the fpga loads() functions that are used to load secure
124 (authenticated or encrypted or both) bitstreams on to FPGA.
125
126config SPL_FPGA_LOAD_SECURE
127 bool "Enable loading secure bitstreams for SPL"
128 depends on SPL_FPGA
129 help
130 Enables the fpga loads() functions that are used to load secure
131 (authenticated or encrypted or both) bitstreams on to FPGA.
132
Alexander Dahl1323d082022-09-30 14:04:30 +0200133config DM_FPGA
134 bool "Enable Driver Model for FPGA drivers"
135 depends on DM
136 select FPGA
137 help
138 Enable driver model for Field-Programmable Gate Array (FPGA) devices.
139 The devices cover a wide range of applications and are configured at
140 runtime by loading a bitstream into the FPGA device.
141 Loading a bitstream from any kind of storage is the main task of the
142 FPGA drivers.
143 For now this uclass has no methods yet.
144
145config SANDBOX_FPGA
146 bool "Enable sandbox FPGA driver"
147 depends on SANDBOX && DM_FPGA
148 help
149 This is a driver model based FPGA driver for sandbox.
150 Currently it is a stub only, as there are no usable uclass methods yet.
151
Michal Simek6ded73a2016-09-19 10:41:55 +0200152endmenu