blob: 3ed15092ae989a00dafb1c91a84b2873c8cb30a8 [file] [log] [blame]
wdenke887afc2002-08-27 09:44:07 +00001/*
2 * (C) Copyright 2000
3 * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
wdenke887afc2002-08-27 09:44:07 +000026#if defined(CONFIG_8xx)
27#include <mpc8xx.h>
stroesee075fbe2003-12-09 14:59:11 +000028#elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
wdenke887afc2002-08-27 09:44:07 +000029#include <asm/processor.h>
wdenk0db5bca2003-03-31 17:27:09 +000030#elif defined (CONFIG_5xx)
31#include <mpc5xx.h>
wdenk56523f12004-07-11 17:40:54 +000032#elif defined (CONFIG_MPC5200)
33#include <mpc5xxx.h>
Becky Bruce4f93f8b2008-01-23 16:31:06 -060034#elif defined (CONFIG_MPC86xx)
35extern void mpc86xx_reginfo(void);
wdenke887afc2002-08-27 09:44:07 +000036#endif
Jon Loeliger65c450b2007-06-11 19:01:54 -050037
wdenke887afc2002-08-27 09:44:07 +000038int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
39{
40#if defined(CONFIG_8xx)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
wdenke887afc2002-08-27 09:44:07 +000042 volatile memctl8xx_t *memctl = &immap->im_memctl;
43 volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
44 volatile sit8xx_t *timers = &immap->im_sit;
45
46 /* Hopefully more PowerPC knowledgable people will add code to display
47 * other useful registers
48 */
49
wdenk4b9206e2004-03-23 22:14:11 +000050 printf ("\nSystem Configuration registers\n"
wdenke887afc2002-08-27 09:44:07 +000051
wdenk4b9206e2004-03-23 22:14:11 +000052 "\tIMMR\t0x%08X\n", get_immr(0));
wdenke887afc2002-08-27 09:44:07 +000053
54 printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
55 printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
56
57 printf("\tSWT\t0x%08X", sysconf->sc_swt);
58 printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
59
60 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
61 sysconf->sc_sipend, sysconf->sc_simask);
62 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
63 sysconf->sc_siel, sysconf->sc_sivec);
64 printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
65 sysconf->sc_tesr, sysconf->sc_sdcr);
66
wdenk4b9206e2004-03-23 22:14:11 +000067 printf ("Memory Controller Registers\n"
wdenke887afc2002-08-27 09:44:07 +000068
wdenk4b9206e2004-03-23 22:14:11 +000069 "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
wdenke887afc2002-08-27 09:44:07 +000070 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
71 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
72 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
73 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
74 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
75 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
76 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
wdenk4b9206e2004-03-23 22:14:11 +000077 printf ("\n"
78 "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
wdenke887afc2002-08-27 09:44:07 +000079 memctl->memc_mamr, memctl->memc_mbmr );
80 printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
81 memctl->memc_mstat, memctl->memc_mptpr );
82 printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
83
wdenk4b9206e2004-03-23 22:14:11 +000084 printf ("\nSystem Integration Timers\n"
85 "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
wdenke887afc2002-08-27 09:44:07 +000086 timers->sit_tbscr, timers->sit_rtcsc);
87 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
88
89 /*
90 * May be some CPM info here?
91 */
92
stroesee075fbe2003-12-09 14:59:11 +000093#elif defined (CONFIG_405GP)
wdenk50015ab2003-12-09 20:22:16 +000094 printf ("\n405GP registers; MSR=%08x\n",mfmsr());
95 printf ("\nUniversal Interrupt Controller Regs\n"
Stefan Roesed1631fe2008-06-26 13:40:57 +020096 "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
wdenk50015ab2003-12-09 20:22:16 +000097 "\n"
Stefan Roesed1631fe2008-06-26 13:40:57 +020098 "%08x %08x %08x %08x %08x %08x %08x %08x\n",
wdenke887afc2002-08-27 09:44:07 +000099 mfdcr(uicsr),
wdenke887afc2002-08-27 09:44:07 +0000100 mfdcr(uicer),
101 mfdcr(uiccr),
102 mfdcr(uicpr),
103 mfdcr(uictr),
104 mfdcr(uicmsr),
105 mfdcr(uicvr),
106 mfdcr(uicvcr));
107
wdenk4b9206e2004-03-23 22:14:11 +0000108 puts ("\nMemory (SDRAM) Configuration\n"
wdenk50015ab2003-12-09 20:22:16 +0000109 "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
wdenke887afc2002-08-27 09:44:07 +0000110
Stefan Roesed1c3b272009-09-09 16:25:29 +0200111 mtdcr(SDRAM0_CFGADDR,mem_besra); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
112 mtdcr(SDRAM0_CFGADDR,mem_besrsa); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
113 mtdcr(SDRAM0_CFGADDR,mem_besrb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
114 mtdcr(SDRAM0_CFGADDR,mem_besrsb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
115 mtdcr(SDRAM0_CFGADDR,mem_bear); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
116 mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
117 mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
118 mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
wdenke887afc2002-08-27 09:44:07 +0000119
wdenk4b9206e2004-03-23 22:14:11 +0000120 puts ("\n"
wdenk50015ab2003-12-09 20:22:16 +0000121 "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
Stefan Roesed1c3b272009-09-09 16:25:29 +0200122 mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
123 mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
124 mtdcr(SDRAM0_CFGADDR,mem_mb2cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
125 mtdcr(SDRAM0_CFGADDR,mem_mb3cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
126 mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
127 mtdcr(SDRAM0_CFGADDR,mem_ecccf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
128 mtdcr(SDRAM0_CFGADDR,mem_eccerr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
wdenke887afc2002-08-27 09:44:07 +0000129
130 printf ("\n\n"
wdenk50015ab2003-12-09 20:22:16 +0000131 "DMA Channels\n"
Stefan Roesed1c3b272009-09-09 16:25:29 +0200132 "DMASR DMASGC DMAADR\n"
wdenk50015ab2003-12-09 20:22:16 +0000133 "%08x %08x %08x\n"
134 "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n"
135 "%08x %08x %08x %08x %08x\n"
136 "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n"
137 "%08x %08x %08x %08x %08x\n",
Stefan Roesed1c3b272009-09-09 16:25:29 +0200138 mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR),
139 mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0),
140 mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1));
wdenke887afc2002-08-27 09:44:07 +0000141
142 printf (
wdenk50015ab2003-12-09 20:22:16 +0000143 "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
144 "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
Stefan Roesed1c3b272009-09-09 16:25:29 +0200145 mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2),
146 mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) );
wdenke887afc2002-08-27 09:44:07 +0000147
wdenk4b9206e2004-03-23 22:14:11 +0000148 puts ("\n"
wdenk50015ab2003-12-09 20:22:16 +0000149 "External Bus\n"
Stefan Roesed1c3b272009-09-09 16:25:29 +0200150 "PBEAR PBESR0 PBESR1 EBC0_CFG\n");
151 mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
152 mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA));
153 mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA));
154 mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA));
wdenke887afc2002-08-27 09:44:07 +0000155
wdenk4b9206e2004-03-23 22:14:11 +0000156 puts ("\n"
Stefan Roesed1c3b272009-09-09 16:25:29 +0200157 "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n");
158 mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
159 mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
160 mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
161 mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
162 mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
163 mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
164 mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
165 mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
wdenke887afc2002-08-27 09:44:07 +0000166
wdenk4b9206e2004-03-23 22:14:11 +0000167 puts ("\n"
Stefan Roesed1c3b272009-09-09 16:25:29 +0200168 "PB4CR PB4AP PB5CR bp5ap PB6CR PB6AP PB7CR PB7AP\n");
169 mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
170 mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
171 mtdcr(EBC0_CFGADDR,PB5CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
172 mtdcr(EBC0_CFGADDR,PB5AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
173 mtdcr(EBC0_CFGADDR,PB6CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
174 mtdcr(EBC0_CFGADDR,PB6AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
175 mtdcr(EBC0_CFGADDR,PB7CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
176 mtdcr(EBC0_CFGADDR,PB7AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
wdenke887afc2002-08-27 09:44:07 +0000177
wdenk4b9206e2004-03-23 22:14:11 +0000178 puts ("\n\n");
wdenk56523f12004-07-11 17:40:54 +0000179
stroesee075fbe2003-12-09 14:59:11 +0000180#elif defined(CONFIG_405EP)
wdenk50015ab2003-12-09 20:22:16 +0000181 printf ("\n405EP registers; MSR=%08x\n",mfmsr());
182 printf ("\nUniversal Interrupt Controller Regs\n"
183 "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
184 "\n"
185 "%08x %08x %08x %08x %08x %08x %08x %08x\n",
stroesee075fbe2003-12-09 14:59:11 +0000186 mfdcr(uicsr),
187 mfdcr(uicer),
188 mfdcr(uiccr),
189 mfdcr(uicpr),
190 mfdcr(uictr),
191 mfdcr(uicmsr),
192 mfdcr(uicvr),
193 mfdcr(uicvcr));
194
wdenk4b9206e2004-03-23 22:14:11 +0000195 puts ("\nMemory (SDRAM) Configuration\n"
wdenk50015ab2003-12-09 20:22:16 +0000196 "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");
stroesee075fbe2003-12-09 14:59:11 +0000197
Stefan Roesed1c3b272009-09-09 16:25:29 +0200198 mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
199 mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
200 mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
201 mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
202 mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
203 mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
stroesee075fbe2003-12-09 14:59:11 +0000204
205 printf ("\n\n"
wdenk50015ab2003-12-09 20:22:16 +0000206 "DMA Channels\n"
Stefan Roesed1c3b272009-09-09 16:25:29 +0200207 "DMASR DMASGC DMAADR\n" "%08x %08x %08x\n"
wdenk50015ab2003-12-09 20:22:16 +0000208 "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n"
209 "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n",
Stefan Roesed1c3b272009-09-09 16:25:29 +0200210 mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR),
211 mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0),
212 mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1));
stroesee075fbe2003-12-09 14:59:11 +0000213
214 printf (
wdenk50015ab2003-12-09 20:22:16 +0000215 "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
216 "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
Stefan Roesed1c3b272009-09-09 16:25:29 +0200217 mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2),
218 mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) );
stroesee075fbe2003-12-09 14:59:11 +0000219
wdenk4b9206e2004-03-23 22:14:11 +0000220 puts ("\n"
wdenk50015ab2003-12-09 20:22:16 +0000221 "External Bus\n"
Stefan Roesed1c3b272009-09-09 16:25:29 +0200222 "PBEAR PBESR0 PBESR1 EBC0_CFG\n");
223 mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
224 mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA));
225 mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA));
226 mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA));
stroesee075fbe2003-12-09 14:59:11 +0000227
wdenk4b9206e2004-03-23 22:14:11 +0000228 puts ("\n"
Stefan Roesed1c3b272009-09-09 16:25:29 +0200229 "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n");
230 mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
231 mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
232 mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
233 mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
234 mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
235 mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
236 mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
237 mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
stroesee075fbe2003-12-09 14:59:11 +0000238
wdenk4b9206e2004-03-23 22:14:11 +0000239 puts ("\n"
Stefan Roesed1c3b272009-09-09 16:25:29 +0200240 "PB4CR PB4AP\n");
241 mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
242 mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
stroesee075fbe2003-12-09 14:59:11 +0000243
wdenk4b9206e2004-03-23 22:14:11 +0000244 puts ("\n\n");
wdenk0db5bca2003-03-31 17:27:09 +0000245#elif defined(CONFIG_5xx)
wdenke887afc2002-08-27 09:44:07 +0000246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
wdenk0db5bca2003-03-31 17:27:09 +0000248 volatile memctl5xx_t *memctl = &immap->im_memctl;
249 volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
250 volatile sit5xx_t *timers = &immap->im_sit;
251 volatile car5xx_t *car = &immap->im_clkrst;
252 volatile uimb5xx_t *uimb = &immap->im_uimb;
253
wdenk4b9206e2004-03-23 22:14:11 +0000254 puts ("\nSystem Configuration registers\n");
wdenk0db5bca2003-03-31 17:27:09 +0000255 printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
256 printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
257 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
258 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
259 printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
260
wdenk4b9206e2004-03-23 22:14:11 +0000261 puts ("\nMemory Controller Registers\n");
wdenk0db5bca2003-03-31 17:27:09 +0000262 printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
263 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
264 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
265 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
266 printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
267 printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
268
wdenk4b9206e2004-03-23 22:14:11 +0000269 puts ("\nSystem Integration Timers\n");
wdenk0db5bca2003-03-31 17:27:09 +0000270 printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
271 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
272
wdenk4b9206e2004-03-23 22:14:11 +0000273 puts ("\nClocks and Reset\n");
wdenk0db5bca2003-03-31 17:27:09 +0000274 printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
275
wdenk4b9206e2004-03-23 22:14:11 +0000276 puts ("\nU-Bus to IMB3 Bus Interface\n");
wdenk0db5bca2003-03-31 17:27:09 +0000277 printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
wdenk4b9206e2004-03-23 22:14:11 +0000278 puts ("\n\n");
wdenk56523f12004-07-11 17:40:54 +0000279
280#elif defined(CONFIG_MPC5200)
281 puts ("\nMPC5200 registers\n");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282 printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
wdenk56523f12004-07-11 17:40:54 +0000283 puts ("Memory map registers\n");
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200284 printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000285 *(volatile ulong*)MPC5XXX_CS0_START,
286 *(volatile ulong*)MPC5XXX_CS0_STOP,
287 *(volatile ulong*)MPC5XXX_CS0_CFG,
288 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200289 printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000290 *(volatile ulong*)MPC5XXX_CS1_START,
291 *(volatile ulong*)MPC5XXX_CS1_STOP,
292 *(volatile ulong*)MPC5XXX_CS1_CFG,
293 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200294 printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000295 *(volatile ulong*)MPC5XXX_CS2_START,
296 *(volatile ulong*)MPC5XXX_CS2_STOP,
297 *(volatile ulong*)MPC5XXX_CS2_CFG,
298 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200299 printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000300 *(volatile ulong*)MPC5XXX_CS3_START,
301 *(volatile ulong*)MPC5XXX_CS3_STOP,
302 *(volatile ulong*)MPC5XXX_CS3_CFG,
303 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200304 printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000305 *(volatile ulong*)MPC5XXX_CS4_START,
306 *(volatile ulong*)MPC5XXX_CS4_STOP,
307 *(volatile ulong*)MPC5XXX_CS4_CFG,
308 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200309 printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000310 *(volatile ulong*)MPC5XXX_CS5_START,
311 *(volatile ulong*)MPC5XXX_CS5_STOP,
312 *(volatile ulong*)MPC5XXX_CS5_CFG,
313 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200314 printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000315 *(volatile ulong*)MPC5XXX_CS6_START,
316 *(volatile ulong*)MPC5XXX_CS6_STOP,
317 *(volatile ulong*)MPC5XXX_CS6_CFG,
318 (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200319 printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000320 *(volatile ulong*)MPC5XXX_CS7_START,
321 *(volatile ulong*)MPC5XXX_CS7_STOP,
322 *(volatile ulong*)MPC5XXX_CS7_CFG,
323 (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200324 printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000325 *(volatile ulong*)MPC5XXX_BOOTCS_START,
326 *(volatile ulong*)MPC5XXX_BOOTCS_STOP,
327 *(volatile ulong*)MPC5XXX_BOOTCS_CFG,
328 (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200329 printf ("\tSDRAMCS0: %08lX\n",
wdenk56523f12004-07-11 17:40:54 +0000330 *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200331 printf ("\tSDRAMCS1: %08lX\n",
wdenk56523f12004-07-11 17:40:54 +0000332 *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600333#elif defined(CONFIG_MPC86xx)
334 mpc86xx_reginfo();
Mike Frysinger97c26e02008-02-04 19:26:56 -0500335
336#elif defined(CONFIG_BLACKFIN)
337 puts("\nSystem Configuration registers\n");
338
339 puts("\nPLL Registers\n");
340 printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n",
341 bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
342 printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n",
343 bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
344 printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL());
345
346 puts("\nEBIU AMC Registers\n");
347 printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL());
348 printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n",
349 bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
350# ifdef EBIU_MODE
351 printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n",
352 bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
353 printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n",
354 bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
355# endif
356
357# ifdef EBIU_RSTCTL
358 puts("\nEBIU DDR Registers\n");
359 printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n",
360 bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
361 printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n",
362 bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
363 printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n",
364 bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
365 printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n",
366 bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
367# else
368 puts("\nEBIU SDC Registers\n");
369 printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n",
370 bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
371 printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n",
372 bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
373# endif
374
Wolfgang Denk9e04a812008-02-15 00:26:52 +0100375#endif /* CONFIG_BLACKFIN */
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600376
wdenke887afc2002-08-27 09:44:07 +0000377 return 0;
378}
379
wdenk8bde7f72003-06-27 21:31:46 +0000380 /**************************************************/
381
Mike Frysinger97c26e02008-02-04 19:26:56 -0500382#if defined(CONFIG_CMD_REGINFO)
wdenk0d498392003-07-01 21:06:45 +0000383U_BOOT_CMD(
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200384 reginfo, 2, 1, do_reginfo,
Peter Tyser2fb26042009-01-27 18:03:12 -0600385 "print register information",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200386 ""
wdenk8bde7f72003-06-27 21:31:46 +0000387);
388#endif