blob: 9ec02cce998189ad7e093b1781bac34781f6ace9 [file] [log] [blame]
Kumar Gala129ba612008-08-12 11:13:08 -05001/*
Kumar Gala509c4c42010-05-21 04:05:14 -05002 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
Kumar Gala129ba612008-08-12 11:13:08 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8572ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Kumar Gala509c4c42010-05-21 04:05:14 -050030#include "../board/freescale/common/ics307_clk.h"
31
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020032#ifdef CONFIG_36BIT
Kumar Galaf9edcc12009-09-10 16:23:45 -050033#define CONFIG_PHYS_64BIT
34#endif
35
Kumar Galacb14e932010-11-12 08:22:01 -060036#ifdef CONFIG_NAND
37#define CONFIG_NAND_U_BOOT
38#define CONFIG_RAMBOOT_NAND
39#ifdef CONFIG_NAND_SPL
40#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
41#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
42#else
43#define CONFIG_SYS_TEXT_BASE 0xf8f82000
44#endif /* CONFIG_NAND_SPL */
45#endif
46
47#ifndef CONFIG_SYS_TEXT_BASE
48#define CONFIG_SYS_TEXT_BASE 0xeff80000
49#endif
50
51#ifndef CONFIG_SYS_MONITOR_BASE
52#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
53#endif
54
Kumar Gala129ba612008-08-12 11:13:08 -050055/* High Level Configuration Options */
56#define CONFIG_BOOKE 1 /* BOOKE */
57#define CONFIG_E500 1 /* BOOKE e500 family */
58#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
59#define CONFIG_MPC8572 1
60#define CONFIG_MPC8572DS 1
61#define CONFIG_MP 1 /* support multiple processors */
Kumar Gala129ba612008-08-12 11:13:08 -050062
Kumar Galac51fc5d2009-01-23 14:22:13 -060063#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Kumar Gala129ba612008-08-12 11:13:08 -050064#define CONFIG_PCI 1 /* Enable PCI/PCIE */
65#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
66#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
67#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
68#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
69#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050070#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala129ba612008-08-12 11:13:08 -050071
72#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
73
74#define CONFIG_TSEC_ENET /* tsec ethernet support */
75#define CONFIG_ENV_OVERWRITE
76
Kumar Gala509c4c42010-05-21 04:05:14 -050077#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
78#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
Haiying Wang4ca06602008-10-03 12:37:41 -040079#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala129ba612008-08-12 11:13:08 -050080
81/*
82 * These can be toggled for performance analysis, otherwise use default.
83 */
84#define CONFIG_L2_CACHE /* toggle L2 cache */
85#define CONFIG_BTB /* toggle branch predition */
Kumar Gala129ba612008-08-12 11:13:08 -050086
87#define CONFIG_ENABLE_36BIT_PHYS 1
88
Kumar Gala18af1c52009-01-23 14:22:14 -060089#ifdef CONFIG_PHYS_64BIT
90#define CONFIG_ADDR_MAP 1
91#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
92#endif
93
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
95#define CONFIG_SYS_MEMTEST_END 0x7fffffff
Kumar Gala129ba612008-08-12 11:13:08 -050096#define CONFIG_PANIC_HANG /* do not reset board on panic */
97
98/*
Kumar Galacb14e932010-11-12 08:22:01 -060099 * Config the L2 Cache as L2 SRAM
100 */
101#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
102#ifdef CONFIG_PHYS_64BIT
103#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
104#else
105#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
106#endif
107#define CONFIG_SYS_L2_SIZE (512 << 10)
108#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
109
110/*
Kumar Gala129ba612008-08-12 11:13:08 -0500111 * Base addresses -- Note these are effective addresses where the
112 * actual resources get mapped (not physical addresses)
113 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
Kumar Gala18af1c52009-01-23 14:22:14 -0600115#ifdef CONFIG_PHYS_64BIT
116#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
117#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
Kumar Gala18af1c52009-01-23 14:22:14 -0600119#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Kumar Gala129ba612008-08-12 11:13:08 -0500121
Kumar Galacb14e932010-11-12 08:22:01 -0600122#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
123#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
124#else
125#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
126#endif
127
Kumar Gala129ba612008-08-12 11:13:08 -0500128/* DDR Setup */
Kumar Galaf8523cb2009-02-06 09:56:35 -0600129#define CONFIG_VERY_BIG_RAM
Kumar Gala129ba612008-08-12 11:13:08 -0500130#define CONFIG_FSL_DDR2
131#undef CONFIG_FSL_DDR_INTERACTIVE
132#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
133#define CONFIG_DDR_SPD
Kumar Gala129ba612008-08-12 11:13:08 -0500134
Dave Liu9b0ad1b2008-10-28 17:53:38 +0800135#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
Kumar Gala129ba612008-08-12 11:13:08 -0500136#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
139#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala129ba612008-08-12 11:13:08 -0500140
141#define CONFIG_NUM_DDR_CONTROLLERS 2
142#define CONFIG_DIMM_SLOTS_PER_CTLR 1
143#define CONFIG_CHIP_SELECTS_PER_CTRL 2
144
145/* I2C addresses of SPD EEPROMs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500147#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
148#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
149
150/* These are used when DDR doesn't use SPD. */
Dave Liudc889e82008-11-28 20:16:58 +0800151#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
152#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
153#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
154#define CONFIG_SYS_DDR_TIMING_3 0x00020000
155#define CONFIG_SYS_DDR_TIMING_0 0x00260802
156#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
157#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
158#define CONFIG_SYS_DDR_MODE_1 0x00440462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_DDR_MODE_2 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800160#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
Dave Liudc889e82008-11-28 20:16:58 +0800162#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
163#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800165#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
166#define CONFIG_SYS_DDR_CONTROL2 0x24400000
Kumar Gala129ba612008-08-12 11:13:08 -0500167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
169#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
170#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala129ba612008-08-12 11:13:08 -0500171
172/*
Kumar Gala129ba612008-08-12 11:13:08 -0500173 * Make sure required options are set
174 */
175#ifndef CONFIG_SPD_EEPROM
176#error ("CONFIG_SPD_EEPROM is required")
177#endif
178
179#undef CONFIG_CLOCKS_IN_MHZ
180
181/*
182 * Memory map
183 *
184 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
185 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
186 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
187 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
188 *
189 * Localbus cacheable (TBD)
190 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
191 *
192 * Localbus non-cacheable
193 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
194 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100195 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala129ba612008-08-12 11:13:08 -0500196 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
197 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
198 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
199 */
200
201/*
202 * Local Bus Definitions
203 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala18af1c52009-01-23 14:22:14 -0600205#ifdef CONFIG_PHYS_64BIT
206#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
207#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600208#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600209#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500210
Kumar Galacb14e932010-11-12 08:22:01 -0600211
212#define CONFIG_FLASH_BR_PRELIM \
213 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
214 | BR_PS_16 | BR_V)
215#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500216
Kumar Galac953ddf2008-12-02 14:19:34 -0600217#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
218#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500219
Kumar Gala18af1c52009-01-23 14:22:14 -0600220#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala129ba612008-08-12 11:13:08 -0500222#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
225#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
226#undef CONFIG_SYS_FLASH_CHECKSUM
227#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
228#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala129ba612008-08-12 11:13:08 -0500229
Kumar Galacb14e932010-11-12 08:22:01 -0600230#if defined(CONFIG_RAMBOOT_NAND)
231#define CONFIG_SYS_RAMBOOT
232#define CONFIG_SYS_EXTRA_ENV_RELOC
233#else
234#undef CONFIG_SYS_RAMBOOT
235#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500236
237#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_FLASH_CFI
239#define CONFIG_SYS_FLASH_EMPTY_INFO
240#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala129ba612008-08-12 11:13:08 -0500241
242#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
243
Kumar Gala558710b2010-11-19 08:53:25 -0600244#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala129ba612008-08-12 11:13:08 -0500245#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
246#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala18af1c52009-01-23 14:22:14 -0600247#ifdef CONFIG_PHYS_64BIT
248#define PIXIS_BASE_PHYS 0xfffdf0000ull
249#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600250#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600251#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500252
Kumar Gala52b565f2008-12-02 14:19:33 -0600253#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala129ba612008-08-12 11:13:08 -0500255
256#define PIXIS_ID 0x0 /* Board ID at offset 0 */
257#define PIXIS_VER 0x1 /* Board version at offset 1 */
258#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
259#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
260#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
261#define PIXIS_PWR 0x5 /* PIXIS Power status register */
262#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
263#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
264#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
265#define PIXIS_VCTL 0x10 /* VELA Control Register */
266#define PIXIS_VSTAT 0x11 /* VELA Status Register */
267#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
268#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
269#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
270#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500271#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
272#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
273#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
274#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
275#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500276#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
277#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
278#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
279#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
280#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
281#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
282#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
283#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
284#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
285#define PIXIS_VWATCH 0x24 /* Watchdog Register */
286#define PIXIS_LED 0x25 /* LED Register */
287
Kumar Galacb14e932010-11-12 08:22:01 -0600288#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
289
Kumar Gala129ba612008-08-12 11:13:08 -0500290/* old pixis referenced names */
291#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
292#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
Liu Yu7e183ca2008-10-10 11:40:59 +0800294#define PIXIS_VSPEED2_TSEC1SER 0x8
295#define PIXIS_VSPEED2_TSEC2SER 0x4
296#define PIXIS_VSPEED2_TSEC3SER 0x2
297#define PIXIS_VSPEED2_TSEC4SER 0x1
298#define PIXIS_VCFGEN1_TSEC1SER 0x20
299#define PIXIS_VCFGEN1_TSEC2SER 0x20
300#define PIXIS_VCFGEN1_TSEC3SER 0x20
301#define PIXIS_VCFGEN1_TSEC4SER 0x20
302#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
303 | PIXIS_VSPEED2_TSEC2SER \
304 | PIXIS_VSPEED2_TSEC3SER \
305 | PIXIS_VSPEED2_TSEC4SER)
306#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
307 | PIXIS_VCFGEN1_TSEC2SER \
308 | PIXIS_VCFGEN1_TSEC3SER \
309 | PIXIS_VCFGEN1_TSEC4SER)
Kumar Gala129ba612008-08-12 11:13:08 -0500310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_INIT_RAM_LOCK 1
312#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200313#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala129ba612008-08-12 11:13:08 -0500314
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200315#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
319#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala129ba612008-08-12 11:13:08 -0500320
Kumar Galacb14e932010-11-12 08:22:01 -0600321#ifndef CONFIG_NAND_SPL
Haiying Wangc013b742008-10-29 13:32:59 -0400322#define CONFIG_SYS_NAND_BASE 0xffa00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600323#ifdef CONFIG_PHYS_64BIT
324#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
325#else
Haiying Wangc013b742008-10-29 13:32:59 -0400326#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600327#endif
Kumar Galacb14e932010-11-12 08:22:01 -0600328#else
329#define CONFIG_SYS_NAND_BASE 0xfff00000
330#ifdef CONFIG_PHYS_64BIT
331#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
332#else
333#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
334#endif
335#endif
336
Haiying Wangc013b742008-10-29 13:32:59 -0400337#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
338 CONFIG_SYS_NAND_BASE + 0x40000, \
339 CONFIG_SYS_NAND_BASE + 0x80000,\
340 CONFIG_SYS_NAND_BASE + 0xC0000}
341#define CONFIG_SYS_MAX_NAND_DEVICE 4
Haiying Wangc013b742008-10-29 13:32:59 -0400342#define CONFIG_MTD_NAND_VERIFY_WRITE
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100343#define CONFIG_CMD_NAND 1
344#define CONFIG_NAND_FSL_ELBC 1
Haiying Wangc013b742008-10-29 13:32:59 -0400345#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
346
Kumar Galacb14e932010-11-12 08:22:01 -0600347/* NAND boot: 4K NAND loader config */
348#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
349#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
350#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
351#define CONFIG_SYS_NAND_U_BOOT_START \
352 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
353#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
354#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
355#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
356
357
Haiying Wangc013b742008-10-29 13:32:59 -0400358/* NAND flash config */
Kumar Gala72a9414a2009-01-23 14:22:12 -0600359#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100360 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
361 | BR_PS_8 /* Port Size = 8 bit */ \
362 | BR_MS_FCM /* MSEL = FCM */ \
363 | BR_V) /* valid */
364#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
365 | OR_FCM_PGS /* Large Page*/ \
366 | OR_FCM_CSCT \
367 | OR_FCM_CST \
368 | OR_FCM_CHT \
369 | OR_FCM_SCY_1 \
370 | OR_FCM_TRLX \
371 | OR_FCM_EHTR)
Haiying Wangc013b742008-10-29 13:32:59 -0400372
Kumar Galacb14e932010-11-12 08:22:01 -0600373#ifdef CONFIG_RAMBOOT_NAND
374#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
375#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
376#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
377#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
378#else
379#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
380#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400381#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
382#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Kumar Galacb14e932010-11-12 08:22:01 -0600383#endif
Kumar Gala72a9414a2009-01-23 14:22:12 -0600384#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100385 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
386 | BR_PS_8 /* Port Size = 8 bit */ \
387 | BR_MS_FCM /* MSEL = FCM */ \
388 | BR_V) /* valid */
389#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Kumar Gala72a9414a2009-01-23 14:22:12 -0600390#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100391 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
392 | BR_PS_8 /* Port Size = 8 bit */ \
393 | BR_MS_FCM /* MSEL = FCM */ \
394 | BR_V) /* valid */
395#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400396
Kumar Gala72a9414a2009-01-23 14:22:12 -0600397#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100398 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
399 | BR_PS_8 /* Port Size = 8 bit */ \
400 | BR_MS_FCM /* MSEL = FCM */ \
401 | BR_V) /* valid */
402#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400403
404
Kumar Gala129ba612008-08-12 11:13:08 -0500405/* Serial Port - controlled on board with jumper J8
406 * open - index 2
407 * shorted - index 1
408 */
409#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_NS16550
411#define CONFIG_SYS_NS16550_SERIAL
412#define CONFIG_SYS_NS16550_REG_SIZE 1
413#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Galacb14e932010-11-12 08:22:01 -0600414#ifdef CONFIG_NAND_SPL
415#define CONFIG_NS16550_MIN_FUNCTIONS
416#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala129ba612008-08-12 11:13:08 -0500419 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
420
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
422#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Kumar Gala129ba612008-08-12 11:13:08 -0500423
424/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_HUSH_PARSER
426#ifdef CONFIG_SYS_HUSH_PARSER
427#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Kumar Gala129ba612008-08-12 11:13:08 -0500428#endif
429
430/*
431 * Pass open firmware flat tree
432 */
433#define CONFIG_OF_LIBFDT 1
434#define CONFIG_OF_BOARD_SETUP 1
435#define CONFIG_OF_STDOUT_VIA_ALIAS 1
436
Kumar Gala129ba612008-08-12 11:13:08 -0500437/* new uImage format support */
438#define CONFIG_FIT 1
439#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
440
441/* I2C */
442#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
443#define CONFIG_HARD_I2C /* I2C with hardware support */
444#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Haiying Wang1f3ba312008-10-03 11:46:59 -0400445#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
447#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
448#define CONFIG_SYS_I2C_SLAVE 0x7F
449#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
450#define CONFIG_SYS_I2C_OFFSET 0x3000
451#define CONFIG_SYS_I2C2_OFFSET 0x3100
Kumar Gala129ba612008-08-12 11:13:08 -0500452
453/*
Haiying Wang445a7b32008-10-03 11:47:30 -0400454 * I2C2 EEPROM
455 */
456#define CONFIG_ID_EEPROM
457#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_I2C_EEPROM_NXID
Haiying Wang445a7b32008-10-03 11:47:30 -0400459#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
461#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
462#define CONFIG_SYS_EEPROM_BUS_NUM 1
Haiying Wang445a7b32008-10-03 11:47:30 -0400463
464/*
Kumar Gala129ba612008-08-12 11:13:08 -0500465 * General PCI
466 * Memory space is mapped 1-1, but I/O space must start from 0.
467 */
468
Kumar Gala129ba612008-08-12 11:13:08 -0500469/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600470#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600471#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600472#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500473#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600474#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
475#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600476#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600477#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600478#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600480#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600481#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600482#ifdef CONFIG_PHYS_64BIT
483#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
484#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600486#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500488
489/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600490#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600491#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600492#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500493#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600494#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
495#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600496#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600497#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600498#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600500#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600501#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600502#ifdef CONFIG_PHYS_64BIT
503#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
504#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
Kumar Gala18af1c52009-01-23 14:22:14 -0600506#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500508
509/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600510#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600511#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600512#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500513#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600514#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
515#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600516#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600517#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600518#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600520#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600521#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600522#ifdef CONFIG_PHYS_64BIT
523#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
524#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200525#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
Kumar Gala18af1c52009-01-23 14:22:14 -0600526#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500528
529#if defined(CONFIG_PCI)
530
531/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600532#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Kumar Gala129ba612008-08-12 11:13:08 -0500533
534/* video */
535#define CONFIG_VIDEO
536
537#if defined(CONFIG_VIDEO)
538#define CONFIG_BIOSEMU
539#define CONFIG_CFB_CONSOLE
540#define CONFIG_VIDEO_SW_CURSOR
541#define CONFIG_VGA_AS_SINGLE_DEVICE
542#define CONFIG_ATI_RADEON_FB
543#define CONFIG_VIDEO_LOGO
544/*#define CONFIG_CONSOLE_CURSOR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200545#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500546#endif
547
548#define CONFIG_NET_MULTI
549#define CONFIG_PCI_PNP /* do pci plug-and-play */
550
551#undef CONFIG_EEPRO100
552#undef CONFIG_TULIP
553#undef CONFIG_RTL8139
Kumar Gala16855ec2010-11-09 23:19:50 -0600554#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Kumar Gala129ba612008-08-12 11:13:08 -0500555
Kumar Gala129ba612008-08-12 11:13:08 -0500556#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600557 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
558 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
Kumar Gala129ba612008-08-12 11:13:08 -0500559 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
560#endif
561
562#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
563#define CONFIG_DOS_PARTITION
564#define CONFIG_SCSI_AHCI
565
566#ifdef CONFIG_SCSI_AHCI
567#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200568#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
569#define CONFIG_SYS_SCSI_MAX_LUN 1
570#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
571#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Kumar Gala129ba612008-08-12 11:13:08 -0500572#endif /* SCSI */
573
574#endif /* CONFIG_PCI */
575
576
577#if defined(CONFIG_TSEC_ENET)
578
579#ifndef CONFIG_NET_MULTI
580#define CONFIG_NET_MULTI 1
581#endif
582
583#define CONFIG_MII 1 /* MII PHY management */
584#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
585#define CONFIG_TSEC1 1
586#define CONFIG_TSEC1_NAME "eTSEC1"
587#define CONFIG_TSEC2 1
588#define CONFIG_TSEC2_NAME "eTSEC2"
589#define CONFIG_TSEC3 1
590#define CONFIG_TSEC3_NAME "eTSEC3"
591#define CONFIG_TSEC4 1
592#define CONFIG_TSEC4_NAME "eTSEC4"
593
Liu Yu7e183ca2008-10-10 11:40:59 +0800594#define CONFIG_PIXIS_SGMII_CMD
595#define CONFIG_FSL_SGMII_RISER 1
596#define SGMII_RISER_PHY_OFFSET 0x1c
597
598#ifdef CONFIG_FSL_SGMII_RISER
599#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
600#endif
601
Kumar Gala129ba612008-08-12 11:13:08 -0500602#define TSEC1_PHY_ADDR 0
603#define TSEC2_PHY_ADDR 1
604#define TSEC3_PHY_ADDR 2
605#define TSEC4_PHY_ADDR 3
606
607#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
608#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
609#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
610#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
611
612#define TSEC1_PHYIDX 0
613#define TSEC2_PHYIDX 0
614#define TSEC3_PHYIDX 0
615#define TSEC4_PHYIDX 0
616
617#define CONFIG_ETHPRIME "eTSEC1"
618
619#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
620#endif /* CONFIG_TSEC_ENET */
621
622/*
623 * Environment
624 */
Kumar Galacb14e932010-11-12 08:22:01 -0600625
626#if defined(CONFIG_SYS_RAMBOOT)
627#if defined(CONFIG_RAMBOOT_NAND)
628#define CONFIG_ENV_IS_IN_NAND 1
629#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
630#define CONFIG_ENV_OFFSET ((512 * 1024)\
631 + CONFIG_SYS_NAND_BLOCK_SIZE)
Kumar Gala129ba612008-08-12 11:13:08 -0500632#endif
Kumar Galacb14e932010-11-12 08:22:01 -0600633
634#else
635 #define CONFIG_ENV_IS_IN_FLASH 1
636 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
637 #define CONFIG_ENV_ADDR 0xfff80000
638 #else
639 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
640 #endif
641 #define CONFIG_ENV_SIZE 0x2000
642 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
643#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500644
645#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200646#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala129ba612008-08-12 11:13:08 -0500647
648/*
649 * Command line configuration.
650 */
651#include <config_cmd_default.h>
652
653#define CONFIG_CMD_IRQ
654#define CONFIG_CMD_PING
655#define CONFIG_CMD_I2C
656#define CONFIG_CMD_MII
657#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500658#define CONFIG_CMD_IRQ
659#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500660#define CONFIG_CMD_REGINFO
Kumar Gala129ba612008-08-12 11:13:08 -0500661
662#if defined(CONFIG_PCI)
663#define CONFIG_CMD_PCI
Kumar Gala129ba612008-08-12 11:13:08 -0500664#define CONFIG_CMD_NET
665#define CONFIG_CMD_SCSI
666#define CONFIG_CMD_EXT2
667#endif
668
669#undef CONFIG_WATCHDOG /* watchdog disabled */
670
671/*
672 * Miscellaneous configurable options
673 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200674#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500675#define CONFIG_CMDLINE_EDITING /* Command-line editing */
676#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200677#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
678#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Kumar Gala129ba612008-08-12 11:13:08 -0500679#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200680#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500681#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200682#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500683#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200684#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
685#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
686#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
687#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Kumar Gala129ba612008-08-12 11:13:08 -0500688
689/*
690 * For booting Linux, the board info and command line data
Kumar Gala89188a62009-07-15 08:54:50 -0500691 * have to be in the first 16 MB of memory, since this is
Kumar Gala129ba612008-08-12 11:13:08 -0500692 * the maximum mapped by the Linux kernel during initialization.
693 */
Kumar Gala89188a62009-07-15 08:54:50 -0500694#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Kumar Gala129ba612008-08-12 11:13:08 -0500695
Kumar Gala129ba612008-08-12 11:13:08 -0500696#if defined(CONFIG_CMD_KGDB)
697#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
698#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
699#endif
700
701/*
702 * Environment Configuration
703 */
704
705/* The mac addresses for all ethernet interface */
706#if defined(CONFIG_TSEC_ENET)
707#define CONFIG_HAS_ETH0
708#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
709#define CONFIG_HAS_ETH1
710#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
711#define CONFIG_HAS_ETH2
712#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
713#define CONFIG_HAS_ETH3
714#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
715#endif
716
717#define CONFIG_IPADDR 192.168.1.254
718
719#define CONFIG_HOSTNAME unknown
720#define CONFIG_ROOTPATH /opt/nfsroot
721#define CONFIG_BOOTFILE uImage
722#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
723
724#define CONFIG_SERVERIP 192.168.1.1
725#define CONFIG_GATEWAYIP 192.168.1.1
726#define CONFIG_NETMASK 255.255.255.0
727
728/* default location for tftp and bootm */
729#define CONFIG_LOADADDR 1000000
730
731#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
732#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
733
734#define CONFIG_BAUDRATE 115200
735
736#define CONFIG_EXTRA_ENV_SETTINGS \
Haiying Wang4ca06602008-10-03 12:37:41 -0400737 "memctl_intlv_ctl=2\0" \
Kumar Gala129ba612008-08-12 11:13:08 -0500738 "netdev=eth0\0" \
739 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
740 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200741 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
742 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
743 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
744 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
745 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Kumar Gala129ba612008-08-12 11:13:08 -0500746 "consoledev=ttyS0\0" \
747 "ramdiskaddr=2000000\0" \
748 "ramdiskfile=8572ds/ramdisk.uboot\0" \
749 "fdtaddr=c00000\0" \
750 "fdtfile=8572ds/mpc8572ds.dtb\0" \
751 "bdev=sda3\0"
752
753#define CONFIG_HDBOOT \
754 "setenv bootargs root=/dev/$bdev rw " \
755 "console=$consoledev,$baudrate $othbootargs;" \
756 "tftp $loadaddr $bootfile;" \
757 "tftp $fdtaddr $fdtfile;" \
758 "bootm $loadaddr - $fdtaddr"
759
760#define CONFIG_NFSBOOTCOMMAND \
761 "setenv bootargs root=/dev/nfs rw " \
762 "nfsroot=$serverip:$rootpath " \
763 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
764 "console=$consoledev,$baudrate $othbootargs;" \
765 "tftp $loadaddr $bootfile;" \
766 "tftp $fdtaddr $fdtfile;" \
767 "bootm $loadaddr - $fdtaddr"
768
769#define CONFIG_RAMBOOTCOMMAND \
770 "setenv bootargs root=/dev/ram rw " \
771 "console=$consoledev,$baudrate $othbootargs;" \
772 "tftp $ramdiskaddr $ramdiskfile;" \
773 "tftp $loadaddr $bootfile;" \
774 "tftp $fdtaddr $fdtfile;" \
775 "bootm $loadaddr $ramdiskaddr $fdtaddr"
776
777#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
778
779#endif /* __CONFIG_H */