blob: fe072da5164d012d6b6a509740ca235adea9d514 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +02002/*
Codrin Ciubotariua857d5f2015-07-24 16:55:36 +03003 * Copyright 2013, 2015 Freescale Semiconductor, Inc.
Codrin Ciubotariu6706b112015-01-12 14:08:33 +02004 *
Codrin Ciubotariua857d5f2015-07-24 16:55:36 +03005 * Driver for the Vitesse VSC9953 L2 Switch
Codrin Ciubotariu6706b112015-01-12 14:08:33 +02006 */
7
8#ifndef _VSC9953_H_
9#define _VSC9953_H_
10
11#include <config.h>
12#include <miiphy.h>
13#include <asm/types.h>
Codrin Ciubotariu6706b112015-01-12 14:08:33 +020014
15#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
16
17#define VSC9953_SYS_OFFSET 0x010000
Codrin Ciubotariu9de05982015-07-24 16:55:26 +030018#define VSC9953_REW_OFFSET 0x030000
Codrin Ciubotariu6706b112015-01-12 14:08:33 +020019#define VSC9953_DEV_GMII_OFFSET 0x100000
20#define VSC9953_QSYS_OFFSET 0x200000
21#define VSC9953_ANA_OFFSET 0x280000
22#define VSC9953_DEVCPU_GCB 0x070000
23#define VSC9953_ES0 0x040000
24#define VSC9953_IS1 0x050000
25#define VSC9953_IS2 0x060000
26
27#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
28#define VSC9953_PHY_REGS_OFFST 0x0000AC
29
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +030030/* Macros for vsc9953_chip_regs.soft_rst register */
Codrin Ciubotariuc4390482015-07-24 16:52:44 +030031#define VSC9953_SOFT_SWC_RST_ENA 0x00000001
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +030032
33/* Macros for vsc9953_sys_sys.reset_cfg register */
Codrin Ciubotariuc4390482015-07-24 16:52:44 +030034#define VSC9953_CORE_ENABLE 0x80
35#define VSC9953_MEM_ENABLE 0x40
36#define VSC9953_MEM_INIT 0x20
Codrin Ciubotariu6706b112015-01-12 14:08:33 +020037
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +030038/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
Codrin Ciubotariuc4390482015-07-24 16:52:44 +030039#define VSC9953_MAC_ENA_CFG 0x00000011
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +030040
41/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
Codrin Ciubotariuc4390482015-07-24 16:52:44 +030042#define VSC9953_MAC_MODE_CFG 0x00000011
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +030043
44/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
Codrin Ciubotariuc4390482015-07-24 16:52:44 +030045#define VSC9953_MAC_IFG_CFG 0x00000515
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +030046
47/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
Codrin Ciubotariuc4390482015-07-24 16:52:44 +030048#define VSC9953_MAC_HDX_CFG 0x00001043
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +030049
50/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
Codrin Ciubotariuc4390482015-07-24 16:52:44 +030051#define VSC9953_MAC_MAX_LEN 0x000005ee
Codrin Ciubotariu6706b112015-01-12 14:08:33 +020052
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +030053/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
54#define VSC9953_CLOCK_CFG 0x00000001
55#define VSC9953_CLOCK_CFG_1000M 0x00000001
56
57/* Macros for vsc9953_sys_sys.front_port_mode register */
58#define VSC9953_FRONT_PORT_MODE 0x00000000
59
60/* Macros for vsc9953_ana_pfc.pfc_cfg register */
61#define VSC9953_PFC_FC 0x00000001
62#define VSC9953_PFC_FC_QSGMII 0x00000000
63
64/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
65#define VSC9953_MAC_FC_CFG 0x04700000
66#define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
67
68/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
69#define VSC9953_PAUSE_CFG 0x001ffffe
70
71/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
72#define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
73
Codrin Ciubotariu86719f02015-07-24 16:55:29 +030074/* Macros for vsc9953_sys_sys.stat_cfg register */
75#define VSC9953_STAT_CLEAR_RX 0x00000400
76#define VSC9953_STAT_CLEAR_TX 0x00000800
77#define VSC9953_STAT_CLEAR_DR 0x00001000
78
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +030079/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
Codrin Ciubotariuc4390482015-07-24 16:52:44 +030080#define VSC9953_VCAP_MV_CFG 0x0000ffff
81#define VSC9953_VCAP_UPDATE_CTRL 0x01000004
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +030082
Codrin Ciubotariu22449852015-09-09 18:00:52 +030083/* Macros for register vsc9953_ana_ana_tables.mac_access register */
84#define VSC9953_MAC_CMD_IDLE 0x00000000
85#define VSC9953_MAC_CMD_LEARN 0x00000001
86#define VSC9953_MAC_CMD_FORGET 0x00000002
87#define VSC9953_MAC_CMD_AGE 0x00000003
88#define VSC9953_MAC_CMD_NEXT 0x00000004
89#define VSC9953_MAC_CMD_READ 0x00000006
90#define VSC9953_MAC_CMD_WRITE 0x00000007
91#define VSC9953_MAC_CMD_MASK 0x00000007
92#define VSC9953_MAC_CMD_VALID 0x00000800
93#define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000
94#define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200
95#define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400
96#define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600
97#define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600
98#define VSC9953_MAC_DESTIDX_MASK 0x000001f8
99#define VSC9953_MAC_VID_MASK 0x1fff0000
100#define VSC9953_MAC_MACH_MASK 0x0000ffff
101
Codrin Ciubotariu9de05982015-07-24 16:55:26 +0300102/* Macros for vsc9953_ana_port.vlan_cfg register */
103#define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
104#define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
Codrin Ciubotariua2477922015-07-24 16:55:33 +0300105#define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000
106#define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000
Codrin Ciubotariu9de05982015-07-24 16:55:26 +0300107#define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
108
109/* Macros for vsc9953_rew_port.port_vlan_cfg register */
110#define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
111
112/* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
113#define VSC9953_ANA_TBL_VID_MASK 0x00000fff
114
115/* Macros for vsc9953_ana_ana_tables.vlan_access register */
116#define VSC9953_VLAN_PORT_MASK 0x00001ffc
117#define VSC9953_VLAN_CMD_MASK 0x00000003
118#define VSC9953_VLAN_CMD_IDLE 0x00000000
119#define VSC9953_VLAN_CMD_READ 0x00000001
120#define VSC9953_VLAN_CMD_WRITE 0x00000002
121#define VSC9953_VLAN_CMD_INIT 0x00000003
122
Codrin Ciubotariu68c929d2015-07-24 16:55:30 +0300123/* Macros for vsc9953_ana_port.port_cfg register */
124#define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
125#define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
126#define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
127#define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
Codrin Ciubotariuaae0e682015-12-15 15:21:06 +0200128#define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c
Codrin Ciubotariu68c929d2015-07-24 16:55:30 +0300129
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300130/* Macros for vsc9953_qsys_sys.switch_port_mode register */
Codrin Ciubotariufe910952015-07-24 16:52:46 +0300131#define VSC9953_PORT_ENA 0x00002000
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300132
Codrin Ciubotariu21d214f2015-07-24 16:55:34 +0300133/* Macros for vsc9953_ana_ana.agen_ctrl register */
134#define VSC9953_FID_MASK_ALL 0x00fff000
135
Codrin Ciubotariu9de05982015-07-24 16:55:26 +0300136/* Macros for vsc9953_ana_ana.adv_learn register */
137#define VSC9953_VLAN_CHK 0x00000400
138
Codrin Ciubotariuba389e62015-12-15 15:21:03 +0200139/* Macros for vsc9953_ana_ana.auto_age register */
140#define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe
141
Codrin Ciubotariu9de05982015-07-24 16:55:26 +0300142/* Macros for vsc9953_rew_port.port_tag_cfg register */
143#define VSC9953_TAG_CFG_MASK 0x00000180
144#define VSC9953_TAG_CFG_NONE 0x00000000
145#define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
146#define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
147#define VSC9953_TAG_CFG_ALL 0x00000180
Codrin Ciubotariua2477922015-07-24 16:55:33 +0300148#define VSC9953_TAG_VID_PVID 0x00000010
Codrin Ciubotariu9de05982015-07-24 16:55:26 +0300149
Codrin Ciubotariu22449852015-09-09 18:00:52 +0300150/* Macros for vsc9953_ana_ana.anag_efil register */
151#define VSC9953_AGE_PORT_EN 0x00080000
152#define VSC9953_AGE_PORT_MASK 0x0007c000
153#define VSC9953_AGE_VID_EN 0x00002000
154#define VSC9953_AGE_VID_MASK 0x00001fff
155
156/* Macros for vsc9953_ana_ana_tables.mach_data register */
157#define VSC9953_MACHDATA_VID_MASK 0x1fff0000
158
Codrin Ciubotariuaae0e682015-12-15 15:21:06 +0200159/* Macros for vsc9953_ana_common.aggr_cfg register */
160#define VSC9953_AC_RND_ENA 0x00000080
161#define VSC9953_AC_DMAC_ENA 0x00000040
162#define VSC9953_AC_SMAC_ENA 0x00000020
163#define VSC9953_AC_IP6_LBL_ENA 0x00000010
164#define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008
165#define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004
166#define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002
167#define VSC9953_AC_MASK 0x000000fe
168
169/* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
170#define VSC9953_PGID_PORT_MASK 0x000003ff
171
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200172#define VSC9953_MAX_PORTS 10
173#define VSC9953_PORT_CHECK(port) \
174 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
175#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
176 ( \
177 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
178 ) ? 0 : 1 \
179)
Codrin Ciubotariu9de05982015-07-24 16:55:26 +0300180#define VSC9953_MAX_VLAN 4096
181#define VSC9953_VLAN_CHECK(vid) \
182 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
Codrin Ciubotariuba389e62015-12-15 15:21:03 +0200183#define VSC9953_DEFAULT_AGE_TIME 300
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200184
185#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
186
187#define MIIMIND_OPR_PEND 0x00000004
188
Radu Bulie98017a12018-05-21 10:02:09 -0500189#define VSC9953_BITMASK(offset) ((BIT(offset)) - 1)
190#define VSC9953_ENC_BITFIELD(target, offset, width) \
191 (((target) & VSC9953_BITMASK(width)) << (offset))
192
193#define VSC9953_IO_ADDR(target, offset) ((target) + (offset << 2))
194
195#define VSC9953_IO_REG(target, offset) (VSC9953_IO_ADDR(target, offset))
196#define VSC9953_VCAP_CACHE_ENTRY_DAT(target, ri) \
197 VSC9953_IO_REG(target, (0x2 + (ri)))
198
199#define VSC9953_VCAP_CACHE_MASK_DAT(target, ri) \
200 VSC9953_IO_REG(target, (0x42 + (ri)))
201
202#define VSC9953_VCAP_CACHE_TG_DAT(target) VSC9953_IO_REG(target, 0xe2)
203#define VSC9953_VCAP_CFG_MV_CFG(target) VSC9953_IO_REG(target, 0x1)
204#define VSC9953_VCAP_CFG_MV_CFG_SIZE(target) \
205 VSC9953_ENC_BITFIELD(target, 0, 16)
206
207#define VSC9953_VCAP_CFG_UPDATE_CTRL(target) VSC9953_IO_REG(target, 0x0)
208#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(target) \
209 VSC9953_ENC_BITFIELD(target, 22, 3)
210
211#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(target) \
212 VSC9953_ENC_BITFIELD(target, 3, 16)
213
214#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT BIT(2)
215#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
216#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
217#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
218#define VSC9953_VCAP_CACHE_ACTION_DAT(target, ri) \
219 VSC9953_IO_REG(target, (0x82 + (ri)))
220
221#define VSC9953_VCAP_CACHE_CNT_DAT(target, ri) \
222 VSC9953_IO_REG(target, (0xc2 + (ri)))
223
224#define VSC9953_PORT_OFFSET 1
225#define VSC9953_IS1_CNT 256
226#define VSC9953_IS2_CNT 1024
227#define VSC9953_ES0_CNT 1024
228
229#define BITS_TO_DWORD(in) (1 + (((in) - 1) / 32))
230#define ENTRY_WORDS_ES0 BITS_TO_DWORD(29)
231#define ENTRY_WORDS_IS1 BITS_TO_DWORD(376)
232#define ENTRY_WORDS_IS2 BITS_TO_DWORD(376)
233#define ES0_ACT_WIDTH BITS_TO_DWORD(91)
234#define ES0_CNT_WIDTH BITS_TO_DWORD(1)
235#define IS1_ACT_WIDTH BITS_TO_DWORD(320)
236#define IS1_CNT_WIDTH BITS_TO_DWORD(4)
237#define IS2_ACT_WIDTH BITS_TO_DWORD(103 - 2 * VSC9953_PORT_OFFSET)
238#define IS2_CNT_WIDTH BITS_TO_DWORD(4 * 32)
239#define ES0_ACT_COUNT (VSC9953_ES0_CNT + VSC9953_MAX_PORTS)
240#define IS1_ACT_COUNT (VSC9953_IS1_CNT + 1)
241#define IS2_ACT_COUNT (VSC9953_IS2_CNT + VSC9953_MAX_PORTS + 2)
242
243/* TCAM entries */
244enum tcam_sel {
245 TCAM_SEL_ENTRY = BIT(0),
246 TCAM_SEL_ACTION = BIT(1),
247 TCAM_SEL_COUNTER = BIT(2),
248 TCAM_SEL_ALL = VSC9953_BITMASK(3),
249};
250
251enum tcam_cmd {
252 TCAM_CMD_WRITE = 0,
253 TCAM_CMD_READ = 1,
254 TCAM_CMD_MOVE_UP = 2,
255 TCAM_CMD_MOVE_DOWN = 3,
256 TCAM_CMD_INITIALIZE = 4,
257};
258
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200259struct vsc9953_mdio_info {
260 struct vsc9953_mii_mng *regs;
261 char *name;
262};
263
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300264/* VSC9953 ANA structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200265
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300266struct vsc9953_ana_port {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200267 u32 vlan_cfg;
268 u32 drop_cfg;
269 u32 qos_cfg;
270 u32 vcap_cfg;
271 u32 vcap_s1_key_cfg[3];
272 u32 vcap_s2_cfg;
273 u32 qos_pcp_dei_map_cfg[16];
274 u32 cpu_fwd_cfg;
275 u32 cpu_fwd_bpdu_cfg;
276 u32 cpu_fwd_garp_cfg;
277 u32 cpu_fwd_ccm_cfg;
278 u32 port_cfg;
279 u32 pol_cfg;
280 u32 reserved[34];
281};
282
283struct vsc9953_ana_pol {
284 u32 pol_pir_cfg;
285 u32 pol_cir_cfg;
286 u32 pol_mode_cfg;
287 u32 pol_pir_state;
288 u32 pol_cir_state;
289 u32 reserved1[3];
290};
291
292struct vsc9953_ana_ana_tables {
293 u32 entry_lim[11];
294 u32 an_moved;
295 u32 mach_data;
296 u32 macl_data;
297 u32 mac_access;
298 u32 mact_indx;
299 u32 vlan_access;
300 u32 vlan_tidx;
301};
302
303struct vsc9953_ana_ana {
304 u32 adv_learn;
305 u32 vlan_mask;
Codrin Ciubotariu440873d2015-07-24 16:55:24 +0300306 u32 reserved;
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200307 u32 anag_efil;
308 u32 an_events;
309 u32 storm_limit_burst;
310 u32 storm_limit_cfg[4];
311 u32 isolated_prts;
312 u32 community_ports;
313 u32 auto_age;
314 u32 mac_options;
315 u32 learn_disc;
316 u32 agen_ctrl;
317 u32 mirror_ports;
318 u32 emirror_ports;
319 u32 flooding;
320 u32 flooding_ipmc;
321 u32 sflow_cfg[11];
322 u32 port_mode[12];
323};
324
Codrin Ciubotariuaae0e682015-12-15 15:21:06 +0200325#define PGID_DST_START 0
326#define PGID_AGGR_START 64
327#define PGID_SRC_START 80
328
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200329struct vsc9953_ana_pgid {
330 u32 port_grp_id[91];
331};
332
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300333struct vsc9953_ana_pfc {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200334 u32 pfc_cfg;
335 u32 reserved1[15];
336};
337
338struct vsc9953_ana_pol_misc {
339 u32 pol_flowc[10];
340 u32 reserved1[17];
341 u32 pol_hyst;
342};
343
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300344struct vsc9953_ana_common {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200345 u32 aggr_cfg;
346 u32 cpuq_cfg;
347 u32 cpuq_8021_cfg;
348 u32 dscp_cfg;
349 u32 dscp_rewr_cfg;
350 u32 vcap_rng_type_cfg;
351 u32 vcap_rng_val_cfg;
352 u32 discard_cfg;
353 u32 fid_cfg;
354};
355
356struct vsc9953_analyzer {
357 struct vsc9953_ana_port port[11];
358 u32 reserved1[9536];
359 struct vsc9953_ana_pol pol[164];
360 struct vsc9953_ana_ana_tables ana_tables;
361 u32 reserved2[14];
362 struct vsc9953_ana_ana ana;
Codrin Ciubotariu96979dc2015-12-15 15:21:02 +0200363 u32 reserved3[21];
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200364 struct vsc9953_ana_pgid port_id_tbl;
365 u32 reserved4[549];
366 struct vsc9953_ana_pfc pfc[10];
367 struct vsc9953_ana_pol_misc pol_misc;
368 u32 reserved5[196];
369 struct vsc9953_ana_common common;
370};
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300371/* END VSC9953 ANA structure t*/
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200372
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300373/* VSC9953 DEV_GMII structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200374
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300375struct vsc9953_dev_gmii_port_mode {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200376 u32 clock_cfg;
377 u32 port_misc;
378 u32 reserved1;
379 u32 eee_cfg;
380};
381
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300382struct vsc9953_dev_gmii_mac_cfg_status {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200383 u32 mac_ena_cfg;
384 u32 mac_mode_cfg;
385 u32 mac_maxlen_cfg;
386 u32 mac_tags_cfg;
387 u32 mac_adv_chk_cfg;
388 u32 mac_ifg_cfg;
389 u32 mac_hdx_cfg;
390 u32 mac_fc_mac_low_cfg;
391 u32 mac_fc_mac_high_cfg;
392 u32 mac_sticky;
393};
394
395struct vsc9953_dev_gmii {
396 struct vsc9953_dev_gmii_port_mode port_mode;
397 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
398};
399
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300400/* END VSC9953 DEV_GMII structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200401
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300402/* VSC9953 QSYS structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200403
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300404struct vsc9953_qsys_hsch {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200405 u32 cir_cfg;
406 u32 reserved1;
407 u32 se_cfg;
408 u32 se_dwrr_cfg[8];
409 u32 cir_state;
410 u32 reserved2[20];
411};
412
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300413struct vsc9953_qsys_sys {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200414 u32 port_mode[12];
415 u32 switch_port_mode[11];
416 u32 stat_cnt_cfg;
417 u32 eee_cfg[10];
418 u32 eee_thrs;
419 u32 igr_no_sharing;
420 u32 egr_no_sharing;
421 u32 sw_status[11];
422 u32 ext_cpu_cfg;
423 u32 cpu_group_map;
424 u32 reserved1[23];
425};
426
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300427struct vsc9953_qsys_qos_cfg {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200428 u32 red_profile[16];
429 u32 res_qos_mode;
430};
431
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300432struct vsc9953_qsys_drop_cfg {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200433 u32 egr_drop_mode;
434};
435
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300436struct vsc9953_qsys_mmgt {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200437 u32 eq_cntrl;
438 u32 reserved1;
439};
440
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300441struct vsc9953_qsys_hsch_misc {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200442 u32 hsch_misc_cfg;
443 u32 reserved1[546];
444};
445
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300446struct vsc9953_qsys_res_ctrl {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200447 u32 res_cfg;
448 u32 res_stat;
449
450};
451
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300452struct vsc9953_qsys_reg {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200453 struct vsc9953_qsys_hsch hsch[108];
454 struct vsc9953_qsys_sys sys;
455 struct vsc9953_qsys_qos_cfg qos_cfg;
456 struct vsc9953_qsys_drop_cfg drop_cfg;
457 struct vsc9953_qsys_mmgt mmgt;
458 struct vsc9953_qsys_hsch_misc hsch_misc;
459 struct vsc9953_qsys_res_ctrl res_ctrl[1024];
460};
461
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300462/* END VSC9953 QSYS structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200463
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300464/* VSC9953 SYS structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200465
Codrin Ciubotariu86719f02015-07-24 16:55:29 +0300466struct vsc9953_rx_cntrs {
467 u32 c_rx_oct;
468 u32 c_rx_uc;
469 u32 c_rx_mc;
470 u32 c_rx_bc;
471 u32 c_rx_short;
472 u32 c_rx_frag;
473 u32 c_rx_jabber;
474 u32 c_rx_crc;
475 u32 c_rx_symbol_err;
476 u32 c_rx_sz_64;
477 u32 c_rx_sz_65_127;
478 u32 c_rx_sz_128_255;
479 u32 c_rx_sz_256_511;
480 u32 c_rx_sz_512_1023;
481 u32 c_rx_sz_1024_1526;
482 u32 c_rx_sz_jumbo;
483 u32 c_rx_pause;
484 u32 c_rx_control;
485 u32 c_rx_long;
486 u32 c_rx_cat_drop;
487 u32 c_rx_red_prio_0;
488 u32 c_rx_red_prio_1;
489 u32 c_rx_red_prio_2;
490 u32 c_rx_red_prio_3;
491 u32 c_rx_red_prio_4;
492 u32 c_rx_red_prio_5;
493 u32 c_rx_red_prio_6;
494 u32 c_rx_red_prio_7;
495 u32 c_rx_yellow_prio_0;
496 u32 c_rx_yellow_prio_1;
497 u32 c_rx_yellow_prio_2;
498 u32 c_rx_yellow_prio_3;
499 u32 c_rx_yellow_prio_4;
500 u32 c_rx_yellow_prio_5;
501 u32 c_rx_yellow_prio_6;
502 u32 c_rx_yellow_prio_7;
503 u32 c_rx_green_prio_0;
504 u32 c_rx_green_prio_1;
505 u32 c_rx_green_prio_2;
506 u32 c_rx_green_prio_3;
507 u32 c_rx_green_prio_4;
508 u32 c_rx_green_prio_5;
509 u32 c_rx_green_prio_6;
510 u32 c_rx_green_prio_7;
511 u32 reserved[20];
512};
513
514struct vsc9953_tx_cntrs {
515 u32 c_tx_oct;
516 u32 c_tx_uc;
517 u32 c_tx_mc;
518 u32 c_tx_bc;
519 u32 c_tx_col;
520 u32 c_tx_drop;
521 u32 c_tx_pause;
522 u32 c_tx_sz_64;
523 u32 c_tx_sz_65_127;
524 u32 c_tx_sz_128_255;
525 u32 c_tx_sz_256_511;
526 u32 c_tx_sz_512_1023;
527 u32 c_tx_sz_1024_1526;
528 u32 c_tx_sz_jumbo;
529 u32 c_tx_yellow_prio_0;
530 u32 c_tx_yellow_prio_1;
531 u32 c_tx_yellow_prio_2;
532 u32 c_tx_yellow_prio_3;
533 u32 c_tx_yellow_prio_4;
534 u32 c_tx_yellow_prio_5;
535 u32 c_tx_yellow_prio_6;
536 u32 c_tx_yellow_prio_7;
537 u32 c_tx_green_prio_0;
538 u32 c_tx_green_prio_1;
539 u32 c_tx_green_prio_2;
540 u32 c_tx_green_prio_3;
541 u32 c_tx_green_prio_4;
542 u32 c_tx_green_prio_5;
543 u32 c_tx_green_prio_6;
544 u32 c_tx_green_prio_7;
545 u32 c_tx_aged;
546 u32 reserved[33];
547};
548
549struct vsc9953_drop_cntrs {
550 u32 c_dr_local;
551 u32 c_dr_tail;
552 u32 c_dr_yellow_prio_0;
553 u32 c_dr_yellow_prio_1;
554 u32 c_dr_yellow_prio_2;
555 u32 c_dr_yellow_prio_3;
556 u32 c_dr_yellow_prio_4;
557 u32 c_dr_yellow_prio_5;
558 u32 c_dr_yellow_prio_6;
559 u32 c_dr_yellow_prio_7;
560 u32 c_dr_green_prio_0;
561 u32 c_dr_green_prio_1;
562 u32 c_dr_green_prio_2;
563 u32 c_dr_green_prio_3;
564 u32 c_dr_green_prio_4;
565 u32 c_dr_green_prio_5;
566 u32 c_dr_green_prio_6;
567 u32 c_dr_green_prio_7;
568 u32 reserved[46];
569};
570
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300571struct vsc9953_sys_stat {
Codrin Ciubotariu86719f02015-07-24 16:55:29 +0300572 struct vsc9953_rx_cntrs rx_cntrs;
573 struct vsc9953_tx_cntrs tx_cntrs;
574 struct vsc9953_drop_cntrs drop_cntrs;
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200575 u32 reserved1[6];
576};
577
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300578struct vsc9953_sys_sys {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200579 u32 reset_cfg;
580 u32 reserved1;
581 u32 vlan_etype_cfg;
582 u32 port_mode[12];
583 u32 front_port_mode[10];
584 u32 frame_aging;
585 u32 stat_cfg;
586 u32 reserved2[50];
587};
588
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300589struct vsc9953_sys_pause_cfg {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200590 u32 pause_cfg[11];
591 u32 pause_tot_cfg;
592 u32 tail_drop_level[11];
593 u32 tot_tail_drop_lvl;
594 u32 mac_fc_cfg[10];
595};
596
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300597struct vsc9953_sys_mmgt {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200598 u16 free_cnt;
599};
600
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300601struct vsc9953_system_reg {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200602 struct vsc9953_sys_stat stat;
603 struct vsc9953_sys_sys sys;
604 struct vsc9953_sys_pause_cfg pause_cfg;
605 struct vsc9953_sys_mmgt mmgt;
606};
607
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300608/* END VSC9953 SYS structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200609
Codrin Ciubotariu9de05982015-07-24 16:55:26 +0300610/* VSC9953 REW structure */
611
612struct vsc9953_rew_port {
613 u32 port_vlan_cfg;
614 u32 port_tag_cfg;
615 u32 port_port_cfg;
616 u32 port_dscp_cfg;
617 u32 port_pcp_dei_qos_map_cfg[16];
618 u32 reserved[12];
619};
620
621struct vsc9953_rew_common {
622 u32 reserve[4];
623 u32 dscp_remap_dp1_cfg[64];
624 u32 dscp_remap_cfg[64];
625};
626
627struct vsc9953_rew_reg {
628 struct vsc9953_rew_port port[12];
629 struct vsc9953_rew_common common;
630};
631
632/* END VSC9953 REW structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200633
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300634/* VSC9953 DEVCPU_GCB structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200635
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300636struct vsc9953_chip_regs {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200637 u32 chipd_id;
638 u32 gpr;
639 u32 soft_rst;
640};
641
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300642struct vsc9953_gpio {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200643 u32 gpio_out_set[10];
644 u32 gpio_out_clr[10];
645 u32 gpio_out[10];
646 u32 gpio_in[10];
647};
648
649struct vsc9953_mii_mng {
650 u32 miimstatus;
651 u32 reserved1;
652 u32 miimcmd;
653 u32 miimdata;
654 u32 miimcfg;
655 u32 miimscan_0;
656 u32 miimscan_1;
657 u32 miiscan_lst_rslts;
658 u32 miiscan_lst_rslts_valid;
659};
660
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300661struct vsc9953_mii_read_scan {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200662 u32 mii_scan_results_sticky[2];
663};
664
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300665struct vsc9953_devcpu_gcb {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200666 struct vsc9953_chip_regs chip_regs;
667 struct vsc9953_gpio gpio;
668 struct vsc9953_mii_mng mii_mng[2];
669 struct vsc9953_mii_read_scan mii_read_scan;
670};
671
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300672/* END VSC9953 DEVCPU_GCB structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200673
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300674/* VSC9953 IS* structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200675
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300676struct vsc9953_vcap_core_cfg {
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200677 u32 vcap_update_ctrl;
678 u32 vcap_mv_cfg;
679};
680
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300681struct vsc9953_vcap {
682 struct vsc9953_vcap_core_cfg vcap_core_cfg;
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200683};
684
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300685/* END VSC9953 IS* structure */
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200686
687#define VSC9953_PORT_INFO_INITIALIZER(idx) \
688{ \
689 .enabled = 0, \
690 .phyaddr = 0, \
691 .index = idx, \
692 .phy_regs = NULL, \
693 .enet_if = PHY_INTERFACE_MODE_NONE, \
694 .bus = NULL, \
695 .phydev = NULL, \
696}
697
698/* Structure to describe a VSC9953 port */
699struct vsc9953_port_info {
700 u8 enabled;
701 u8 phyaddr;
702 int index;
703 void *phy_regs;
704 phy_interface_t enet_if;
705 struct mii_dev *bus;
706 struct phy_device *phydev;
707};
708
709/* Structure to describe a VSC9953 switch */
710struct vsc9953_info {
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300711 struct vsc9953_port_info port[VSC9953_MAX_PORTS];
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200712};
713
714void vsc9953_init(bd_t *bis);
715
Codrin Ciubotariu3cc8cff2015-07-24 16:52:45 +0300716void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
717void vsc9953_port_info_set_phy_address(int port_no, int address);
718void vsc9953_port_enable(int port_no);
719void vsc9953_port_disable(int port_no);
720void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
Codrin Ciubotariu6706b112015-01-12 14:08:33 +0200721
722#endif /* _VSC9953_H_ */