blob: 69ce13cf45a6ca169fecfd1a133cc7fc623d5b63 [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +00007 */
8
wdenk0ac6f8b2004-07-09 23:27:13 +00009/*
10 * mpc8560ads board configuration file
11 *
12 * Please refer to doc/README.mpc85xx for more info.
13 *
14 * Make sure you change the MAC address and other network params first,
Joe Hershberger92ac5202015-05-04 14:55:14 -050015 * search for CONFIG_SERVERIP, etc. in this file.
wdenk42d1f032003-10-15 23:53:47 +000016 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
York Sun9ae14ca2015-08-18 12:35:52 -070021#define CONFIG_DISPLAY_BOARDINFO
22
wdenk42d1f032003-10-15 23:53:47 +000023/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000024#define CONFIG_BOOKE 1 /* BOOKE */
25#define CONFIG_E500 1 /* BOOKE e500 family */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050026#define CONFIG_CPM2 1 /* has CPM2 */
wdenk0ac6f8b2004-07-09 23:27:13 +000027#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
Kumar Galaf0600542008-06-11 00:44:10 -050028#define CONFIG_MPC8560 1
wdenk42d1f032003-10-15 23:53:47 +000029
Wolfgang Denk2ae18242010-10-06 09:05:45 +020030/*
31 * default CCARBAR is at 0xff700000
32 * assume U-Boot is less than 0.5MB
33 */
34#define CONFIG_SYS_TEXT_BASE 0xfff80000
35
wdenk0ac6f8b2004-07-09 23:27:13 +000036#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000037#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala0151cba2008-10-21 11:33:58 -050038#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020039#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Flemingccc091a2007-05-08 17:27:43 -050040#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000041#define CONFIG_ENV_OVERWRITE
Kumar Gala7232a272008-01-16 01:32:06 -060042#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Peter Tyser004eca02009-09-16 22:03:08 -050043#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk42d1f032003-10-15 23:53:47 +000044
wdenk0ac6f8b2004-07-09 23:27:13 +000045/*
46 * sysclk for MPC85xx
47 *
48 * Two valid values are:
49 * 33000000
50 * 66000000
51 *
52 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000053 * is likely the desired value here, so that is now the default.
54 * The board, however, can run at 66MHz. In any event, this value
55 * must match the settings of some switches. Details can be found
56 * in the README.mpc85xxads.
wdenk0ac6f8b2004-07-09 23:27:13 +000057 */
58
wdenk9aea9532004-08-01 23:02:45 +000059#ifndef CONFIG_SYS_CLK_FREQ
60#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000061#endif
62
wdenk9aea9532004-08-01 23:02:45 +000063
wdenk0ac6f8b2004-07-09 23:27:13 +000064/*
65 * These can be toggled for performance analysis, otherwise use default.
66 */
67#define CONFIG_L2_CACHE /* toggle L2 cache */
68#define CONFIG_BTB /* toggle branch predition */
wdenk42d1f032003-10-15 23:53:47 +000069
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
wdenk42d1f032003-10-15 23:53:47 +000071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
73#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000074
Timur Tabie46fedf2011-08-04 18:03:41 -050075#define CONFIG_SYS_CCSRBAR 0xe0000000
76#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk42d1f032003-10-15 23:53:47 +000077
Jon Loeliger8b625112008-03-18 11:12:44 -050078/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070079#define CONFIG_SYS_FSL_DDR1
Jon Loeliger8b625112008-03-18 11:12:44 -050080#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
81#define CONFIG_DDR_SPD
82#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk9aea9532004-08-01 23:02:45 +000083
Jon Loeliger8b625112008-03-18 11:12:44 -050084#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
85
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
87#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +000088
Jon Loeliger8b625112008-03-18 11:12:44 -050089#define CONFIG_NUM_DDR_CONTROLLERS 1
90#define CONFIG_DIMM_SLOTS_PER_CTLR 1
91#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +000092
Jon Loeliger8b625112008-03-18 11:12:44 -050093/* I2C addresses of SPD EEPROMs */
94#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +000095
Jon Loeliger8b625112008-03-18 11:12:44 -050096/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
98#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
99#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
100#define CONFIG_SYS_DDR_TIMING_1 0x37344321
101#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
102#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
103#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
104#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +0000105
wdenk0ac6f8b2004-07-09 23:27:13 +0000106/*
107 * SDRAM on the Local Bus
108 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
110#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
113#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
116#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
117#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
118#undef CONFIG_SYS_FLASH_CHECKSUM
119#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
120#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000121
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200122#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
125#define CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000126#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#undef CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000128#endif
129
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200130#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_FLASH_CFI
132#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk0ac6f8b2004-07-09 23:27:13 +0000133
134#undef CONFIG_CLOCKS_IN_MHZ
wdenk42d1f032003-10-15 23:53:47 +0000135
wdenk42d1f032003-10-15 23:53:47 +0000136
wdenk0ac6f8b2004-07-09 23:27:13 +0000137/*
138 * Local Bus Definitions
139 */
140
141/*
142 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0ac6f8b2004-07-09 23:27:13 +0000144 *
145 * For BR2, need:
146 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
147 * port-size = 32-bits = BR2[19:20] = 11
148 * no parity checking = BR2[21:22] = 00
149 * SDRAM for MSEL = BR2[24:26] = 011
150 * Valid = BR[31] = 1
151 *
152 * 0 4 8 12 16 20 24 28
153 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
154 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0ac6f8b2004-07-09 23:27:13 +0000156 * FIXME: the top 17 bits of BR2.
157 */
158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0ac6f8b2004-07-09 23:27:13 +0000160
161/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0ac6f8b2004-07-09 23:27:13 +0000163 *
164 * For OR2, need:
165 * 64MB mask for AM, OR2[0:7] = 1111 1100
166 * XAM, OR2[17:18] = 11
167 * 9 columns OR2[19-21] = 010
168 * 13 rows OR2[23-25] = 100
169 * EAD set for extra time OR[31] = 1
170 *
171 * 0 4 8 12 16 20 24 28
172 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
173 */
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
178#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
179#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
180#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000181
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500182#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
183 | LSDMR_RFCR5 \
184 | LSDMR_PRETOACT3 \
185 | LSDMR_ACTTORW3 \
186 | LSDMR_BL8 \
187 | LSDMR_WRC2 \
188 | LSDMR_CL3 \
189 | LSDMR_RFEN \
wdenk0ac6f8b2004-07-09 23:27:13 +0000190 )
191
192/*
193 * SDRAM Controller configuration sequence.
194 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500195#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
196#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
197#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
198#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
199#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000200
wdenk42d1f032003-10-15 23:53:47 +0000201
wdenk9aea9532004-08-01 23:02:45 +0000202/*
203 * 32KB, 8-bit wide for ADS config reg
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_BR4_PRELIM 0xf8000801
206#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
207#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_INIT_RAM_LOCK 1
210#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200211#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000212
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200213#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
217#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000218
219/* Serial Port */
wdenk0ac6f8b2004-07-09 23:27:13 +0000220#define CONFIG_CONS_ON_SCC /* define if console on SCC */
221#undef CONFIG_CONS_NONE /* define if console on something else */
222#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
wdenk42d1f032003-10-15 23:53:47 +0000223
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200224#define CONFIG_BAUDRATE 115200
wdenk42d1f032003-10-15 23:53:47 +0000225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000227 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
228
229/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_HUSH_PARSER
231#ifdef CONFIG_SYS_HUSH_PARSER
wdenk42d1f032003-10-15 23:53:47 +0000232#endif
233
Matthew McClintock0e163872006-06-28 10:43:36 -0500234/* pass open firmware flat tree */
Kumar Gala5ce71582007-11-28 22:40:31 -0600235#define CONFIG_OF_LIBFDT 1
236#define CONFIG_OF_BOARD_SETUP 1
237#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500238
Jon Loeliger20476722006-10-20 15:50:15 -0500239/*
240 * I2C
241 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200242#define CONFIG_SYS_I2C
243#define CONFIG_SYS_I2C_FSL
244#define CONFIG_SYS_FSL_I2C_SPEED 400000
245#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
246#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
247#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk42d1f032003-10-15 23:53:47 +0000248
wdenk0ac6f8b2004-07-09 23:27:13 +0000249/* RapidIO MMU */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600250#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala10795f42008-12-02 16:08:36 -0600251#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600252#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk42d1f032003-10-15 23:53:47 +0000254
wdenk0ac6f8b2004-07-09 23:27:13 +0000255/*
256 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300257 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000258 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600259#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600260#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600261#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600263#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600264#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
266#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000267
268#if defined(CONFIG_PCI)
269
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200270#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000271
272#undef CONFIG_EEPRO100
wdenk42d1f032003-10-15 23:53:47 +0000273#undef CONFIG_TULIP
wdenk0ac6f8b2004-07-09 23:27:13 +0000274
275#if !defined(CONFIG_PCI_PNP)
276 #define PCI_ENET0_IOADDR 0xe0000000
277 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200278 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000279#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000280
281#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0ac6f8b2004-07-09 23:27:13 +0000283
284#endif /* CONFIG_PCI */
285
286
Andy Flemingccc091a2007-05-08 17:27:43 -0500287#ifdef CONFIG_TSEC_ENET
wdenk0ac6f8b2004-07-09 23:27:13 +0000288
Andy Flemingccc091a2007-05-08 17:27:43 -0500289#ifndef CONFIG_MII
wdenk0ac6f8b2004-07-09 23:27:13 +0000290#define CONFIG_MII 1 /* MII PHY management */
Andy Flemingccc091a2007-05-08 17:27:43 -0500291#endif
Kim Phillips255a35772007-05-16 16:52:19 -0500292#define CONFIG_TSEC1 1
293#define CONFIG_TSEC1_NAME "TSEC0"
294#define CONFIG_TSEC2 1
295#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000296#define TSEC1_PHY_ADDR 0
297#define TSEC2_PHY_ADDR 1
298#define TSEC1_PHYIDX 0
299#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500300#define TSEC1_FLAGS TSEC_GIGABIT
301#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500302
303/* Options are: TSEC[0-1] */
304#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000305
Andy Flemingccc091a2007-05-08 17:27:43 -0500306#endif /* CONFIG_TSEC_ENET */
wdenk0ac6f8b2004-07-09 23:27:13 +0000307
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200308#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
Andy Flemingccc091a2007-05-08 17:27:43 -0500309
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200310#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk0ac6f8b2004-07-09 23:27:13 +0000311#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
312
313#if (CONFIG_ETHER_INDEX == 2)
wdenk42d1f032003-10-15 23:53:47 +0000314 /*
315 * - Rx-CLK is CLK13
316 * - Tx-CLK is CLK14
317 * - Select bus for bd/buffers
318 * - Full duplex
319 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000320 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
321 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
323 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk42d1f032003-10-15 23:53:47 +0000324 #define FETH2_RST 0x01
wdenk0ac6f8b2004-07-09 23:27:13 +0000325#elif (CONFIG_ETHER_INDEX == 3)
wdenk42d1f032003-10-15 23:53:47 +0000326 /* need more definitions here for FE3 */
327 #define FETH3_RST 0x80
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200328#endif /* CONFIG_ETHER_INDEX */
wdenk0ac6f8b2004-07-09 23:27:13 +0000329
Andy Flemingccc091a2007-05-08 17:27:43 -0500330#ifndef CONFIG_MII
331#define CONFIG_MII 1 /* MII PHY management */
332#endif
333
wdenk0ac6f8b2004-07-09 23:27:13 +0000334#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
335
wdenk42d1f032003-10-15 23:53:47 +0000336/*
337 * GPIO pins used for bit-banged MII communications
338 */
339#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200340#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
341 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
342#define MDC_DECLARE MDIO_DECLARE
343
wdenk42d1f032003-10-15 23:53:47 +0000344#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
345#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
346#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
347
348#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
349 else iop->pdat &= ~0x00400000
350
351#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
352 else iop->pdat &= ~0x00200000
353
354#define MIIDELAY udelay(1)
wdenk0ac6f8b2004-07-09 23:27:13 +0000355
wdenk42d1f032003-10-15 23:53:47 +0000356#endif
357
wdenk0ac6f8b2004-07-09 23:27:13 +0000358
359/*
360 * Environment
361 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200363 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200365 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
366 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000367#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200369 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200371 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000372#endif
373
wdenk0ac6f8b2004-07-09 23:27:13 +0000374#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000376
Jon Loeliger2835e512007-06-13 13:22:08 -0500377/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500378 * BOOTP options
379 */
380#define CONFIG_BOOTP_BOOTFILESIZE
381#define CONFIG_BOOTP_BOOTPATH
382#define CONFIG_BOOTP_GATEWAY
383#define CONFIG_BOOTP_HOSTNAME
384
385
386/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500387 * Command line configuration.
388 */
Jon Loeliger2835e512007-06-13 13:22:08 -0500389#define CONFIG_CMD_PING
390#define CONFIG_CMD_I2C
Kumar Gala1c9aa762008-09-22 23:40:42 -0500391#define CONFIG_CMD_IRQ
Becky Bruce199e2622010-06-17 11:37:25 -0500392#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500393
394#if defined(CONFIG_PCI)
395 #define CONFIG_CMD_PCI
wdenk42d1f032003-10-15 23:53:47 +0000396#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000397
Jon Loeliger2835e512007-06-13 13:22:08 -0500398#if defined(CONFIG_ETHER_ON_FCC)
399 #define CONFIG_CMD_MII
400#endif
401
wdenk0ac6f8b2004-07-09 23:27:13 +0000402#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000403
404/*
405 * Miscellaneous configurable options
406 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500408#define CONFIG_CMDLINE_EDITING /* Command-line editing */
409#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
wdenk0ac6f8b2004-07-09 23:27:13 +0000411
Jon Loeliger2835e512007-06-13 13:22:08 -0500412#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000414#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000416#endif
417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
419#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
420#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000421
422/*
423 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500424 * have to be in the first 64 MB of memory, since this is
wdenk42d1f032003-10-15 23:53:47 +0000425 * the maximum mapped by the Linux kernel during initialization.
426 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500427#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
428#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk42d1f032003-10-15 23:53:47 +0000429
Jon Loeliger2835e512007-06-13 13:22:08 -0500430#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000431#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk42d1f032003-10-15 23:53:47 +0000432#endif
433
wdenk9aea9532004-08-01 23:02:45 +0000434
435/*
436 * Environment Configuration
437 */
wdenk42d1f032003-10-15 23:53:47 +0000438#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500439#define CONFIG_HAS_ETH0
wdenke2ffd592004-12-31 09:32:47 +0000440#define CONFIG_HAS_ETH1
wdenke2ffd592004-12-31 09:32:47 +0000441#define CONFIG_HAS_ETH2
Kumar Gala5ce71582007-11-28 22:40:31 -0600442#define CONFIG_HAS_ETH3
wdenk42d1f032003-10-15 23:53:47 +0000443#endif
444
wdenk0ac6f8b2004-07-09 23:27:13 +0000445#define CONFIG_IPADDR 192.168.1.253
446
447#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000448#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000449#define CONFIG_BOOTFILE "your.uImage"
wdenk0ac6f8b2004-07-09 23:27:13 +0000450
451#define CONFIG_SERVERIP 192.168.1.1
452#define CONFIG_GATEWAYIP 192.168.1.1
453#define CONFIG_NETMASK 255.255.255.0
454
455#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
456
wdenk9aea9532004-08-01 23:02:45 +0000457#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
wdenk0ac6f8b2004-07-09 23:27:13 +0000458#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
459
460#define CONFIG_BAUDRATE 115200
461
wdenk9aea9532004-08-01 23:02:45 +0000462#define CONFIG_EXTRA_ENV_SETTINGS \
Andy Fleming6b44a442008-07-14 20:04:40 -0500463 "netdev=eth0\0" \
464 "consoledev=ttyCPM\0" \
465 "ramdiskaddr=1000000\0" \
466 "ramdiskfile=your.ramdisk.u-boot\0" \
467 "fdtaddr=400000\0" \
468 "fdtfile=mpc8560ads.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000469
wdenk9aea9532004-08-01 23:02:45 +0000470#define CONFIG_NFSBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500471 "setenv bootargs root=/dev/nfs rw " \
472 "nfsroot=$serverip:$rootpath " \
473 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
474 "console=$consoledev,$baudrate $othbootargs;" \
475 "tftp $loadaddr $bootfile;" \
476 "tftp $fdtaddr $fdtfile;" \
477 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000478
479#define CONFIG_RAMBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500480 "setenv bootargs root=/dev/ram rw " \
481 "console=$consoledev,$baudrate $othbootargs;" \
482 "tftp $ramdiskaddr $ramdiskfile;" \
483 "tftp $loadaddr $bootfile;" \
484 "tftp $fdtaddr $fdtfile;" \
485 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000486
487#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000488
489#endif /* __CONFIG_H */