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Kumar Gala129ba612008-08-12 11:13:08 -05001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
Kumar Gala129ba612008-08-12 11:13:08 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala129ba612008-08-12 11:13:08 -05005 */
6
7/*
8 * mpc8572ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
York Sun15672c62014-04-30 14:43:49 -070014#define CONFIG_DISPLAY_BOARDINFO
15
Kumar Gala509c4c42010-05-21 04:05:14 -050016#include "../board/freescale/common/ics307_clk.h"
17
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020018#ifdef CONFIG_36BIT
Kumar Galaf9edcc12009-09-10 16:23:45 -050019#define CONFIG_PHYS_64BIT
20#endif
21
Kumar Galacb14e932010-11-12 08:22:01 -060022#ifndef CONFIG_SYS_TEXT_BASE
York Sun18025752014-04-25 12:06:17 -070023#define CONFIG_SYS_TEXT_BASE 0xeff40000
Kumar Galacb14e932010-11-12 08:22:01 -060024#endif
25
Kumar Gala7a577fd2011-01-12 02:48:53 -060026#ifndef CONFIG_RESET_VECTOR_ADDRESS
27#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
28#endif
29
Kumar Galacb14e932010-11-12 08:22:01 -060030#ifndef CONFIG_SYS_MONITOR_BASE
31#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
32#endif
33
Kumar Gala129ba612008-08-12 11:13:08 -050034/* High Level Configuration Options */
35#define CONFIG_BOOKE 1 /* BOOKE */
36#define CONFIG_E500 1 /* BOOKE e500 family */
Kumar Gala129ba612008-08-12 11:13:08 -050037#define CONFIG_MPC8572 1
38#define CONFIG_MPC8572DS 1
39#define CONFIG_MP 1 /* support multiple processors */
Kumar Gala129ba612008-08-12 11:13:08 -050040
Kumar Galac51fc5d2009-01-23 14:22:13 -060041#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Kumar Gala129ba612008-08-12 11:13:08 -050042#define CONFIG_PCI 1 /* Enable PCI/PCIE */
43#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
44#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
45#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
46#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000047#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala129ba612008-08-12 11:13:08 -050048#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050049#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala129ba612008-08-12 11:13:08 -050050
51#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
52
53#define CONFIG_TSEC_ENET /* tsec ethernet support */
54#define CONFIG_ENV_OVERWRITE
55
Kumar Gala509c4c42010-05-21 04:05:14 -050056#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
57#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
Haiying Wang4ca06602008-10-03 12:37:41 -040058#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala129ba612008-08-12 11:13:08 -050059
60/*
61 * These can be toggled for performance analysis, otherwise use default.
62 */
63#define CONFIG_L2_CACHE /* toggle L2 cache */
64#define CONFIG_BTB /* toggle branch predition */
Kumar Gala129ba612008-08-12 11:13:08 -050065
66#define CONFIG_ENABLE_36BIT_PHYS 1
67
Kumar Gala18af1c52009-01-23 14:22:14 -060068#ifdef CONFIG_PHYS_64BIT
69#define CONFIG_ADDR_MAP 1
70#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
71#endif
72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
74#define CONFIG_SYS_MEMTEST_END 0x7fffffff
Kumar Gala129ba612008-08-12 11:13:08 -050075#define CONFIG_PANIC_HANG /* do not reset board on panic */
76
77/*
Kumar Galacb14e932010-11-12 08:22:01 -060078 * Config the L2 Cache as L2 SRAM
79 */
80#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
81#ifdef CONFIG_PHYS_64BIT
82#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
83#else
84#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
85#endif
86#define CONFIG_SYS_L2_SIZE (512 << 10)
87#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
88
Timur Tabie46fedf2011-08-04 18:03:41 -050089#define CONFIG_SYS_CCSRBAR 0xffe00000
90#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala129ba612008-08-12 11:13:08 -050091
Kumar Gala8d22ddc2011-11-09 09:10:49 -060092#if defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -050093#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Kumar Galacb14e932010-11-12 08:22:01 -060094#endif
95
Kumar Gala129ba612008-08-12 11:13:08 -050096/* DDR Setup */
Kumar Galaf8523cb2009-02-06 09:56:35 -060097#define CONFIG_VERY_BIG_RAM
York Sun5614e712013-09-30 09:22:09 -070098#define CONFIG_SYS_FSL_DDR2
Kumar Gala129ba612008-08-12 11:13:08 -050099#undef CONFIG_FSL_DDR_INTERACTIVE
100#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
101#define CONFIG_DDR_SPD
Kumar Gala129ba612008-08-12 11:13:08 -0500102
York Sund34897d2011-01-25 21:51:29 -0800103#define CONFIG_DDR_ECC
Dave Liu9b0ad1b2008-10-28 17:53:38 +0800104#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
Kumar Gala129ba612008-08-12 11:13:08 -0500105#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
108#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala129ba612008-08-12 11:13:08 -0500109
110#define CONFIG_NUM_DDR_CONTROLLERS 2
111#define CONFIG_DIMM_SLOTS_PER_CTLR 1
112#define CONFIG_CHIP_SELECTS_PER_CTRL 2
113
114/* I2C addresses of SPD EEPROMs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500116#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
117#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
118
119/* These are used when DDR doesn't use SPD. */
Dave Liudc889e82008-11-28 20:16:58 +0800120#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
121#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
122#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
123#define CONFIG_SYS_DDR_TIMING_3 0x00020000
124#define CONFIG_SYS_DDR_TIMING_0 0x00260802
125#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
126#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
127#define CONFIG_SYS_DDR_MODE_1 0x00440462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_DDR_MODE_2 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800129#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
Dave Liudc889e82008-11-28 20:16:58 +0800131#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
132#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800134#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
135#define CONFIG_SYS_DDR_CONTROL2 0x24400000
Kumar Gala129ba612008-08-12 11:13:08 -0500136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
138#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
139#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala129ba612008-08-12 11:13:08 -0500140
141/*
Kumar Gala129ba612008-08-12 11:13:08 -0500142 * Make sure required options are set
143 */
144#ifndef CONFIG_SPD_EEPROM
145#error ("CONFIG_SPD_EEPROM is required")
146#endif
147
148#undef CONFIG_CLOCKS_IN_MHZ
149
150/*
151 * Memory map
152 *
153 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
154 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
155 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
156 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
157 *
158 * Localbus cacheable (TBD)
159 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
160 *
161 * Localbus non-cacheable
162 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
163 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100164 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala129ba612008-08-12 11:13:08 -0500165 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
166 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
167 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
168 */
169
170/*
171 * Local Bus Definitions
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala18af1c52009-01-23 14:22:14 -0600174#ifdef CONFIG_PHYS_64BIT
175#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
176#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600177#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600178#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500179
Kumar Galacb14e932010-11-12 08:22:01 -0600180
181#define CONFIG_FLASH_BR_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000182 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
Kumar Galacb14e932010-11-12 08:22:01 -0600183#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500184
Kumar Galac953ddf2008-12-02 14:19:34 -0600185#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
186#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500187
Kumar Gala18af1c52009-01-23 14:22:14 -0600188#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala129ba612008-08-12 11:13:08 -0500190#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
193#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
194#undef CONFIG_SYS_FLASH_CHECKSUM
195#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
196#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala129ba612008-08-12 11:13:08 -0500197
Kumar Galacb14e932010-11-12 08:22:01 -0600198#undef CONFIG_SYS_RAMBOOT
Kumar Gala129ba612008-08-12 11:13:08 -0500199
200#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_FLASH_CFI
202#define CONFIG_SYS_FLASH_EMPTY_INFO
203#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala129ba612008-08-12 11:13:08 -0500204
205#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
206
Kumar Gala558710b2010-11-19 08:53:25 -0600207#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala129ba612008-08-12 11:13:08 -0500208#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
209#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala18af1c52009-01-23 14:22:14 -0600210#ifdef CONFIG_PHYS_64BIT
211#define PIXIS_BASE_PHYS 0xfffdf0000ull
212#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600213#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600214#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500215
Kumar Gala52b565f2008-12-02 14:19:33 -0600216#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala129ba612008-08-12 11:13:08 -0500218
219#define PIXIS_ID 0x0 /* Board ID at offset 0 */
220#define PIXIS_VER 0x1 /* Board version at offset 1 */
221#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
222#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
223#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
224#define PIXIS_PWR 0x5 /* PIXIS Power status register */
225#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
226#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
227#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
228#define PIXIS_VCTL 0x10 /* VELA Control Register */
229#define PIXIS_VSTAT 0x11 /* VELA Status Register */
230#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
231#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
232#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
233#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500234#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
235#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
236#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
237#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
238#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500239#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
240#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
241#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
242#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
243#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
244#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
245#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
246#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
247#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
248#define PIXIS_VWATCH 0x24 /* Watchdog Register */
249#define PIXIS_LED 0x25 /* LED Register */
250
Kumar Galacb14e932010-11-12 08:22:01 -0600251#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
252
Kumar Gala129ba612008-08-12 11:13:08 -0500253/* old pixis referenced names */
254#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
255#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
Liu Yu7e183ca2008-10-10 11:40:59 +0800257#define PIXIS_VSPEED2_TSEC1SER 0x8
258#define PIXIS_VSPEED2_TSEC2SER 0x4
259#define PIXIS_VSPEED2_TSEC3SER 0x2
260#define PIXIS_VSPEED2_TSEC4SER 0x1
261#define PIXIS_VCFGEN1_TSEC1SER 0x20
262#define PIXIS_VCFGEN1_TSEC2SER 0x20
263#define PIXIS_VCFGEN1_TSEC3SER 0x20
264#define PIXIS_VCFGEN1_TSEC4SER 0x20
265#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
266 | PIXIS_VSPEED2_TSEC2SER \
267 | PIXIS_VSPEED2_TSEC3SER \
268 | PIXIS_VSPEED2_TSEC4SER)
269#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
270 | PIXIS_VCFGEN1_TSEC2SER \
271 | PIXIS_VCFGEN1_TSEC3SER \
272 | PIXIS_VCFGEN1_TSEC4SER)
Kumar Gala129ba612008-08-12 11:13:08 -0500273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_INIT_RAM_LOCK 1
275#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200276#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala129ba612008-08-12 11:13:08 -0500277
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200278#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
282#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala129ba612008-08-12 11:13:08 -0500283
Kumar Galacb14e932010-11-12 08:22:01 -0600284#ifndef CONFIG_NAND_SPL
Haiying Wangc013b742008-10-29 13:32:59 -0400285#define CONFIG_SYS_NAND_BASE 0xffa00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600286#ifdef CONFIG_PHYS_64BIT
287#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
288#else
Haiying Wangc013b742008-10-29 13:32:59 -0400289#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600290#endif
Kumar Galacb14e932010-11-12 08:22:01 -0600291#else
292#define CONFIG_SYS_NAND_BASE 0xfff00000
293#ifdef CONFIG_PHYS_64BIT
294#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
295#else
296#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
297#endif
298#endif
299
Haiying Wangc013b742008-10-29 13:32:59 -0400300#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
301 CONFIG_SYS_NAND_BASE + 0x40000, \
302 CONFIG_SYS_NAND_BASE + 0x80000,\
303 CONFIG_SYS_NAND_BASE + 0xC0000}
304#define CONFIG_SYS_MAX_NAND_DEVICE 4
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100305#define CONFIG_CMD_NAND 1
306#define CONFIG_NAND_FSL_ELBC 1
Haiying Wangc013b742008-10-29 13:32:59 -0400307#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Prabhakar Kushwaha68ec9c82013-10-04 13:47:58 +0530308#define CONFIG_SYS_NAND_MAX_OOBFREE 5
309#define CONFIG_SYS_NAND_MAX_ECCPOS 56
Haiying Wangc013b742008-10-29 13:32:59 -0400310
Kumar Galacb14e932010-11-12 08:22:01 -0600311/* NAND boot: 4K NAND loader config */
312#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
313#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
314#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
315#define CONFIG_SYS_NAND_U_BOOT_START \
316 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
317#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
318#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
319#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
320
321
Haiying Wangc013b742008-10-29 13:32:59 -0400322/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500323#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
325 | BR_PS_8 /* Port Size = 8 bit */ \
326 | BR_MS_FCM /* MSEL = FCM */ \
327 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500328#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100329 | OR_FCM_PGS /* Large Page*/ \
330 | OR_FCM_CSCT \
331 | OR_FCM_CST \
332 | OR_FCM_CHT \
333 | OR_FCM_SCY_1 \
334 | OR_FCM_TRLX \
335 | OR_FCM_EHTR)
Haiying Wangc013b742008-10-29 13:32:59 -0400336
Kumar Galacb14e932010-11-12 08:22:01 -0600337#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
338#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500339#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
340#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Timur Tabi7ee41102012-07-06 07:39:26 +0000341#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100342 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
343 | BR_PS_8 /* Port Size = 8 bit */ \
344 | BR_MS_FCM /* MSEL = FCM */ \
345 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500346#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Timur Tabi7ee41102012-07-06 07:39:26 +0000347#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100348 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
349 | BR_PS_8 /* Port Size = 8 bit */ \
350 | BR_MS_FCM /* MSEL = FCM */ \
351 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500352#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400353
Timur Tabi7ee41102012-07-06 07:39:26 +0000354#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100355 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
356 | BR_PS_8 /* Port Size = 8 bit */ \
357 | BR_MS_FCM /* MSEL = FCM */ \
358 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500359#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400360
361
Kumar Gala129ba612008-08-12 11:13:08 -0500362/* Serial Port - controlled on board with jumper J8
363 * open - index 2
364 * shorted - index 1
365 */
366#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_NS16550
368#define CONFIG_SYS_NS16550_SERIAL
369#define CONFIG_SYS_NS16550_REG_SIZE 1
370#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Galacb14e932010-11-12 08:22:01 -0600371#ifdef CONFIG_NAND_SPL
372#define CONFIG_NS16550_MIN_FUNCTIONS
373#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala129ba612008-08-12 11:13:08 -0500376 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
379#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Kumar Gala129ba612008-08-12 11:13:08 -0500380
381/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_HUSH_PARSER
Kumar Gala129ba612008-08-12 11:13:08 -0500383
384/*
385 * Pass open firmware flat tree
386 */
387#define CONFIG_OF_LIBFDT 1
388#define CONFIG_OF_BOARD_SETUP 1
389#define CONFIG_OF_STDOUT_VIA_ALIAS 1
390
Kumar Gala129ba612008-08-12 11:13:08 -0500391/* new uImage format support */
392#define CONFIG_FIT 1
393#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
394
395/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200396#define CONFIG_SYS_I2C
397#define CONFIG_SYS_I2C_FSL
398#define CONFIG_SYS_FSL_I2C_SPEED 400000
399#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
400#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
401#define CONFIG_SYS_FSL_I2C2_SPEED 400000
402#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
403#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
404#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
Kumar Gala129ba612008-08-12 11:13:08 -0500406
407/*
Haiying Wang445a7b32008-10-03 11:47:30 -0400408 * I2C2 EEPROM
409 */
410#define CONFIG_ID_EEPROM
411#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_I2C_EEPROM_NXID
Haiying Wang445a7b32008-10-03 11:47:30 -0400413#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
415#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
416#define CONFIG_SYS_EEPROM_BUS_NUM 1
Haiying Wang445a7b32008-10-03 11:47:30 -0400417
418/*
Kumar Gala129ba612008-08-12 11:13:08 -0500419 * General PCI
420 * Memory space is mapped 1-1, but I/O space must start from 0.
421 */
422
Kumar Gala129ba612008-08-12 11:13:08 -0500423/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600424#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600425#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600426#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500427#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600428#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
429#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600430#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600431#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600432#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600434#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600435#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600436#ifdef CONFIG_PHYS_64BIT
437#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
438#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600440#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500442
443/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600444#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600445#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600446#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500447#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600448#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
449#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600450#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600451#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600452#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600454#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600455#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600456#ifdef CONFIG_PHYS_64BIT
457#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
458#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
Kumar Gala18af1c52009-01-23 14:22:14 -0600460#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500462
463/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600464#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600465#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600466#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500467#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600468#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
469#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600470#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600471#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600472#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600474#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600475#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600476#ifdef CONFIG_PHYS_64BIT
477#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
478#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
Kumar Gala18af1c52009-01-23 14:22:14 -0600480#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500482
483#if defined(CONFIG_PCI)
484
485/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600486#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Kumar Gala129ba612008-08-12 11:13:08 -0500487
488/* video */
489#define CONFIG_VIDEO
490
491#if defined(CONFIG_VIDEO)
492#define CONFIG_BIOSEMU
493#define CONFIG_CFB_CONSOLE
494#define CONFIG_VIDEO_SW_CURSOR
495#define CONFIG_VGA_AS_SINGLE_DEVICE
496#define CONFIG_ATI_RADEON_FB
497#define CONFIG_VIDEO_LOGO
498/*#define CONFIG_CONSOLE_CURSOR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500500#endif
501
Kumar Gala129ba612008-08-12 11:13:08 -0500502#define CONFIG_PCI_PNP /* do pci plug-and-play */
503
504#undef CONFIG_EEPRO100
505#undef CONFIG_TULIP
506#undef CONFIG_RTL8139
507
Kumar Gala129ba612008-08-12 11:13:08 -0500508#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600509 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
510 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
Kumar Gala129ba612008-08-12 11:13:08 -0500511 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
512#endif
513
514#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
515#define CONFIG_DOS_PARTITION
516#define CONFIG_SCSI_AHCI
517
518#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -0500519#define CONFIG_LIBATA
Kumar Gala129ba612008-08-12 11:13:08 -0500520#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
522#define CONFIG_SYS_SCSI_MAX_LUN 1
523#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
524#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Kumar Gala129ba612008-08-12 11:13:08 -0500525#endif /* SCSI */
526
527#endif /* CONFIG_PCI */
528
529
530#if defined(CONFIG_TSEC_ENET)
531
Kumar Gala129ba612008-08-12 11:13:08 -0500532#define CONFIG_MII 1 /* MII PHY management */
533#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
534#define CONFIG_TSEC1 1
535#define CONFIG_TSEC1_NAME "eTSEC1"
536#define CONFIG_TSEC2 1
537#define CONFIG_TSEC2_NAME "eTSEC2"
538#define CONFIG_TSEC3 1
539#define CONFIG_TSEC3_NAME "eTSEC3"
540#define CONFIG_TSEC4 1
541#define CONFIG_TSEC4_NAME "eTSEC4"
542
Liu Yu7e183ca2008-10-10 11:40:59 +0800543#define CONFIG_PIXIS_SGMII_CMD
544#define CONFIG_FSL_SGMII_RISER 1
545#define SGMII_RISER_PHY_OFFSET 0x1c
546
547#ifdef CONFIG_FSL_SGMII_RISER
548#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
549#endif
550
Kumar Gala129ba612008-08-12 11:13:08 -0500551#define TSEC1_PHY_ADDR 0
552#define TSEC2_PHY_ADDR 1
553#define TSEC3_PHY_ADDR 2
554#define TSEC4_PHY_ADDR 3
555
556#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
557#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
558#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
559#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
560
561#define TSEC1_PHYIDX 0
562#define TSEC2_PHYIDX 0
563#define TSEC3_PHYIDX 0
564#define TSEC4_PHYIDX 0
565
566#define CONFIG_ETHPRIME "eTSEC1"
567
568#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
569#endif /* CONFIG_TSEC_ENET */
570
571/*
572 * Environment
573 */
Kumar Galacb14e932010-11-12 08:22:01 -0600574
575#if defined(CONFIG_SYS_RAMBOOT)
Kumar Galacb14e932010-11-12 08:22:01 -0600576
577#else
578 #define CONFIG_ENV_IS_IN_FLASH 1
579 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
580 #define CONFIG_ENV_ADDR 0xfff80000
581 #else
582 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
583 #endif
584 #define CONFIG_ENV_SIZE 0x2000
585 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
586#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500587
588#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200589#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala129ba612008-08-12 11:13:08 -0500590
591/*
592 * Command line configuration.
593 */
York Sun67f94472011-01-26 00:14:57 -0600594#define CONFIG_CMD_ERRATA
Kumar Gala129ba612008-08-12 11:13:08 -0500595#define CONFIG_CMD_IRQ
596#define CONFIG_CMD_PING
597#define CONFIG_CMD_I2C
598#define CONFIG_CMD_MII
Becky Bruce199e2622010-06-17 11:37:25 -0500599#define CONFIG_CMD_REGINFO
Kumar Gala129ba612008-08-12 11:13:08 -0500600
601#if defined(CONFIG_PCI)
602#define CONFIG_CMD_PCI
Kumar Gala129ba612008-08-12 11:13:08 -0500603#define CONFIG_CMD_SCSI
604#define CONFIG_CMD_EXT2
605#endif
606
Zhao Chenhui863a3ea2011-03-04 16:31:41 +0800607/*
608 * USB
609 */
610#define CONFIG_USB_EHCI
611
612#ifdef CONFIG_USB_EHCI
613#define CONFIG_CMD_USB
614#define CONFIG_USB_EHCI_PCI
615#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
616#define CONFIG_USB_STORAGE
617#define CONFIG_PCI_EHCI_DEVICE 0
618#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
619#endif
620
Kumar Gala129ba612008-08-12 11:13:08 -0500621#undef CONFIG_WATCHDOG /* watchdog disabled */
622
623/*
624 * Miscellaneous configurable options
625 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200626#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500627#define CONFIG_CMDLINE_EDITING /* Command-line editing */
628#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200629#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Gala129ba612008-08-12 11:13:08 -0500630#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200631#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500632#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200633#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500634#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200635#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
636#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
637#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Kumar Gala129ba612008-08-12 11:13:08 -0500638
639/*
640 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500641 * have to be in the first 64 MB of memory, since this is
Kumar Gala129ba612008-08-12 11:13:08 -0500642 * the maximum mapped by the Linux kernel during initialization.
643 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500644#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
645#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala129ba612008-08-12 11:13:08 -0500646
Kumar Gala129ba612008-08-12 11:13:08 -0500647#if defined(CONFIG_CMD_KGDB)
648#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Gala129ba612008-08-12 11:13:08 -0500649#endif
650
651/*
652 * Environment Configuration
653 */
Kumar Gala129ba612008-08-12 11:13:08 -0500654#if defined(CONFIG_TSEC_ENET)
655#define CONFIG_HAS_ETH0
Kumar Gala129ba612008-08-12 11:13:08 -0500656#define CONFIG_HAS_ETH1
Kumar Gala129ba612008-08-12 11:13:08 -0500657#define CONFIG_HAS_ETH2
Kumar Gala129ba612008-08-12 11:13:08 -0500658#define CONFIG_HAS_ETH3
Kumar Gala129ba612008-08-12 11:13:08 -0500659#endif
660
661#define CONFIG_IPADDR 192.168.1.254
662
663#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000664#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000665#define CONFIG_BOOTFILE "uImage"
Kumar Gala129ba612008-08-12 11:13:08 -0500666#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
667
668#define CONFIG_SERVERIP 192.168.1.1
669#define CONFIG_GATEWAYIP 192.168.1.1
670#define CONFIG_NETMASK 255.255.255.0
671
672/* default location for tftp and bootm */
673#define CONFIG_LOADADDR 1000000
674
675#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
676#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
677
678#define CONFIG_BAUDRATE 115200
679
680#define CONFIG_EXTRA_ENV_SETTINGS \
Hongtao Jia238e1462012-12-20 19:36:12 +0000681"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200682"netdev=eth0\0" \
683"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
684"tftpflash=tftpboot $loadaddr $uboot; " \
685 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
686 " +$filesize; " \
687 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
688 " +$filesize; " \
689 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
690 " $filesize; " \
691 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
692 " +$filesize; " \
693 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
694 " $filesize\0" \
695"consoledev=ttyS0\0" \
696"ramdiskaddr=2000000\0" \
697"ramdiskfile=8572ds/ramdisk.uboot\0" \
698"fdtaddr=c00000\0" \
699"fdtfile=8572ds/mpc8572ds.dtb\0" \
700"bdev=sda3\0"
Kumar Gala129ba612008-08-12 11:13:08 -0500701
702#define CONFIG_HDBOOT \
703 "setenv bootargs root=/dev/$bdev rw " \
704 "console=$consoledev,$baudrate $othbootargs;" \
705 "tftp $loadaddr $bootfile;" \
706 "tftp $fdtaddr $fdtfile;" \
707 "bootm $loadaddr - $fdtaddr"
708
709#define CONFIG_NFSBOOTCOMMAND \
710 "setenv bootargs root=/dev/nfs rw " \
711 "nfsroot=$serverip:$rootpath " \
712 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
713 "console=$consoledev,$baudrate $othbootargs;" \
714 "tftp $loadaddr $bootfile;" \
715 "tftp $fdtaddr $fdtfile;" \
716 "bootm $loadaddr - $fdtaddr"
717
718#define CONFIG_RAMBOOTCOMMAND \
719 "setenv bootargs root=/dev/ram rw " \
720 "console=$consoledev,$baudrate $othbootargs;" \
721 "tftp $ramdiskaddr $ramdiskfile;" \
722 "tftp $loadaddr $bootfile;" \
723 "tftp $fdtaddr $fdtfile;" \
724 "bootm $loadaddr $ramdiskaddr $fdtaddr"
725
726#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
727
728#endif /* __CONFIG_H */