blob: 76ddef54e647bb1a4d8bff99196baec74d534bf6 [file] [log] [blame]
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
7 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02009 */
10
11/*
12 * board/config.h - configuration options, board specific
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
22
23#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
24#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
Wolfgang Denk23c5d252014-10-24 15:31:26 +020025#define CONFIG_SYS_GENERIC_BOARD
26#define CONFIG_DISPLAY_BOARDINFO
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020027
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028#define CONFIG_SYS_TEXT_BASE 0x40000000
29
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020030#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
32#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
Jens Gehrlein22d1a562007-09-26 17:55:54 +020033#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020034 /* (it will be used if there is no */
35 /* 'cpuclk' variable with valid value) */
36
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020037#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020038#define CONFIG_SYS_SMC_RXBUFLEN 128
39#define CONFIG_SYS_MAXIDLE 10
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020040#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
41
42#define CONFIG_BOOTCOUNT_LIMIT
43
44#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
45
46#define CONFIG_BOARD_TYPES 1 /* support board types */
47
48#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010049 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020050 "echo"
51
52#undef CONFIG_BOOTARGS
53
54#define CONFIG_EXTRA_ENV_SETTINGS \
55 "netdev=eth0\0" \
56 "nfsargs=setenv bootargs root=/dev/nfs rw " \
57 "nfsroot=${serverip}:${rootpath}\0" \
58 "ramargs=setenv bootargs root=/dev/ram rw\0" \
59 "addip=setenv bootargs ${bootargs} " \
60 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
61 ":${hostname}:${netdev}:off panic=1\0" \
62 "flash_nfs=run nfsargs addip;" \
63 "bootm ${kernel_addr}\0" \
64 "flash_self=run ramargs addip;" \
65 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
66 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
67 "rootpath=/opt/eldk/ppc_8xx\0" \
Martin Krause11d9eec2007-09-26 17:55:56 +020068 "bootfile=/tftpboot/TQM885D/uImage\0" \
69 "fdt_addr=400C0000\0" \
70 "kernel_addr=40100000\0" \
71 "ramdisk_addr=40280000\0" \
72 "load=tftp 200000 ${u-boot}\0" \
73 "update=protect off 40000000 +${filesize};" \
74 "erase 40000000 +${filesize};" \
75 "cp.b 200000 40000000 ${filesize};" \
76 "protect on 40000000 +${filesize}\0" \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020077 ""
78#define CONFIG_BOOTCOMMAND "run flash_self"
79
80#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020082
83#undef CONFIG_WATCHDOG /* watchdog disabled */
84
85#define CONFIG_STATUS_LED 1 /* Status LED enabled */
86
87#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
88
89/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010090#define CONFIG_SYS_I2C
91#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
92#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
93#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020094/*
95 * Software (bit-bang) I2C driver configuration
96 */
97#define PB_SCL 0x00000020 /* PB 26 */
98#define PB_SDA 0x00000010 /* PB 27 */
99
100#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
101#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
102#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
103#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
104#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
105 else immr->im_cpm.cp_pbdat &= ~PB_SDA
106#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
107 else immr->im_cpm.cp_pbdat &= ~PB_SCL
108#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
111#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
112#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
113#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200114
115# define CONFIG_RTC_DS1337 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116# define CONFIG_SYS_I2C_RTC_ADDR 0x68
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200117
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500118/*
119 * BOOTP options
120 */
121#define CONFIG_BOOTP_SUBNETMASK
122#define CONFIG_BOOTP_GATEWAY
123#define CONFIG_BOOTP_HOSTNAME
124#define CONFIG_BOOTP_BOOTPATH
125#define CONFIG_BOOTP_BOOTFILESIZE
126
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200127
128#define CONFIG_MAC_PARTITION
129#define CONFIG_DOS_PARTITION
130
Martin Krause11d9eec2007-09-26 17:55:56 +0200131#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200132
133#define CONFIG_TIMESTAMP /* but print image timestmps */
134
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200135
Jon Loeliger26946902007-07-04 22:30:50 -0500136/*
137 * Command line configuration.
138 */
Jon Loeliger26946902007-07-04 22:30:50 -0500139#define CONFIG_CMD_ASKENV
140#define CONFIG_CMD_DATE
141#define CONFIG_CMD_DHCP
142#define CONFIG_CMD_EEPROM
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100143#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500144#define CONFIG_CMD_I2C
145#define CONFIG_CMD_IDE
146#define CONFIG_CMD_MII
Jon Loeliger26946902007-07-04 22:30:50 -0500147#define CONFIG_CMD_PING
148
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200149
150/*
151 * Miscellaneous configurable options
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_LONGHELP /* undef to save memory */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200154
Wolfgang Denk2751a952006-10-28 02:29:14 +0200155#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200157
Jon Loeliger26946902007-07-04 22:30:50 -0500158#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200160#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200162#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
164#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
165#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
168#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
169#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200170 memory test.*/
171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200173
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200174/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500175 * Enable loopw command.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200176 */
177#define CONFIG_LOOPW
178
179/*
180 * Low Level Configuration Settings
181 * (address mappings, register initial values, etc.)
182 * You should know what you are doing if you make changes here.
183 */
184/*-----------------------------------------------------------------------
185 * Internal Memory Mapped Register
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_IMMR 0xFFF00000
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200188
189/*-----------------------------------------------------------------------
190 * Definitions for initial stack pointer and data area (in DPRAM)
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200193#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200194#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200196
197/*-----------------------------------------------------------------------
198 * Start addresses for the final memory configuration
199 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_SDRAM_BASE 0x00000000
203#define CONFIG_SYS_FLASH_BASE 0x40000000
204#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
205#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
206#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200207
208/*
209 * For booting Linux, the board info and command line data
210 * have to be in the first 8 MB of memory, since this is
211 * the maximum mapped by the Linux kernel during initialization.
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200214
215/*-----------------------------------------------------------------------
216 * FLASH organization
217 */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200218
Martin Krausee318d9e2007-09-27 11:10:08 +0200219/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200221#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
223#define CONFIG_SYS_FLASH_EMPTY_INFO
224#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
225#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
226#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200227
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200228#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200229#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
230#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
231#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200232
233/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200234#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
235#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200236
237/*-----------------------------------------------------------------------
238 * Hardware Information Block
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
241#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
242#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200243
244/*-----------------------------------------------------------------------
245 * Cache Configuration
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500248#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200250#endif
251
252/*-----------------------------------------------------------------------
253 * SYPCR - System Protection Control 11-9
254 * SYPCR can only be written once after reset!
255 *-----------------------------------------------------------------------
256 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
257 */
258#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200260 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
261#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200263#endif
264
265/*-----------------------------------------------------------------------
266 * SIUMCR - SIU Module Configuration 11-6
267 *-----------------------------------------------------------------------
268 * PCMCIA config., multi-function pin tri-state
269 */
270#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200272#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200274#endif /* CONFIG_CAN_DRIVER */
275
276/*-----------------------------------------------------------------------
277 * TBSCR - Time Base Status and Control 11-26
278 *-----------------------------------------------------------------------
279 * Clear Reference Interrupt Status, Timebase freezing enabled
280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200282
283/*-----------------------------------------------------------------------
284 * PISCR - Periodic Interrupt Status and Control 11-31
285 *-----------------------------------------------------------------------
286 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200289
290/*-----------------------------------------------------------------------
291 * SCCR - System Clock and reset Control Register 15-27
292 *-----------------------------------------------------------------------
293 * Set clock output, timebase and RTC source and divider,
294 * power management and some other internal clocks
295 */
296#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200298 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
299 SCCR_DFALCD00)
300
301/*-----------------------------------------------------------------------
302 * PCMCIA stuff
303 *-----------------------------------------------------------------------
304 *
305 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
307#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
308#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
309#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
310#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
311#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
312#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
313#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200314
315/*-----------------------------------------------------------------------
316 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
317 *-----------------------------------------------------------------------
318 */
319
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000320#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200321#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
322
323#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
324#undef CONFIG_IDE_LED /* LED for ide not supported */
325#undef CONFIG_IDE_RESET /* reset for ide not supported */
326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
328#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200333
334/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200336
337/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200339
340/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200342
343/*-----------------------------------------------------------------------
344 *
345 *-----------------------------------------------------------------------
346 *
347 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_DER 0
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200349
350/*
351 * Init Memory Controller:
352 *
353 * BR0/1 and OR0/1 (FLASH)
354 */
355
356#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
357#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
358
359/* used to re-map FLASH both when starting from SRAM or FLASH:
360 * restrict access enough to keep SRAM working (if any)
361 * but not too much to meddle with FLASH accesses
362 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
364#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200365
366/*
367 * FLASH timing: Default value of OR0 after reset
368 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200370 OR_SCY_6_CLK | OR_TRLX)
371
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
373#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
374#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200375
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
377#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
378#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200379
380/*
381 * BR2/3 and OR2/3 (SDRAM)
382 *
383 */
384#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
385#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
386#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
387
388/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200390
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
392#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200393
394#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
396#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200397#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
399#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
400#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
401#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200402 BR_PS_8 | BR_MS_UPMB | BR_V )
403#endif /* CONFIG_CAN_DRIVER */
404
405/*
406 * 4096 Rows from SDRAM example configuration
407 * 1000 factor s -> ms
408 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
409 * 4 Number of refresh cycles per period
410 * 64 Refresh cycle in ms per number of rows
411 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200413
414/*
Jens Gehrlein492c7042007-09-27 14:54:46 +0200415 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
416 *
417 * CPUclock(MHz) * 31.2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
Jens Gehrlein492c7042007-09-27 14:54:46 +0200419 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
420 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
422 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
423 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
424 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
Jens Gehrlein492c7042007-09-27 14:54:46 +0200425 *
426 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
427 * be met also in the default configuration, i.e. if environment variable
428 * 'cpuclk' is not set.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200429 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_MAMR_PTA 128
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200431
432/*
Jens Gehrlein492c7042007-09-27 14:54:46 +0200433 * Memory Periodic Timer Prescaler Register (MPTPR) values.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200434 */
Jens Gehrlein492c7042007-09-27 14:54:46 +0200435/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
Jens Gehrlein492c7042007-09-27 14:54:46 +0200437/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200439
440/*
441 * MAMR settings for SDRAM
442 */
443
444/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200446 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
447 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
448/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200450 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
451 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
452/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200454 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
455 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
456
457/*
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200458 * Network configuration
459 */
460#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
461#define CONFIG_FEC_ENET /* enable ethernet on FEC */
462#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
463#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
464
Jon Loeliger26946902007-07-04 22:30:50 -0500465#if defined(CONFIG_CMD_MII)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_DISCOVER_PHY
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500467#define CONFIG_MII_INIT 1
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200468#endif
469
470#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
471 switching to another netwok (if the
472 tried network is unreachable) */
473
Heiko Schocher48690d82010-07-20 17:45:02 +0200474#define CONFIG_ETHPRIME "SCC"
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200475
Heiko Schocher7026ead2010-02-09 15:50:27 +0100476/* pass open firmware flat tree */
477#define CONFIG_OF_LIBFDT 1
478#define CONFIG_OF_BOARD_SETUP 1
479#define CONFIG_HWCONFIG 1
480
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200481#endif /* __CONFIG_H */