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Stelian Popd99a8ff2008-05-08 20:52:22 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Popd99a8ff2008-05-08 20:52:22 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9261EK board.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Stelian Popd99a8ff2008-05-08 20:52:22 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/* ARM asynchronous clock */
Xu, Hongf7aea462011-07-31 22:49:00 +000015#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Achim Ehrlich7c966a82010-02-24 10:29:16 +010016#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Stelian Popd99a8ff2008-05-08 20:52:22 +020017
Xu, Hongf7aea462011-07-31 22:49:00 +000018#ifdef CONFIG_AT91SAM9G10
19#define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020020#else
Xu, Hongf7aea462011-07-31 22:49:00 +000021#define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020022#endif
Xu, Hongf7aea462011-07-31 22:49:00 +000023
24#include <asm/hardware.h>
25
Xu, Hongf7aea462011-07-31 22:49:00 +000026#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
27#define CONFIG_SETUP_MEMORY_TAGS
28#define CONFIG_INITRD_TAG
Stelian Popd99a8ff2008-05-08 20:52:22 +020029
30#define CONFIG_SKIP_LOWLEVEL_INIT
Stelian Popd99a8ff2008-05-08 20:52:22 +020031
Xu, Hongf7aea462011-07-31 22:49:00 +000032#define CONFIG_DISPLAY_CPUINFO
33
Bo Shendc3e30b2012-09-04 23:22:55 +000034#define CONFIG_OF_LIBFDT
35
Bo Shen59158ba2014-10-22 18:01:23 +080036#define CONFIG_SYS_GENERIC_BOARD
37
Xu, Hongf7aea462011-07-31 22:49:00 +000038#define CONFIG_ATMEL_LEGACY
39#define CONFIG_SYS_TEXT_BASE 0x21f00000
40
Stelian Popd99a8ff2008-05-08 20:52:22 +020041/*
42 * Hardware drivers
43 */
Xu, Hongf7aea462011-07-31 22:49:00 +000044
45/* gpio */
46#define CONFIG_AT91_GPIO
47#define CONFIG_AT91_GPIO_PULLUP 1
48
49/* serial console */
50#define CONFIG_ATMEL_USART
51#define CONFIG_USART_BASE ATMEL_BASE_DBGU
52#define CONFIG_USART_ID ATMEL_ID_SYS
53#define CONFIG_BAUDRATE 115200
Stelian Popd99a8ff2008-05-08 20:52:22 +020054
Stelian Pop820f2a92008-05-08 14:52:30 +020055/* LCD */
Xu, Hongf7aea462011-07-31 22:49:00 +000056#define CONFIG_LCD
Stelian Pop820f2a92008-05-08 14:52:30 +020057#define LCD_BPP LCD_COLOR8
Xu, Hongf7aea462011-07-31 22:49:00 +000058#define CONFIG_LCD_LOGO
Stelian Pop820f2a92008-05-08 14:52:30 +020059#undef LCD_TEST_PATTERN
Xu, Hongf7aea462011-07-31 22:49:00 +000060#define CONFIG_LCD_INFO
61#define CONFIG_LCD_INFO_BELOW_LOGO
62#define CONFIG_SYS_WHITE_ON_BLACK
63#define CONFIG_ATMEL_LCD
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020064#ifdef CONFIG_AT91SAM9261EK
Xu, Hongf7aea462011-07-31 22:49:00 +000065#define CONFIG_ATMEL_LCD_BGR555
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020066#endif
Xu, Hongf7aea462011-07-31 22:49:00 +000067
68#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Stelian Pop820f2a92008-05-08 14:52:30 +020069
Jean-Christophe PLAGNIOL-VILLARDa484b002009-03-21 21:08:00 +010070/* LED */
71#define CONFIG_AT91_LED
72#define CONFIG_RED_LED AT91_PIN_PA23 /* this is the power led */
73#define CONFIG_GREEN_LED AT91_PIN_PA13 /* this is the user1 led */
74#define CONFIG_YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */
75
Stelian Popd99a8ff2008-05-08 20:52:22 +020076#define CONFIG_BOOTDELAY 3
77
Stelian Popd99a8ff2008-05-08 20:52:22 +020078/*
79 * BOOTP options
80 */
Xu, Hongf7aea462011-07-31 22:49:00 +000081#define CONFIG_BOOTP_BOOTFILESIZE
82#define CONFIG_BOOTP_BOOTPATH
83#define CONFIG_BOOTP_GATEWAY
84#define CONFIG_BOOTP_HOSTNAME
Stelian Popd99a8ff2008-05-08 20:52:22 +020085
86/*
87 * Command line configuration.
88 */
Xu, Hongf7aea462011-07-31 22:49:00 +000089#define CONFIG_CMD_PING
90#define CONFIG_CMD_DHCP
91#define CONFIG_CMD_NAND
92#define CONFIG_CMD_USB
Stelian Popd99a8ff2008-05-08 20:52:22 +020093
94/* SDRAM */
95#define CONFIG_NR_DRAM_BANKS 1
Xu, Hongf7aea462011-07-31 22:49:00 +000096#define CONFIG_SYS_SDRAM_BASE 0x20000000
97#define CONFIG_SYS_SDRAM_SIZE 0x04000000
98#define CONFIG_SYS_INIT_SP_ADDR \
99 (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
Stelian Popd99a8ff2008-05-08 20:52:22 +0200100
101/* DataFlash */
Jean-Christophe PLAGNIOL-VILLARD4758ebd2009-03-27 23:26:44 +0100102#define CONFIG_ATMEL_DATAFLASH_SPI
Xu, Hongf7aea462011-07-31 22:49:00 +0000103#define CONFIG_HAS_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
105#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
106#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
Xu, Hongf7aea462011-07-31 22:49:00 +0000107#define AT91_SPI_CLK 15000000
108#define DATAFLASH_TCSS (0x1a << 16)
109#define DATAFLASH_TCHS (0x1 << 24)
Stelian Popd99a8ff2008-05-08 20:52:22 +0200110
111/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100112#ifdef CONFIG_CMD_NAND
113#define CONFIG_NAND_ATMEL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_MAX_NAND_DEVICE 1
115#define CONFIG_SYS_NAND_BASE 0x40000000
Xu, Hongf7aea462011-07-31 22:49:00 +0000116#define CONFIG_SYS_NAND_DBW_8
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100117/* our ALE is AD22 */
118#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
119/* our CLE is AD21 */
120#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
121#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
122#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +0200123
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100124#endif
Stelian Popd99a8ff2008-05-08 20:52:22 +0200125
126/* NOR flash - no real flash on this board */
Xu, Hongf7aea462011-07-31 22:49:00 +0000127#define CONFIG_SYS_NO_FLASH
Stelian Popd99a8ff2008-05-08 20:52:22 +0200128
129/* Ethernet */
Xu, Hongf7aea462011-07-31 22:49:00 +0000130#define CONFIG_DRIVER_DM9000
Stelian Popd99a8ff2008-05-08 20:52:22 +0200131#define CONFIG_DM9000_BASE 0x30000000
132#define DM9000_IO CONFIG_DM9000_BASE
133#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
Xu, Hongf7aea462011-07-31 22:49:00 +0000134#define CONFIG_DM9000_USE_16BIT
135#define CONFIG_DM9000_NO_SROM
Stelian Popd99a8ff2008-05-08 20:52:22 +0200136#define CONFIG_NET_RETRY_COUNT 20
Xu, Hongf7aea462011-07-31 22:49:00 +0000137#define CONFIG_RESET_PHY_R
Stelian Popd99a8ff2008-05-08 20:52:22 +0200138
139/* USB */
Jean-Christophe PLAGNIOL-VILLARD2b7178a2009-03-27 23:26:44 +0100140#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800141#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Xu, Hongf7aea462011-07-31 22:49:00 +0000142#define CONFIG_USB_OHCI_NEW
143#define CONFIG_DOS_PARTITION
144#define CONFIG_SYS_USB_OHCI_CPU_INIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +0200146#ifdef CONFIG_AT91SAM9G10EK
147#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10"
148#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +0200150#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Xu, Hongf7aea462011-07-31 22:49:00 +0000152#define CONFIG_USB_STORAGE
153#define CONFIG_CMD_FAT
Stelian Popd99a8ff2008-05-08 20:52:22 +0200154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Popd99a8ff2008-05-08 20:52:22 +0200156
Xu, Hongf7aea462011-07-31 22:49:00 +0000157#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Popd99a8ff2008-05-08 20:52:22 +0200159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
Stelian Popd99a8ff2008-05-08 20:52:22 +0200161
162/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Xu, Hongf7aea462011-07-31 22:49:00 +0000163#define CONFIG_ENV_IS_IN_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100165#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200167#define CONFIG_ENV_SIZE 0x4200
Alexandre Bellonie139cb32012-07-02 04:26:58 +0000168#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
Stelian Popd99a8ff2008-05-08 20:52:22 +0200169#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
170 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200171 "mtdparts=atmel_nand:-(root) " \
Stelian Popd99a8ff2008-05-08 20:52:22 +0200172 "rw rootfstype=jffs2"
173
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100174#elif CONFIG_SYS_USE_DATAFLASH_CS3
175
176/* bootstrap + u-boot + env + linux in dataflash on CS3 */
Xu, Hongf7aea462011-07-31 22:49:00 +0000177#define CONFIG_ENV_IS_IN_DATAFLASH
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100178#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
179#define CONFIG_ENV_OFFSET 0x4200
180#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
181#define CONFIG_ENV_SIZE 0x4200
Alexandre Bellonie139cb32012-07-02 04:26:58 +0000182#define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm"
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100183#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
184 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200185 "mtdparts=atmel_nand:-(root) " \
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100186 "rw rootfstype=jffs2"
187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#else /* CONFIG_SYS_USE_NANDFLASH */
Stelian Popd99a8ff2008-05-08 20:52:22 +0200189
190/* bootstrap + u-boot + env + linux in nandflash */
Xu, Hongf7aea462011-07-31 22:49:00 +0000191#define CONFIG_ENV_IS_IN_NAND
Bo Shen0c58cfa2013-02-20 00:16:25 +0000192#define CONFIG_ENV_OFFSET 0xc0000
193#define CONFIG_ENV_OFFSET_REDUND 0x100000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200194#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Bo Shen0c58cfa2013-02-20 00:16:25 +0000195#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
196#define CONFIG_BOOTARGS \
197 "console=ttyS0,115200 earlyprintk " \
198 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
199 "256k(env),256k(env_redundant),256k(spare)," \
200 "512k(dtb),6M(kernel)ro,-(rootfs) " \
201 "root=/dev/mtdblock7 rw rootfstype=jffs2"
Stelian Popd99a8ff2008-05-08 20:52:22 +0200202#endif
203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_CBSIZE 256
205#define CONFIG_SYS_MAXARGS 16
Xu, Hongf7aea462011-07-31 22:49:00 +0000206#define CONFIG_SYS_LONGHELP
207#define CONFIG_CMDLINE_EDITING
Alexandre Bellonie139cb32012-07-02 04:26:58 +0000208#define CONFIG_AUTO_COMPLETE
Stelian Popd99a8ff2008-05-08 20:52:22 +0200209
Stelian Popd99a8ff2008-05-08 20:52:22 +0200210/*
211 * Size of malloc() pool
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Popd99a8ff2008-05-08 20:52:22 +0200214
Stelian Popd99a8ff2008-05-08 20:52:22 +0200215#endif