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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
wdenkc6097192002-11-03 00:24:07 +000038#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
39
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
41
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050043#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
wdenkc6097192002-11-03 00:24:07 +000044
wdenkc837dcb2004-01-20 23:12:12 +000045#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000046
47#define CONFIG_BAUDRATE 9600
48#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
49
wdenkc6097192002-11-03 00:24:07 +000050#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000051#undef CONFIG_BOOTCOMMAND
52
53#define CONFIG_PREBOOT /* enable preboot variable */
wdenkc6097192002-11-03 00:24:07 +000054
55#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +000057
Ben Warren96e21f82008-10-27 23:50:15 -070058#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +000059#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000060#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000061#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020062#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
63
Matthias Fuchs6f35c532007-06-24 17:41:21 +020064#undef CONFIG_HAS_ETH1
wdenkc6097192002-11-03 00:24:07 +000065
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050066/*
67 * BOOTP options
68 */
69#define CONFIG_BOOTP_SUBNETMASK
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72#define CONFIG_BOOTP_BOOTPATH
73#define CONFIG_BOOTP_DNS
74#define CONFIG_BOOTP_DNS2
75#define CONFIG_BOOTP_SEND_HOSTNAME
stroese9919f132003-05-23 11:38:22 +000076
wdenkc6097192002-11-03 00:24:07 +000077
Jon Loeliger49cf7e82007-07-05 19:52:35 -050078/*
79 * Command line configuration.
80 */
81#include <config_cmd_default.h>
82
83#define CONFIG_CMD_DHCP
84#define CONFIG_CMD_PCI
85#define CONFIG_CMD_IRQ
86#define CONFIG_CMD_IDE
87#define CONFIG_CMD_FAT
88#define CONFIG_CMD_ELF
89#define CONFIG_CMD_MII
90#define CONFIG_CMD_EEPROM
91
wdenkc6097192002-11-03 00:24:07 +000092
93#define CONFIG_MAC_PARTITION
94#define CONFIG_DOS_PARTITION
95
stroesea20b27a2004-12-16 18:05:42 +000096#define CONFIG_SUPPORT_VFAT
97
wdenkc837dcb2004-01-20 23:12:12 +000098#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +000099
wdenkc837dcb2004-01-20 23:12:12 +0000100#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +0000101
102/*
103 * Miscellaneous configurable options
104 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_LONGHELP /* undef to save memory */
106#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkc6097192002-11-03 00:24:07 +0000107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
wdenkc6097192002-11-03 00:24:07 +0000109
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500110#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000112#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000114#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
116#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
117#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
wdenkc6097192002-11-03 00:24:07 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
124#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000125
Stefan Roese550650d2010-09-20 16:05:31 +0200126#define CONFIG_CONS_INDEX 1 /* Use UART0 */
127#define CONFIG_SYS_NS16550
128#define CONFIG_SYS_NS16550_SERIAL
129#define CONFIG_SYS_NS16550_REG_SIZE 1
130#define CONFIG_SYS_NS16550_CLK get_serial_clock()
131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000134
135/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000137 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
138 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
141#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000144
stroesea20b27a2004-12-16 18:05:42 +0000145#define CONFIG_LOOPW 1 /* enable loopw command */
146
wdenkc6097192002-11-03 00:24:07 +0000147#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
148
149/*-----------------------------------------------------------------------
150 * PCI stuff
151 *-----------------------------------------------------------------------
152 */
stroesea20b27a2004-12-16 18:05:42 +0000153#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
154#define PCI_HOST_FORCE 1 /* configure as pci host */
155#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000156
stroesea20b27a2004-12-16 18:05:42 +0000157#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000158#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
stroesea20b27a2004-12-16 18:05:42 +0000159#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
160#define CONFIG_PCI_PNP /* do pci plug-and-play */
161 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000162
stroesea20b27a2004-12-16 18:05:42 +0000163#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000164
stroesea20b27a2004-12-16 18:05:42 +0000165#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
stroesead10dd92003-02-14 11:21:23 +0000166
stroesea20b27a2004-12-16 18:05:42 +0000167#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
170#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
171#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
172#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
173#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
174#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
175#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
176#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
177#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
Matthias Fuchs468ebf12012-11-02 14:30:34 +0100178#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000179
Matthias Fuchs82379b52009-09-07 17:00:41 +0200180#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
181
wdenkc6097192002-11-03 00:24:07 +0000182/*-----------------------------------------------------------------------
183 * IDE/ATA stuff
184 *-----------------------------------------------------------------------
185 */
wdenkc837dcb2004-01-20 23:12:12 +0000186#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
187#undef CONFIG_IDE_LED /* no led for ide supported */
188#undef CONFIG_IDE_RESET /* no reset for ide supported */
wdenkc6097192002-11-03 00:24:07 +0000189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
191#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
194#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
197#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
198#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
wdenkc6097192002-11-03 00:24:07 +0000199
200/*-----------------------------------------------------------------------
201 * Start addresses for the final memory configuration
202 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_SDRAM_BASE 0x00000000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200206#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
207#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
208#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000210
211/*
212 * For booting Linux, the board info and command line data
213 * have to be in the first 8 MB of memory, since this is
214 * the maximum mapped by the Linux kernel during initialization.
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000217/*-----------------------------------------------------------------------
218 * FLASH organization
219 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
221#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
224#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
227#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
228#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000229/*
230 * The following defines are added for buggy IOP480 byte interface.
231 * All other boards should use the standard values (CPCI405 etc.)
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
234#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
235#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
240#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
241#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
stroesea20b27a2004-12-16 18:05:42 +0000242
wdenkc6097192002-11-03 00:24:07 +0000243#if 1 /* Use NVRAM for environment variables */
244/*-----------------------------------------------------------------------
245 * NVRAM organization
246 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200247#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200248#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
249#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
wdenkc6097192002-11-03 00:24:07 +0000251
252#else /* Use EEPROM for environment variables */
253
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200254#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200255#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
256#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
wdenk8bde7f72003-06-27 21:31:46 +0000257 /* total size of a CAT24WC08 is 1024 bytes */
wdenkc6097192002-11-03 00:24:07 +0000258#endif
259
260/*-----------------------------------------------------------------------
261 * I2C EEPROM (CAT24WC08) for environment
262 */
263#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200264#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
266#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc6097192002-11-03 00:24:07 +0000267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
269#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000270/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
272#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenkc6097192002-11-03 00:24:07 +0000273 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000274 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000276
wdenkc6097192002-11-03 00:24:07 +0000277/*
278 * Init Memory Controller:
279 *
280 * BR0/1 and OR0/1 (FLASH)
281 */
282
283#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
284#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
285
286/*-----------------------------------------------------------------------
287 * External Bus Controller (EBC) Setup
288 */
289
wdenkc837dcb2004-01-20 23:12:12 +0000290/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_EBC_PB0AP 0x92015480
292#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000293
wdenkc837dcb2004-01-20 23:12:12 +0000294/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_EBC_PB1AP 0x92015480
296#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000297
wdenkc837dcb2004-01-20 23:12:12 +0000298/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
300#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000301
wdenkc837dcb2004-01-20 23:12:12 +0000302/* Memory Bank 3 (CompactFlash IDE) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
304#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000305
wdenkc837dcb2004-01-20 23:12:12 +0000306/* Memory Bank 4 (NVRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
308#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000309
wdenkc837dcb2004-01-20 23:12:12 +0000310/* Memory Bank 5 (Quart) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
312#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000313
314/*-----------------------------------------------------------------------
315 * FPGA stuff
316 */
317
318/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
320#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
321#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
322#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
323#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
wdenkc6097192002-11-03 00:24:07 +0000324
325/*-----------------------------------------------------------------------
326 * Definitions for initial stack pointer and data area (in data cache)
327 */
328#if 1 /* test-only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
wdenkc6097192002-11-03 00:24:07 +0000330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
wdenkc6097192002-11-03 00:24:07 +0000332#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
wdenkc6097192002-11-03 00:24:07 +0000334#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200335#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200336#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000338
wdenkc6097192002-11-03 00:24:07 +0000339#endif /* __CONFIG_H */