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wdenk3a473b22004-01-03 00:43:19 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk3a473b22004-01-03 00:43:19 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
wdenk3a473b22004-01-03 00:43:19 +000015/* This define must be before the core.h include */
16#define CONFIG_DB64460 1 /* this is an DB64460 board */
17
18#ifndef __ASSEMBLY__
19#include "../board/Marvell/include/core.h"
20#endif
21
22/*-----------------------------------------------------*/
23/* #include "../board/db64460/local.h" */
24#ifndef __LOCAL_H
25#define __LOCAL_H
26
27#define CONFIG_ETHADDR 64:46:00:00:00:01
wdenke2ffd592004-12-31 09:32:47 +000028#define CONFIG_HAS_ETH1
wdenk3a473b22004-01-03 00:43:19 +000029#define CONFIG_ETH1ADDR 64:46:00:00:00:02
wdenke2ffd592004-12-31 09:32:47 +000030#define CONFIG_HAS_ETH2
wdenk3a473b22004-01-03 00:43:19 +000031#define CONFIG_ETH2ADDR 64:46:00:00:00:03
32
33#define CONFIG_ENV_OVERWRITE
34#endif /* __CONFIG_H */
35
36/*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40
41#define CONFIG_74xx /* we have a 750FX (override local.h) */
42
43#define CONFIG_DB64460 1 /* this is an DB64460 board */
44
Wolfgang Denk2ae18242010-10-06 09:05:45 +020045#define CONFIG_SYS_TEXT_BASE 0xfff00000
46
wdenk3a473b22004-01-03 00:43:19 +000047#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
48/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
49 DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
50 so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
51 see sdram_init.c */
52#undef CONFIG_ECC /* enable ECC support */
53#define CONFIG_MV64460_ECC
54
55/* which initialization functions to call for this board */
56#define CONFIG_MISC_INIT_R /* initialize the icache L1 */
wdenkc837dcb2004-01-20 23:12:12 +000057#define CONFIG_BOARD_EARLY_INIT_F
wdenk3a473b22004-01-03 00:43:19 +000058
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_BOARD_NAME "DB64460"
wdenk3a473b22004-01-03 00:43:19 +000060#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)"
61
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062/*#define CONFIG_SYS_HUSH_PARSER */
63#undef CONFIG_SYS_HUSH_PARSER
wdenk3a473b22004-01-03 00:43:19 +000064
wdenk3a473b22004-01-03 00:43:19 +000065
66/*
67 * The following defines let you select what serial you want to use
68 * for your console driver.
69 *
70 * what to do:
71 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
wdenk3a473b22004-01-03 00:43:19 +000073 * to 0 below.
74 *
75 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
76 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
77 */
78
79#define CONFIG_MPSC_PORT 0
80
81/* to change the default ethernet port, use this define (options: 0, 1, 2) */
wdenk3a473b22004-01-03 00:43:19 +000082#define MV_ETH_DEVS 3
83
84/* #undef CONFIG_ETHER_PORT_MII */
85#if 0
86#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
87#else
88#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
89#endif
90#define CONFIG_ZERO_BOOTDELAY_CHECK
91
92
93#undef CONFIG_BOOTARGS
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010094/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
wdenk3a473b22004-01-03 00:43:19 +000095
96/* ronen - autoboot using tftp */
97#if (CONFIG_BOOTDELAY >= 0)
98#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
Wolfgang Denkfe126d82005-11-20 21:40:11 +010099 setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
100 ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; "
wdenk3a473b22004-01-03 00:43:19 +0000101
102#define CONFIG_BOOTARGS "console=ttyS0,115200"
103
104#endif
105
106/* ronen - the u-boot.bin should be ~0x30000 bytes */
107#define CONFIG_EXTRA_ENV_SETTINGS \
108 "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
109cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
110 "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
111cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
112 "bootargs_root=root=/dev/nfs rw\0" \
113 "bootargs_end=:::DB64460:eth0:none \0"\
114 "ethprime=mv_enet0\0"\
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100115 "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
116ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
wdenk3a473b22004-01-03 00:43:19 +0000117
118/* --------------------------------------------------------------------------------------------------------------- */
119/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
120
121#define CONFIG_IPADDR 10.2.40.90
122
123#define CONFIG_SERIAL "No. 1"
124#define CONFIG_SERVERIP 10.2.1.126
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000125#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini"
wdenk3a473b22004-01-03 00:43:19 +0000126
127
128#define CONFIG_TESTDRAMDATA y
129#define CONFIG_TESTDRAMADDRESS n
130#define CONFIG_TESETDRAMWALK n
131
132/* --------------------------------------------------------------------------------------------------------------- */
133
134#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
wdenk3a473b22004-01-03 00:43:19 +0000136
137#undef CONFIG_WATCHDOG /* watchdog disabled */
138#undef CONFIG_ALTIVEC /* undef to disable */
139
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500140/*
141 * BOOTP options
142 */
143#define CONFIG_BOOTP_SUBNETMASK
144#define CONFIG_BOOTP_GATEWAY
145#define CONFIG_BOOTP_HOSTNAME
146#define CONFIG_BOOTP_BOOTPATH
147#define CONFIG_BOOTP_BOOTFILESIZE
148
149
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200150/*
151 * JFFS2 partitions
152 *
153 */
154/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100155#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200156#define CONFIG_JFFS2_DEV "nor1"
157#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
158#define CONFIG_JFFS2_PART_OFFSET 0x00000000
wdenk3a473b22004-01-03 00:43:19 +0000159
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200160/* mtdparts command line support */
161
162/* Use first bank for JFFS2, second bank contains U-Boot.
163 *
164 * Note: fake mtd_id's used, no linux mtd map file.
165 */
166/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100167#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200168#define MTDIDS_DEFAULT "nor1=db64460-1"
169#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)"
170*/
wdenk3a473b22004-01-03 00:43:19 +0000171
wdenk3a473b22004-01-03 00:43:19 +0000172
Jon Loeliger3c3227f2007-07-07 20:40:43 -0500173/*
174 * Command line configuration.
175 */
176#include <config_cmd_default.h>
177
178#define CONFIG_CMD_ASKENV
179#define CONFIG_CMD_I2C
180#define CONFIG_CMD_EEPROM
181#define CONFIG_CMD_CACHE
182#define CONFIG_CMD_JFFS2
183#define CONFIG_CMD_PCI
184#define CONFIG_CMD_NET
185
wdenk3a473b22004-01-03 00:43:19 +0000186
187/*
188 * Miscellaneous configurable options
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
191#define CONFIG_SYS_I2C_MULTI_EEPROMS
192#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */
wdenk3a473b22004-01-03 00:43:19 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */
195#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger3c3227f2007-07-07 20:40:43 -0500196#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk3a473b22004-01-03 00:43:19 +0000198#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk3a473b22004-01-03 00:43:19 +0000200#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
202#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
203#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk3a473b22004-01-03 00:43:19 +0000204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */
206/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
207/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
wdenk3a473b22004-01-03 00:43:19 +0000208
209/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_DRAM_TEST
wdenk3a473b22004-01-03 00:43:19 +0000211 * DRAM tests
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 * CONFIG_SYS_DRAM_TEST - enables the following tests.
wdenk3a473b22004-01-03 00:43:19 +0000213 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214 * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
wdenk3a473b22004-01-03 00:43:19 +0000215 * Environment variable 'test_dram_data' must be
216 * set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217 * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
wdenk3a473b22004-01-03 00:43:19 +0000218 * addressable. Environment variable
219 * 'test_dram_address' must be set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220 * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
wdenk3a473b22004-01-03 00:43:19 +0000221 * This test takes about 6 minutes to test 64 MB.
222 * Environment variable 'test_dram_walk' must be
223 * set to 'y'.
224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_DRAM_TEST
226#if defined(CONFIG_SYS_DRAM_TEST)
227#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
228/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
229#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
230#define CONFIG_SYS_DRAM_TEST_DATA
231#define CONFIG_SYS_DRAM_TEST_ADDRESS
232#define CONFIG_SYS_DRAM_TEST_WALK
233#endif /* CONFIG_SYS_DRAM_TEST */
wdenk3a473b22004-01-03 00:43:19 +0000234
235#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
wdenk3a473b22004-01-03 00:43:19 +0000237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */
wdenk3a473b22004-01-03 00:43:19 +0000239
wdenk3a473b22004-01-03 00:43:19 +0000240/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200241#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
wdenk3a473b22004-01-03 00:43:19 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
244#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
wdenk3a473b22004-01-03 00:43:19 +0000245
246/*ronen - this is the Tclk (MV64460 core) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_TCLK 133000000
wdenk3a473b22004-01-03 00:43:19 +0000248
249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk3a473b22004-01-03 00:43:19 +0000251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_750FX_HID0 0x8000c084
253#define CONFIG_SYS_750FX_HID1 0x54800000
254#define CONFIG_SYS_750FX_HID2 0x00000000
wdenk3a473b22004-01-03 00:43:19 +0000255
256/*
257 * Low Level Configuration Settings
258 * (address mappings, register initial values, etc.)
259 * You should know what you are doing if you make changes here.
260 */
261
262/*-----------------------------------------------------------------------
263 * Definitions for initial stack pointer and data area
264 */
265
266/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
wdenk3a473b22004-01-03 00:43:19 +0000268 * To an unused memory region. The stack will remain in cache until RAM
269 * is initialized
270*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_INIT_RAM_LOCK
272#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200273#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200274#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk3a473b22004-01-03 00:43:19 +0000275
276#define RELOCATE_INTERNAL_RAM_ADDR
277#ifdef RELOCATE_INTERNAL_RAM_ADDR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278 #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000
wdenk3a473b22004-01-03 00:43:19 +0000279#endif
280
281/*-----------------------------------------------------------------------
282 * Start addresses for the final memory configuration
283 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk3a473b22004-01-03 00:43:19 +0000285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenk3a473b22004-01-03 00:43:19 +0000287/* Dummies for BAT 4-7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
289#define CONFIG_SYS_SDRAM2_BASE 0x20000000
290#define CONFIG_SYS_SDRAM3_BASE 0x30000000
291#define CONFIG_SYS_SDRAM4_BASE 0x40000000
292#define CONFIG_SYS_FLASH_BASE 0xfff00000
wdenk3a473b22004-01-03 00:43:19 +0000293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000
wdenk3a473b22004-01-03 00:43:19 +0000295#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
296
297#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
298#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
299#define PCI0_IO_BASE_BOOTM 0xfd000000
300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
302#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
303#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
304#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
wdenk3a473b22004-01-03 00:43:19 +0000305
306/* areas to map different things with the GT in physical space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_DRAM_BANKS 4
wdenk3a473b22004-01-03 00:43:19 +0000308
309/* What to put in the bats. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
wdenk3a473b22004-01-03 00:43:19 +0000311
312/* Peripheral Device section */
313
314/*******************************************************/
315/* We have on the db64460 Board : */
316/* GT-Chipset Register Area */
317/* GT-Chipset internal SRAM 256k */
318/* SRAM on external device module */
319/* Real time clock on external device module */
320/* dobble UART on external device module */
321/* Data flash on external device module */
322/* Boot flash on external device module */
323/*******************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
325#define CONFIG_SYS_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */
wdenk3a473b22004-01-03 00:43:19 +0000326
327/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
329#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */
wdenk3a473b22004-01-03 00:43:19 +0000330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */
332#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
333#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
334#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */
wdenk3a473b22004-01-03 00:43:19 +0000335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */
337#define CONFIG_SYS_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */
338#define CONFIG_SYS_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */
339#define CONFIG_SYS_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */
wdenk3a473b22004-01-03 00:43:19 +0000340/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
341
342/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
344#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
345#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
346#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
347#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
wdenk3a473b22004-01-03 00:43:19 +0000348
349 /* c 4 a 8 2 4 1 c */
350 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
351 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
352 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
353 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
354
355
356/* ronen - update MPP Control MV64460*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_MPP_CONTROL_0 0x02222222
358#define CONFIG_SYS_MPP_CONTROL_1 0x11333011
359#define CONFIG_SYS_MPP_CONTROL_2 0x40431111
360#define CONFIG_SYS_MPP_CONTROL_3 0x00000044
wdenk3a473b22004-01-03 00:43:19 +0000361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
wdenk3a473b22004-01-03 00:43:19 +0000363
364
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
wdenk3a473b22004-01-03 00:43:19 +0000366 /* gpp[31] gpp[30] gpp[29] gpp[28] */
367 /* gpp[27] gpp[24]*/
368 /* gpp[19:14] */
369
370/* setup new config_value for MV64460 DDR-RAM !! */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
wdenk3a473b22004-01-03 00:43:19 +0000372
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
374#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
375#define CONFIG_SYS_INIT_CHAN1
376#define CONFIG_SYS_INIT_CHAN2
wdenk3a473b22004-01-03 00:43:19 +0000377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define SRAM_BASE CONFIG_SYS_DEV0_SPACE
wdenk3a473b22004-01-03 00:43:19 +0000379#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
380
381
382/*-----------------------------------------------------------------------
383 * PCI stuff
384 *-----------------------------------------------------------------------
385 */
386
387#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
388#define PCI_HOST_FORCE 1 /* configure as pci host */
389#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
390
391#define CONFIG_PCI /* include pci support */
392#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
393#define CONFIG_PCI_PNP /* do pci plug-and-play */
394#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
395
396/* PCI MEMORY MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
398#define CONFIG_SYS_PCI0_MEM_SIZE _128M
399#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
400#define CONFIG_SYS_PCI1_MEM_SIZE _128M
wdenk3a473b22004-01-03 00:43:19 +0000401
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
403#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
wdenk3a473b22004-01-03 00:43:19 +0000404
405/* PCI I/O MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
407#define CONFIG_SYS_PCI0_IO_SIZE _16M
408#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
409#define CONFIG_SYS_PCI1_IO_SIZE _16M
wdenk3a473b22004-01-03 00:43:19 +0000410
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
412#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
413#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
414#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
wdenk3a473b22004-01-03 00:43:19 +0000415
416#if defined (CONFIG_750CX)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_PCI_IDSEL 0x0
wdenk3a473b22004-01-03 00:43:19 +0000418#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_PCI_IDSEL 0x30
wdenk3a473b22004-01-03 00:43:19 +0000420#endif
421/*----------------------------------------------------------------------
422 * Initial BAT mappings
423 */
424
425/* NOTES:
426 * 1) GUARDED and WRITE_THRU not allowed in IBATS
427 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
428 */
429
430/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
432#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
433#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
434#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
wdenk3a473b22004-01-03 00:43:19 +0000435
436/* init ram */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
438#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
439#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
440#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
wdenk3a473b22004-01-03 00:43:19 +0000441
442/* PCI0, PCI1 in one BAT */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
444#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
445#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
446#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk3a473b22004-01-03 00:43:19 +0000447
448/* GT regs, bootrom, all the devices, PCI I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
450#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
451#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
452#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenk3a473b22004-01-03 00:43:19 +0000453
454/* I2C addresses for the two DIMM SPD chips */
455#define DIMM0_I2C_ADDR 0x56
456#define DIMM1_I2C_ADDR 0x54
457
458/*
459 * For booting Linux, the board info and command line data
460 * have to be in the first 8 MB of memory, since this is
461 * the maximum mapped by the Linux kernel during initialization.
462 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
wdenk3a473b22004-01-03 00:43:19 +0000464
465/*-----------------------------------------------------------------------
466 * FLASH organization
467 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
469#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
wdenk3a473b22004-01-03 00:43:19 +0000470
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
472#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */
473#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */
wdenk3a473b22004-01-03 00:43:19 +0000474
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
476#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
477#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
478#define CONFIG_SYS_FLASH_CFI 1
wdenk3a473b22004-01-03 00:43:19 +0000479
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200480#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200481#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
482#define CONFIG_ENV_SECT_SIZE 0x10000
483#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
wdenk3a473b22004-01-03 00:43:19 +0000485
486/*-----------------------------------------------------------------------
487 * Cache Configuration
488 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeliger3c3227f2007-07-07 20:40:43 -0500490#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk3a473b22004-01-03 00:43:19 +0000492#endif
493
494/*-----------------------------------------------------------------------
495 * L2CR setup -- make sure this is right for your board!
496 * look in include/mpc74xx.h for the defines used here
497 */
498
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_L2
wdenk3a473b22004-01-03 00:43:19 +0000500
501
502#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
503#define L2_INIT 0
504#else
505
506#define L2_INIT 0
507/*
508#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
509 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
510*/
511#endif
512
513#define L2_ENABLE (L2_INIT | L2CR_L2E)
514
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_BOARD_ASM_INIT 1
wdenk3a473b22004-01-03 00:43:19 +0000516
517#endif /* __CONFIG_H */