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Jon Loeliger9553df82007-10-16 15:26:51 -05001/*
Timur Tabiba8e76b2011-04-11 14:18:22 -05002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Jon Loeliger9553df82007-10-16 15:26:51 -05003 *
Tom Rini5b8031c2016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Jon Loeliger9553df82007-10-16 15:26:51 -05005 */
6
7/*
8 * MPC8610HPCD board configuration file
Jon Loeliger9553df82007-10-16 15:26:51 -05009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
York Sun9ae14ca2015-08-18 12:35:52 -070014#define CONFIG_DISPLAY_BOARDINFO
15
Jon Loeliger9553df82007-10-16 15:26:51 -050016/* High Level Configuration Options */
Jon Loeliger9553df82007-10-16 15:26:51 -050017#define CONFIG_MPC8610 1 /* MPC8610 specific */
18#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
Jon Loeliger9553df82007-10-16 15:26:51 -050019#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
20
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021#define CONFIG_SYS_TEXT_BASE 0xfff00000
22
York Sun070ba562007-10-31 14:59:04 -050023
24/* video */
Timur Tabiba8e76b2011-04-11 14:18:22 -050025#define CONFIG_FSL_DIU_FB
26
Timur Tabi7d3053f2011-02-15 17:09:19 -060027#ifdef CONFIG_FSL_DIU_FB
28#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
29#define CONFIG_VIDEO
Timur Tabie69e5202010-08-31 19:56:43 -050030#define CONFIG_CMD_BMP
York Sun070ba562007-10-31 14:59:04 -050031#define CONFIG_CFB_CONSOLE
Timur Tabi7d3053f2011-02-15 17:09:19 -060032#define CONFIG_VIDEO_SW_CURSOR
York Sun070ba562007-10-31 14:59:04 -050033#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabie69e5202010-08-31 19:56:43 -050034#define CONFIG_VIDEO_LOGO
35#define CONFIG_VIDEO_BMP_LOGO
York Sun070ba562007-10-31 14:59:04 -050036#endif
37
Jon Loeliger9553df82007-10-16 15:26:51 -050038#ifdef RUN_DIAG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_DIAG_ADDR 0xff800000
Jon Loeliger9553df82007-10-16 15:26:51 -050040#endif
41
Becky Bruce1266df82008-11-03 15:44:01 -060042/*
43 * virtual address to be used for temporary mappings. There
44 * should be 128k free at this VA.
45 */
46#define CONFIG_SYS_SCRATCH_VA 0xc0000000
47
Jon Loeliger9553df82007-10-16 15:26:51 -050048#define CONFIG_PCI 1 /* Enable PCI/PCIE*/
49#define CONFIG_PCI1 1 /* PCI controler 1 */
50#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
51#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
52#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000053#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala8ba93f62008-10-21 18:06:15 -050054#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Becky Bruce031976f2008-01-23 16:31:02 -060055#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Jon Loeliger9553df82007-10-16 15:26:51 -050056
57#define CONFIG_ENV_OVERWRITE
Jon Loeliger9553df82007-10-16 15:26:51 -050058#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
59
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050060#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce31d82672008-05-08 19:02:12 -050061#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
Jon Loeliger9553df82007-10-16 15:26:51 -050062#define CONFIG_ALTIVEC 1
63
64/*
65 * L2CR setup -- make sure this is right for your board!
66 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_L2
Jon Loeliger9553df82007-10-16 15:26:51 -050068#define L2_INIT 0
York Suna8778802007-10-29 13:58:39 -050069#define L2_ENABLE (L2CR_L2E |0x00100000 )
Jon Loeliger9553df82007-10-16 15:26:51 -050070
71#ifndef CONFIG_SYS_CLK_FREQ
72#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
73#endif
74
75#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
York Suna8778802007-10-29 13:58:39 -050076#define CONFIG_MISC_INIT_R 1
Jon Loeliger9553df82007-10-16 15:26:51 -050077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
79#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeliger9553df82007-10-16 15:26:51 -050080
81/*
82 * Base addresses -- Note these are effective addresses where the
83 * actual resources get mapped (not physical addresses)
84 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
86#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
87#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeliger9553df82007-10-16 15:26:51 -050088
Jon Loeligerf6987382008-11-20 14:02:56 -060089#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
90#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
Kumar Galaad19e7a2009-08-05 07:59:35 -050091#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
Jon Loeligerf6987382008-11-20 14:02:56 -060092
Jon Loeliger39aa1a72008-08-26 15:01:36 -050093/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070094#define CONFIG_SYS_FSL_DDR2
Jon Loeliger39aa1a72008-08-26 15:01:36 -050095#undef CONFIG_FSL_DDR_INTERACTIVE
96#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
97#define CONFIG_DDR_SPD
98
99#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
100#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Becky Bruce1266df82008-11-03 15:44:01 -0600104#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500105#define CONFIG_VERY_BIG_RAM
106
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500107#define CONFIG_NUM_DDR_CONTROLLERS 1
108#define CONFIG_DIMM_SLOTS_PER_CTLR 1
109#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeliger9553df82007-10-16 15:26:51 -0500110
Kumar Galac39f44d2011-01-31 22:18:47 -0600111#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500112
113/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Jon Loeliger9553df82007-10-16 15:26:51 -0500115
116#if 0 /* TODO */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
118#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
119#define CONFIG_SYS_DDR_TIMING_3 0x00000000
120#define CONFIG_SYS_DDR_TIMING_0 0x00260802
121#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
122#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
123#define CONFIG_SYS_DDR_MODE_1 0x00480432
124#define CONFIG_SYS_DDR_MODE_2 0x00000000
125#define CONFIG_SYS_DDR_INTERVAL 0x06180100
126#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
127#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
128#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
129#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
130#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
131#define CONFIG_SYS_DDR_CONTROL2 0x04400010
Jon Loeliger9553df82007-10-16 15:26:51 -0500132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
134#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
135#define CONFIG_SYS_DDR_SBE 0x000f0000
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500136
Jon Loeliger9553df82007-10-16 15:26:51 -0500137#endif
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500138
Jon Loeliger9553df82007-10-16 15:26:51 -0500139
Jon Loeligerad8f8682008-01-15 13:42:41 -0600140#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_I2C_EEPROM_NXID
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200142#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
144#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500145
146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
148#define CONFIG_SYS_FLASH_BASE2 0xf8000000
Jon Loeliger9553df82007-10-16 15:26:51 -0500149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
Jon Loeliger9553df82007-10-16 15:26:51 -0500151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
153#define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
156#define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
Jon Loeliger9553df82007-10-16 15:26:51 -0500157#if 0 /* TODO */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_BR2_PRELIM 0xf0000000
159#define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
Jon Loeliger9553df82007-10-16 15:26:51 -0500160#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
162#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500163
164
Jason Jin761421c2007-10-29 19:26:21 +0800165#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Jon Loeliger9553df82007-10-16 15:26:51 -0500166#define PIXIS_BASE 0xe8000000 /* PIXIS registers */
167#define PIXIS_ID 0x0 /* Board ID at offset 0 */
168#define PIXIS_VER 0x1 /* Board version at offset 1 */
169#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
170#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
171#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
172#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
York Suna8778802007-10-29 13:58:39 -0500173#define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500174#define PIXIS_VCTL 0x10 /* VELA Control Register */
175#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
176#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
177#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
178#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
179#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
180#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
181#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Timur Tabi2feb4af2010-03-31 17:44:13 -0500182#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
Jon Loeliger9553df82007-10-16 15:26:51 -0500183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
185#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Jon Loeliger9553df82007-10-16 15:26:51 -0500186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#undef CONFIG_SYS_FLASH_CHECKSUM
188#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
189#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200190#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600191#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
Jon Loeliger9553df82007-10-16 15:26:51 -0500192
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200193#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_CFI
195#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeliger9553df82007-10-16 15:26:51 -0500196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
198#define CONFIG_SYS_RAMBOOT
Jon Loeliger9553df82007-10-16 15:26:51 -0500199#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#undef CONFIG_SYS_RAMBOOT
Jon Loeliger9553df82007-10-16 15:26:51 -0500201#endif
202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#if defined(CONFIG_SYS_RAMBOOT)
Jon Loeliger9553df82007-10-16 15:26:51 -0500204#undef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_SDRAM_SIZE 256
Jon Loeliger9553df82007-10-16 15:26:51 -0500206#endif
207
208#undef CONFIG_CLOCKS_IN_MHZ
209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_INIT_RAM_LOCK 1
211#ifndef CONFIG_SYS_INIT_RAM_LOCK
212#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Jon Loeliger9553df82007-10-16 15:26:51 -0500213#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
Jon Loeliger9553df82007-10-16 15:26:51 -0500215#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200216#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeliger9553df82007-10-16 15:26:51 -0500217
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200218#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeliger9553df82007-10-16 15:26:51 -0500220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
222#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
Jon Loeliger9553df82007-10-16 15:26:51 -0500223
224/* Serial Port */
225#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_NS16550_SERIAL
227#define CONFIG_SYS_NS16550_REG_SIZE 1
228#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeliger9553df82007-10-16 15:26:51 -0500229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeliger9553df82007-10-16 15:26:51 -0500231 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
234#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeliger9553df82007-10-16 15:26:51 -0500235
236/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_HUSH_PARSER
Jon Loeliger9553df82007-10-16 15:26:51 -0500238
239/*
240 * Pass open firmware flat tree to kernel
241 */
Jon Loeliger1df170f2008-01-04 12:07:27 -0600242#define CONFIG_OF_LIBFDT 1
243#define CONFIG_OF_BOARD_SETUP 1
244#define CONFIG_OF_STDOUT_VIA_ALIAS 1
245
Jon Loeliger9553df82007-10-16 15:26:51 -0500246
247/* maximum size of the flat tree (8K) */
248#define OF_FLAT_TREE_MAX_SIZE 8192
249
Jon Loeliger9553df82007-10-16 15:26:51 -0500250/*
251 * I2C
252 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200253#define CONFIG_SYS_I2C
254#define CONFIG_SYS_I2C_FSL
255#define CONFIG_SYS_FSL_I2C_SPEED 400000
256#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
257#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
258#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jon Loeliger9553df82007-10-16 15:26:51 -0500259
260/*
261 * General PCI
262 * Addresses are mapped 1-1.
263 */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600264#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
265#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
266#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600268#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600270#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500272
Jon Loeliger9553df82007-10-16 15:26:51 -0500273/* controller 1, Base address 0xa000 */
Kumar Galab8526212010-12-17 10:42:33 -0600274#define CONFIG_SYS_PCIE1_NAME "ULI"
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600275#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
276#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600278#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
280#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500281
282/* controller 2, Base Address 0x9000 */
Kumar Galab8526212010-12-17 10:42:33 -0600283#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600284#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
285#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600287#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
289#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500290
291
292#if defined(CONFIG_PCI)
293
294#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
295
Jon Loeliger9553df82007-10-16 15:26:51 -0500296#define CONFIG_PCI_PNP /* do pci plug-and-play */
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600297#define CONFIG_CMD_REGINFO
Jon Loeliger9553df82007-10-16 15:26:51 -0500298
Roy Zang7c2221e2008-01-15 16:38:38 +0800299#define CONFIG_ULI526X
300#ifdef CONFIG_ULI526X
Roy Zang1d8a49e2007-09-13 18:52:28 +0800301#endif
Jon Loeliger9553df82007-10-16 15:26:51 -0500302
Jon Loeliger9553df82007-10-16 15:26:51 -0500303/************************************************************
304 * USB support
305 ************************************************************/
York Sun070ba562007-10-31 14:59:04 -0500306#define CONFIG_PCI_OHCI 1
307#define CONFIG_USB_OHCI_NEW 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500308#define CONFIG_USB_KEYBOARD 1
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200309#define CONFIG_SYS_STDIO_DEREGISTER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_USB_EVENT_POLL 1
311#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
312#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
313#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500314
315#if !defined(CONFIG_PCI_PNP)
316#define PCI_ENET0_IOADDR 0xe0000000
317#define PCI_ENET0_MEMADDR 0xe0000000
318#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
319#endif
320
321#define CONFIG_DOS_PARTITION
322#define CONFIG_SCSI_AHCI
323
324#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -0500325#define CONFIG_LIBATA
Jon Loeliger9553df82007-10-16 15:26:51 -0500326#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
328#define CONFIG_SYS_SCSI_MAX_LUN 1
329#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
330#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jon Loeliger9553df82007-10-16 15:26:51 -0500331#endif
332
333#endif /* CONFIG_PCI */
334
335/*
336 * BAT0 2G Cacheable, non-guarded
337 * 0x0000_0000 2G DDR
338 */
Timur Tabi9ff32d82010-03-29 12:51:07 -0500339#define CONFIG_SYS_DBAT0L (BATL_PP_RW)
340#define CONFIG_SYS_IBAT0L (BATL_PP_RW)
Jon Loeliger9553df82007-10-16 15:26:51 -0500341
342/*
343 * BAT1 1G Cache-inhibited, guarded
344 * 0x8000_0000 256M PCI-1 Memory
345 * 0xa000_0000 256M PCI-Express 1 Memory
346 * 0x9000_0000 256M PCI-Express 2 Memory
347 */
348
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500350 | BATL_GUARDEDSTORAGE)
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600351#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
353#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
Jon Loeliger9553df82007-10-16 15:26:51 -0500354
355/*
Jason Jinf3bceaa2007-10-26 18:31:59 +0800356 * BAT2 16M Cache-inhibited, guarded
Jon Loeliger9553df82007-10-16 15:26:51 -0500357 * 0xe100_0000 1M PCI-1 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500358 */
359
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500361 | BATL_GUARDEDSTORAGE)
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600362#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
364#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
Jon Loeliger9553df82007-10-16 15:26:51 -0500365
366/*
Becky Bruce104992f2008-11-02 18:19:32 -0600367 * BAT3 4M Cache-inhibited, guarded
368 * 0xe000_0000 4M CCSR
369 */
370
371#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
372 | BATL_GUARDEDSTORAGE)
373#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
374#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
375#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
376
Jon Loeligerf6987382008-11-20 14:02:56 -0600377#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
378#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
379 | BATL_PP_RW | BATL_CACHEINHIBIT \
380 | BATL_GUARDEDSTORAGE)
381#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
382 | BATU_BL_1M | BATU_VS | BATU_VP)
383#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
384 | BATL_PP_RW | BATL_CACHEINHIBIT)
385#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
386#endif
387
Becky Bruce104992f2008-11-02 18:19:32 -0600388/*
389 * BAT4 32M Cache-inhibited, guarded
Jason Jinf3bceaa2007-10-26 18:31:59 +0800390 * 0xe200_0000 1M PCI-Express 2 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500391 * 0xe300_0000 1M PCI-Express 1 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500392 */
393
Becky Bruce104992f2008-11-02 18:19:32 -0600394#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500395 | BATL_GUARDEDSTORAGE)
Becky Bruce104992f2008-11-02 18:19:32 -0600396#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
397#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
Jon Loeliger9553df82007-10-16 15:26:51 -0500399
Becky Bruce104992f2008-11-02 18:19:32 -0600400
Jon Loeliger9553df82007-10-16 15:26:51 -0500401/*
402 * BAT5 128K Cacheable, non-guarded
403 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
404 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
406#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
407#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
408#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
Jon Loeliger9553df82007-10-16 15:26:51 -0500409
410/*
411 * BAT6 256M Cache-inhibited, guarded
412 * 0xf000_0000 256M FLASH
413 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500415 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
417#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
418#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
Jon Loeliger9553df82007-10-16 15:26:51 -0500419
Becky Brucebf9a8c32008-11-05 14:55:35 -0600420/* Map the last 1M of flash where we're running from reset */
421#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
422 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200423#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
Becky Brucebf9a8c32008-11-05 14:55:35 -0600424#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
425 | BATL_MEMCOHERENCE)
426#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
427
Jon Loeliger9553df82007-10-16 15:26:51 -0500428/*
429 * BAT7 4M Cache-inhibited, guarded
430 * 0xe800_0000 4M PIXIS
431 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500433 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
435#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
436#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
Jon Loeliger9553df82007-10-16 15:26:51 -0500437
438
439/*
440 * Environment
441 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200443#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200445#define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
446#define CONFIG_ENV_SIZE 0x2000
Jon Loeliger9553df82007-10-16 15:26:51 -0500447#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200448#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200450#define CONFIG_ENV_SIZE 0x2000
Jon Loeliger9553df82007-10-16 15:26:51 -0500451#endif
452
453#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeliger9553df82007-10-16 15:26:51 -0500455
456
457/*
458 * BOOTP options
459 */
460#define CONFIG_BOOTP_BOOTFILESIZE
461#define CONFIG_BOOTP_BOOTPATH
462#define CONFIG_BOOTP_GATEWAY
463#define CONFIG_BOOTP_HOSTNAME
464
465
466/*
467 * Command line configuration.
468 */
Jon Loeliger9553df82007-10-16 15:26:51 -0500469#define CONFIG_CMD_PING
470#define CONFIG_CMD_I2C
471#define CONFIG_CMD_MII
472
Jon Loeliger9553df82007-10-16 15:26:51 -0500473#if defined(CONFIG_PCI)
474#define CONFIG_CMD_PCI
475#define CONFIG_CMD_SCSI
476#define CONFIG_CMD_EXT2
York Sun070ba562007-10-31 14:59:04 -0500477#define CONFIG_CMD_USB
Jon Loeliger9553df82007-10-16 15:26:51 -0500478#endif
479
480
Jason Jin3473ab72008-05-13 11:50:36 +0800481#define CONFIG_WATCHDOG /* watchdog enabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
Jon Loeliger9553df82007-10-16 15:26:51 -0500483
484/*
485 * Miscellaneous configurable options
486 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_LONGHELP /* undef to save memory */
Timur Tabi6bee7642008-01-16 15:48:12 -0600488#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeliger9553df82007-10-16 15:26:51 -0500490
491#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500493#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500495#endif
496
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
498#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
499#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500500
501/*
502 * For booting Linux, the board info and command line data
503 * have to be in the first 8 MB of memory, since this is
504 * the maximum mapped by the Linux kernel during initialization.
505 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500507
Jon Loeliger9553df82007-10-16 15:26:51 -0500508#if defined(CONFIG_CMD_KGDB)
509#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeliger9553df82007-10-16 15:26:51 -0500510#endif
511
512/*
513 * Environment Configuration
514 */
515#define CONFIG_IPADDR 192.168.1.100
516
517#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000518#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000519#define CONFIG_BOOTFILE "uImage"
Jon Loeliger9553df82007-10-16 15:26:51 -0500520#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
521
522#define CONFIG_SERVERIP 192.168.1.1
523#define CONFIG_GATEWAYIP 192.168.1.1
524#define CONFIG_NETMASK 255.255.255.0
525
526/* default location for tftp and bootm */
527#define CONFIG_LOADADDR 1000000
528
529#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
530#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
531
532#define CONFIG_BAUDRATE 115200
533
534#if defined(CONFIG_PCI1)
535#define PCI_ENV \
536 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
537 "echo e;md ${a}e00 9\0" \
538 "pci1regs=setenv a e0008; run pcireg\0" \
539 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
540 "pci d.w $b.0 56 1\0" \
541 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
542 "pci w.w $b.0 56 ffff\0" \
543 "pci1err=setenv a e0008; run pcierr\0" \
544 "pci1errc=setenv a e0008; run pcierrc\0"
545#else
546#define PCI_ENV ""
547#endif
548
549#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
550#define PCIE_ENV \
551 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
552 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
553 "pcie1regs=setenv a e000a; run pciereg\0" \
554 "pcie2regs=setenv a e0009; run pciereg\0" \
555 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
556 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
557 "pci d $b.0 130 1\0" \
558 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
559 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
560 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
561 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
562 "pcie1err=setenv a e000a; run pcieerr\0" \
563 "pcie2err=setenv a e0009; run pcieerr\0" \
564 "pcie1errc=setenv a e000a; run pcieerrc\0" \
565 "pcie2errc=setenv a e0009; run pcieerrc\0"
566#else
567#define PCIE_ENV ""
568#endif
569
570#define DMA_ENV \
571 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
572 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
573 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
574 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
575 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
576 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
577 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
578 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
579
York Sun18153382007-10-29 13:57:53 -0500580#ifdef ENV_DEBUG
Jon Loeliger9553df82007-10-16 15:26:51 -0500581#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200582"netdev=eth0\0" \
583"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
584"tftpflash=tftpboot $loadaddr $uboot; " \
585 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
586 " +$filesize; " \
587 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
588 " +$filesize; " \
589 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
590 " $filesize; " \
591 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
592 " +$filesize; " \
593 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
594 " $filesize\0" \
595"consoledev=ttyS0\0" \
596"ramdiskaddr=2000000\0" \
597"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
598"fdtaddr=c00000\0" \
599"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
600"bdev=sda3\0" \
601"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
602"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
603"maxcpus=1" \
604"eoi=mw e00400b0 0\0" \
605"iack=md e00400a0 1\0" \
606"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
Jon Loeliger9553df82007-10-16 15:26:51 -0500607 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
608 "md ${a}f00 5\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200609"ddr1regs=setenv a e0002; run ddrreg\0" \
610"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
Jon Loeliger9553df82007-10-16 15:26:51 -0500611 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
612 "md ${a}e60 1; md ${a}ef0 1d\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200613"guregs=setenv a e00e0; run gureg\0" \
614"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
615"mcmregs=setenv a e0001; run mcmreg\0" \
616"diuregs=md e002c000 1d\0" \
617"dium=mw e002c01c\0" \
618"diuerr=md e002c014 1\0" \
619"pmregs=md e00e1000 2b\0" \
620"lawregs=md e0000c08 4b\0" \
621"lbcregs=md e0005000 36\0" \
622"dma0regs=md e0021100 12\0" \
623"dma1regs=md e0021180 12\0" \
624"dma2regs=md e0021200 12\0" \
625"dma3regs=md e0021280 12\0" \
Jon Loeliger9553df82007-10-16 15:26:51 -0500626 PCI_ENV \
627 PCIE_ENV \
628 DMA_ENV
York Sun18153382007-10-29 13:57:53 -0500629#else
Marek Vasut5368c552012-09-23 17:41:24 +0200630#define CONFIG_EXTRA_ENV_SETTINGS \
631 "netdev=eth0\0" \
632 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
633 "consoledev=ttyS0\0" \
634 "ramdiskaddr=2000000\0" \
635 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
636 "fdtaddr=c00000\0" \
637 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
638 "bdev=sda3\0"
York Sun18153382007-10-29 13:57:53 -0500639#endif
Jon Loeliger9553df82007-10-16 15:26:51 -0500640
641#define CONFIG_NFSBOOTCOMMAND \
642 "setenv bootargs root=/dev/nfs rw " \
643 "nfsroot=$serverip:$rootpath " \
644 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
645 "console=$consoledev,$baudrate $othbootargs;" \
646 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600647 "tftp $fdtaddr $fdtfile;" \
648 "bootm $loadaddr - $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500649
650#define CONFIG_RAMBOOTCOMMAND \
651 "setenv bootargs root=/dev/ram rw " \
652 "console=$consoledev,$baudrate $othbootargs;" \
653 "tftp $ramdiskaddr $ramdiskfile;" \
654 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600655 "tftp $fdtaddr $fdtfile;" \
656 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500657
658#define CONFIG_BOOTCOMMAND \
659 "setenv bootargs root=/dev/$bdev rw " \
660 "console=$consoledev,$baudrate $othbootargs;" \
661 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600662 "tftp $fdtaddr $fdtfile;" \
663 "bootm $loadaddr - $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500664
665#endif /* __CONFIG_H */