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wdenk6310eb92005-01-09 21:28:15 +00001/*
2 * Most of this taken from Redboot hal_platform_setup.h with cleanup
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <config.h>
24#include <version.h>
25#include <asm/arch/pxa-regs.h>
26
27DRAM_SIZE: .long CFG_DRAM_SIZE
28
29/* wait for coprocessor write complete */
30 .macro CPWAIT reg
31 mrc p15,0,\reg,c2,c0,0
32 mov \reg,\reg
33 sub pc,pc,#4
34 .endm
35
36.globl memsetup
37memsetup:
38
39 mov r10, lr
40
41 /* Set up GPIO pins first */
42
43 ldr r0, =GPSR0
44 ldr r1, =CFG_GPSR0_VAL
45 str r1, [r0]
46
47 ldr r0, =GPSR1
48 ldr r1, =CFG_GPSR1_VAL
49 str r1, [r0]
50
51 ldr r0, =GPSR2
52 ldr r1, =CFG_GPSR2_VAL
53 str r1, [r0]
54
55 ldr r0, =GPCR0
56 ldr r1, =CFG_GPCR0_VAL
57 str r1, [r0]
58
59 ldr r0, =GPCR1
60 ldr r1, =CFG_GPCR1_VAL
61 str r1, [r0]
62
63 ldr r0, =GPCR2
64 ldr r1, =CFG_GPCR2_VAL
65 str r1, [r0]
66
67 ldr r0, =GRER0
68 ldr r1, =CFG_GRER0_VAL
69 str r1, [r0]
70
71 ldr r0, =GRER1
72 ldr r1, =CFG_GRER1_VAL
73 str r1, [r0]
74
75 ldr r0, =GRER2
76 ldr r1, =CFG_GRER2_VAL
77 str r1, [r0]
78
79 ldr r0, =GFER0
80 ldr r1, =CFG_GFER0_VAL
81 str r1, [r0]
82
83 ldr r0, =GFER1
84 ldr r1, =CFG_GFER1_VAL
85 str r1, [r0]
86
87 ldr r0, =GFER2
88 ldr r1, =CFG_GFER2_VAL
89 str r1, [r0]
90
91 ldr r0, =GPDR0
92 ldr r1, =CFG_GPDR0_VAL
93 str r1, [r0]
94
95 ldr r0, =GPDR1
96 ldr r1, =CFG_GPDR1_VAL
97 str r1, [r0]
98
99 ldr r0, =GPDR2
100 ldr r1, =CFG_GPDR2_VAL
101 str r1, [r0]
102
103 ldr r0, =GAFR0_L
104 ldr r1, =CFG_GAFR0_L_VAL
105 str r1, [r0]
106
107 ldr r0, =GAFR0_U
108 ldr r1, =CFG_GAFR0_U_VAL
109 str r1, [r0]
110
111 ldr r0, =GAFR1_L
112 ldr r1, =CFG_GAFR1_L_VAL
113 str r1, [r0]
114
115 ldr r0, =GAFR1_U
116 ldr r1, =CFG_GAFR1_U_VAL
117 str r1, [r0]
118
119 ldr r0, =GAFR2_L
120 ldr r1, =CFG_GAFR2_L_VAL
121 str r1, [r0]
122
123 ldr r0, =GAFR2_U
124 ldr r1, =CFG_GAFR2_U_VAL
125 str r1, [r0]
126
127 /* enable GPIO pins */
128 ldr r0, =PSSR
129 ldr r1, =CFG_PSSR_VAL
130 str r1, [r0]
131
132
133/*********************************************************************
134 Initlialize Memory Controller
135
136 See PXA250 Operating System Developer's Guide
137
138 pause for 200 uSecs- allow internal clocks to settle
139 *Note: only need this if hard reset... doing it anyway for now
140*/
141
142 @ Step 1
143 @ ---- Wait 200 usec
144 ldr r3, =OSCR @ reset the OS Timer Count to zero
145 mov r2, #0
146 str r2, [r3]
147 ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
1481:
149 ldr r2, [r3]
150 cmp r4, r2
151 bgt 1b
152
153mem_init:
154 @ get memory controller base address
155 ldr r1, =MEMC_BASE
156
157@****************************************************************************
158@ Step 2
159@
160
161 @ Step 2a
162 @ write msc0, read back to ensure data latches
163 @
164 ldr r2, =CFG_MSC0_VAL
165 str r2, [r1, #MSC0_OFFSET]
166 ldr r2, [r1, #MSC0_OFFSET]
167
168 @ write msc1
169 ldr r2, =CFG_MSC1_VAL
170 str r2, [r1, #MSC1_OFFSET]
171 ldr r2, [r1, #MSC1_OFFSET]
172
173 @ write msc2
174 ldr r2, =CFG_MSC2_VAL
175 str r2, [r1, #MSC2_OFFSET]
176 ldr r2, [r1, #MSC2_OFFSET]
177
178
179@ Step 2b
180 @ write mecr
181 ldr r2, =CFG_MECR_VAL
182 str r2, [r1, #MECR_OFFSET]
183
184 @ write mcmem0
185 ldr r2, =CFG_MCMEM0_VAL
186 str r2, [r1, #MCMEM0_OFFSET]
187
188 @ write mcmem1
189 ldr r2, =CFG_MCMEM1_VAL
190 str r2, [r1, #MCMEM1_OFFSET]
191
192 @ write mcatt0
193 ldr r2, =CFG_MCATT0_VAL
194 str r2, [r1, #MCATT0_OFFSET]
195
196 @ write mcatt1
197 ldr r2, =CFG_MCATT1_VAL
198 str r2, [r1, #MCATT1_OFFSET]
199
200 @ write mcio0
201 ldr r2, =CFG_MCIO0_VAL
202 str r2, [r1, #MCIO0_OFFSET]
203
204 @ write mcio1
205 ldr r2, =CFG_MCIO1_VAL
206 str r2, [r1, #MCIO1_OFFSET]
207
208@ Step 2c
209 @ fly-by-dma is defeatured on this part
210 @ write flycnfg
211 @ldr r2, =CFG_FLYCNFG_VAL
212 @str r2, [r1, #FLYCNFG_OFFSET]
213
214/* FIXME Does this sequence really make sense */
215#ifdef REDBOOT_WAY
216 @ Step 2d
217 @ get the mdrefr settings
218 ldr r3, =CFG_MDREFR_VAL
219
220 @ extract DRI field (we need a valid DRI field)
221 @
222 ldr r2, =0xFFF
223
224 @ valid DRI field in r3
225 @
226 and r3, r3, r2
227
228 @ get the reset state of MDREFR
229 @
230 ldr r4, [r1, #MDREFR_OFFSET]
231
232 @ clear the DRI field
233 @
234 bic r4, r4, r2
235
236 @ insert the valid DRI field loaded above
237 @
238 orr r4, r4, r3
239
240 @ write back mdrefr
241 @
242 str r4, [r1, #MDREFR_OFFSET]
243
244 @ *Note: preserve the mdrefr value in r4 *
245
246@****************************************************************************
247@ Step 3
248@
249@ NO SRAM
250
251 mov pc, r10
252
253
254@****************************************************************************
255@ Step 4
256@
257
258 @ Assumes previous mdrefr value in r4, if not then read current mdrefr
259
260 @ clear the free-running clock bits
261 @ (clear K0Free, K1Free, K2Free
262 @
263 bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
264
265 @ set K0RUN for CPLD clock
266 @
267 orr r4, r4, #0x00002000
268
269 @ set K1RUN if bank 0 installed
270 @
271 orr r4, r4, #0x00010000
272
273 @ write back mdrefr
274 @
275 str r4, [r1, #MDREFR_OFFSET]
276 ldr r4, [r1, #MDREFR_OFFSET]
277
278 @ deassert SLFRSH
279 @
280 bic r4, r4, #0x00400000
281
282 @ write back mdrefr
283 @
284 str r4, [r1, #MDREFR_OFFSET]
285
286 @ assert E1PIN
287 @
288 orr r4, r4, #0x00008000
289
290 @ write back mdrefr
291 @
292 str r4, [r1, #MDREFR_OFFSET]
293 ldr r4, [r1, #MDREFR_OFFSET]
294 nop
295 nop
296#else
297 @ Step 2d
298 @ get the mdrefr settings
299 ldr r3, =CFG_MDREFR_VAL
300
301 @ write back mdrefr
302 @
303 str r4, [r1, #MDREFR_OFFSET]
304
305 @ Step 4
306
307 @ set K0RUN for CPLD clock
308 @
309 orr r4, r4, #0x00002000
310
311 @ set K1RUN for bank 0
312 @
313 orr r4, r4, #0x00010000
314
315 @ write back mdrefr
316 @
317 str r4, [r1, #MDREFR_OFFSET]
318 ldr r4, [r1, #MDREFR_OFFSET]
319
320 @ deassert SLFRSH
321 @
322 bic r4, r4, #0x00400000
323
324 @ write back mdrefr
325 @
326 str r4, [r1, #MDREFR_OFFSET]
327
328 @ assert E1PIN
329 @
330 orr r4, r4, #0x00008000
331
332 @ write back mdrefr
333 @
334 str r4, [r1, #MDREFR_OFFSET]
335 ldr r4, [r1, #MDREFR_OFFSET]
336 nop
337 nop
338#endif
339
340 @ Step 4d
341 @ fetch platform value of mdcnfg
342 @
343 ldr r2, =CFG_MDCNFG_VAL
344
345 @ disable all sdram banks
346 @
347 bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
348 bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
349
350 @ program banks 0/1 for bus width
351 @
352 bic r2, r2, #MDCNFG_DWID0 @0=32-bit
353
354 @ write initial value of mdcnfg, w/o enabling sdram banks
355 @
356 str r2, [r1, #MDCNFG_OFFSET]
357
358 @ Step 4e
359 @ pause for 200 uSecs
360 @
361 ldr r3, =OSCR @ reset the OS Timer Count to zero
362 mov r2, #0
363 str r2, [r3]
364 ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
365 1:
366 ldr r2, [r3]
367 cmp r4, r2
368 bgt 1b
369
370 /* Why is this here??? */
371 mov r0, #0x78 @turn everything off
372 mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
373
374 @ Step 4f
375 @ Access memory *not yet enabled* for CBR refresh cycles (8)
376 @ - CBR is generated for all banks
377
378 ldr r2, =CFG_DRAM_BASE
379 str r2, [r2]
380 str r2, [r2]
381 str r2, [r2]
382 str r2, [r2]
383 str r2, [r2]
384 str r2, [r2]
385 str r2, [r2]
386 str r2, [r2]
387
388 @ Step 4g
389 @get memory controller base address
390 @
391 ldr r1, =MEMC_BASE
392
393 @fetch current mdcnfg value
394 @
395 ldr r3, [r1, #MDCNFG_OFFSET]
396
397 @enable sdram bank 0 if installed (must do for any populated bank)
398 @
399 orr r3, r3, #MDCNFG_DE0
400
401 @write back mdcnfg, enabling the sdram bank(s)
402 @
403 str r3, [r1, #MDCNFG_OFFSET]
404
405 @ Step 4h
406 @ write mdmrs
407 @
408 ldr r2, =CFG_MDMRS_VAL
409 str r2, [r1, #MDMRS_OFFSET]
410
411 @ Done Memory Init
412
413 /*SET_LED 6 */
414
415 @********************************************************************
416 @ Disable (mask) all interrupts at the interrupt controller
417 @
418
419 @ clear the interrupt level register (use IRQ, not FIQ)
420 @
421 mov r1, #0
422 ldr r2, =ICLR
423 str r1, [r2]
424
425 @ Set interrupt mask register
426 @
427 ldr r1, =CFG_ICMR_VAL
428 ldr r2, =ICMR
429 str r1, [r2]
430
431 @ ********************************************************************
432 @ Disable the peripheral clocks, and set the core clock
433 @
434
435 @ Turn Off ALL on-chip peripheral clocks for re-configuration
436 @
437 ldr r1, =CKEN
438 mov r2, #0
439 str r2, [r1]
440
441 @ set core clocks
442 @
443 ldr r2, =CFG_CCCR_VAL
444 ldr r1, =CCCR
445 str r2, [r1]
446
447 #ifdef ENABLE32KHZ
448 @ enable the 32Khz oscillator for RTC and PowerManager
449 @
450 ldr r1, =OSCC
451 mov r2, #OSCC_OON
452 str r2, [r1]
453
454 @ NOTE: spin here until OSCC.OOK get set,
455 @ meaning the PLL has settled.
456 @
45760:
458 ldr r2, [r1]
459 ands r2, r2, #1
460 beq 60b
461#endif
462
463 @ Turn on needed clocks
464 @
465 ldr r1, =CKEN
466 ldr r2, =CFG_CKEN_VAL
467 str r2, [r1]
468
469 /*SET_LED 7 */
470
471/* Is this needed???? */
472#define NODEBUG
473#ifdef NODEBUG
474 /*Disable software and data breakpoints */
475 mov r0,#0
476 mcr p15,0,r0,c14,c8,0 /* ibcr0 */
477 mcr p15,0,r0,c14,c9,0 /* ibcr1 */
478 mcr p15,0,r0,c14,c4,0 /* dbcon */
479
480 /*Enable all debug functionality */
481 mov r0,#0x80000000
482 mcr p14,0,r0,c10,c0,0 /* dcsr */
483
484#endif
485
486 mov pc, r10
487
488@ End memsetup