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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sascha Hauer9b56f4f2008-03-26 20:40:42 +01002/*
3 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer9b56f4f2008-03-26 20:40:42 +01004 */
5
6#include <common.h>
Simon Glassa8ba5692014-10-01 19:57:27 -06007#include <dm.h>
8#include <errno.h>
Stefano Babic4ec3d2a2010-08-18 10:22:42 +02009#include <watchdog.h>
Ilya Yanok47d19da2009-06-08 04:12:46 +040010#include <asm/arch/imx-regs.h>
11#include <asm/arch/clock.h>
Masahiro Yamada86256b72014-10-24 12:41:19 +090012#include <dm/platform_data/serial_mxc.h>
Marek Vasuta9434722012-09-14 22:37:43 +020013#include <serial.h>
14#include <linux/compiler.h>
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010015
Sascha Hauer9b56f4f2008-03-26 20:40:42 +010016/* UART Control Register Bit Fields.*/
Jagan Teki52c14ca2017-06-06 05:31:50 +000017#define URXD_CHARRDY (1<<15)
18#define URXD_ERR (1<<14)
19#define URXD_OVRRUN (1<<13)
20#define URXD_FRMERR (1<<12)
21#define URXD_BRK (1<<11)
22#define URXD_PRERR (1<<10)
23#define URXD_RX_DATA (0xFF)
24#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
25#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
26#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
27#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
28#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
29#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
30#define UCR1_IREN (1<<7) /* Infrared interface enable */
31#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
32#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
33#define UCR1_SNDBRK (1<<4) /* Send break */
34#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
35#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
36#define UCR1_DOZE (1<<1) /* Doze */
37#define UCR1_UARTEN (1<<0) /* UART enabled */
38#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
39#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
40#define UCR2_CTSC (1<<13) /* CTS pin control */
41#define UCR2_CTS (1<<12) /* Clear to send */
42#define UCR2_ESCEN (1<<11) /* Escape enable */
43#define UCR2_PREN (1<<8) /* Parity enable */
44#define UCR2_PROE (1<<7) /* Parity odd/even */
45#define UCR2_STPB (1<<6) /* Stop */
46#define UCR2_WS (1<<5) /* Word size */
47#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
48#define UCR2_TXEN (1<<2) /* Transmitter enabled */
49#define UCR2_RXEN (1<<1) /* Receiver enabled */
50#define UCR2_SRST (1<<0) /* SW reset */
51#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
52#define UCR3_PARERREN (1<<12) /* Parity enable */
53#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
54#define UCR3_DSR (1<<10) /* Data set ready */
55#define UCR3_DCD (1<<9) /* Data carrier detect */
56#define UCR3_RI (1<<8) /* Ring indicator */
57#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
58#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
59#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
60#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
61#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
62#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
63#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
64#define UCR3_BPEN (1<<0) /* Preset registers enable */
65#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
66#define UCR4_INVR (1<<9) /* Inverted infrared reception */
67#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
68#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
69#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
70#define UCR4_IRSC (1<<5) /* IR special case */
71#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
72#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
73#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
74#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
75#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
76#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
77#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
78#define RFDIV 4 /* divide input clock by 2 */
79#define UFCR_DCEDTE (1<<6) /* DTE mode select */
80#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
81#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
82#define USR1_RTSS (1<<14) /* RTS pin status */
83#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
84#define USR1_RTSD (1<<12) /* RTS delta */
85#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
86#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
87#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
88#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
89#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
90#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
91#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
92#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
93#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
94#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
95#define USR2_IDLE (1<<12) /* Idle condition */
96#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
97#define USR2_WAKE (1<<7) /* Wake */
98#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
99#define USR2_TXDC (1<<3) /* Transmitter complete */
100#define USR2_BRCD (1<<2) /* Break condition */
101#define USR2_ORE (1<<1) /* Overrun error */
102#define USR2_RDR (1<<0) /* Recv data ready */
103#define UTS_FRCPERR (1<<13) /* Force parity error */
104#define UTS_LOOP (1<<12) /* Loop tx and rx */
105#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
106#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
107#define UTS_TXFULL (1<<4) /* TxFIFO full */
108#define UTS_RXFULL (1<<3) /* RxFIFO full */
109#define UTS_SOFTRS (1<<0) /* Software reset */
Jagan Teki45d97512017-06-06 05:31:49 +0000110#define TXTL 2 /* reset default */
111#define RXTL 1 /* reset default */
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100112
Stefan Agnera99546a2016-10-05 15:27:03 -0700113DECLARE_GLOBAL_DATA_PTR;
114
Jagan Tekiffa8bcd2017-06-06 05:31:45 +0000115struct mxc_uart {
116 u32 rxd;
117 u32 spare0[15];
118
119 u32 txd;
120 u32 spare1[15];
121
122 u32 cr1;
123 u32 cr2;
124 u32 cr3;
125 u32 cr4;
126
127 u32 fcr;
128 u32 sr1;
129 u32 sr2;
130 u32 esc;
131
132 u32 tim;
133 u32 bir;
134 u32 bmr;
135 u32 brc;
136
137 u32 onems;
138 u32 ts;
139};
140
Max Krummenachera2453202019-02-01 16:04:50 +0100141static void _mxc_serial_init(struct mxc_uart *base, int use_dte)
Jagan Teki97548d52017-06-06 05:31:48 +0000142{
143 writel(0, &base->cr1);
144 writel(0, &base->cr2);
145
146 while (!(readl(&base->cr2) & UCR2_SRST));
147
Max Krummenachera2453202019-02-01 16:04:50 +0100148 if (use_dte)
149 writel(0x404 | UCR3_ADNIMP, &base->cr3);
150 else
151 writel(0x704 | UCR3_ADNIMP, &base->cr3);
152
Jagan Teki97548d52017-06-06 05:31:48 +0000153 writel(0x704 | UCR3_ADNIMP, &base->cr3);
154 writel(0x8000, &base->cr4);
155 writel(0x2b, &base->esc);
156 writel(0, &base->tim);
157
158 writel(0, &base->ts);
159}
160
Jagan Teki45d97512017-06-06 05:31:49 +0000161static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
162 unsigned long baudrate, bool use_dte)
163{
164 u32 tmp;
165
166 tmp = RFDIV << UFCR_RFDIV_SHF;
167 if (use_dte)
168 tmp |= UFCR_DCEDTE;
169 else
170 tmp |= (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF);
171 writel(tmp, &base->fcr);
172
173 writel(0xf, &base->bir);
174 writel(clk / (2 * baudrate), &base->bmr);
175
176 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
177 &base->cr2);
178 writel(UCR1_UARTEN, &base->cr1);
179}
180
Adam Forde434b412019-02-19 22:07:22 -0600181#if !CONFIG_IS_ENABLED(DM_SERIAL)
Simon Glassa8ba5692014-10-01 19:57:27 -0600182
183#ifndef CONFIG_MXC_UART_BASE
184#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
185#endif
186
Jagan Tekiffa8bcd2017-06-06 05:31:45 +0000187#define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
Simon Glassa8ba5692014-10-01 19:57:27 -0600188
Marek Vasuta9434722012-09-14 22:37:43 +0200189static void mxc_serial_setbrg(void)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100190{
Stefano Babic71d64c02010-01-20 18:20:19 +0100191 u32 clk = imx_get_uartclk();
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100192
193 if (!gd->baudrate)
194 gd->baudrate = CONFIG_BAUDRATE;
195
Jagan Teki45d97512017-06-06 05:31:49 +0000196 _mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100197}
198
Marek Vasuta9434722012-09-14 22:37:43 +0200199static int mxc_serial_getc(void)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100200{
Jagan Tekiffa8bcd2017-06-06 05:31:45 +0000201 while (readl(&mxc_base->ts) & UTS_RXEMPTY)
Stefano Babic4ec3d2a2010-08-18 10:22:42 +0200202 WATCHDOG_RESET();
Jagan Tekiffa8bcd2017-06-06 05:31:45 +0000203 return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100204}
205
Marek Vasuta9434722012-09-14 22:37:43 +0200206static void mxc_serial_putc(const char c)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100207{
Alison Wang055457e2016-03-02 11:00:37 +0800208 /* If \n, also do \r */
209 if (c == '\n')
210 serial_putc('\r');
211
Jagan Tekiffa8bcd2017-06-06 05:31:45 +0000212 writel(c, &mxc_base->txd);
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100213
214 /* wait for transmitter to be ready */
Jagan Tekiffa8bcd2017-06-06 05:31:45 +0000215 while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
Stefano Babic4ec3d2a2010-08-18 10:22:42 +0200216 WATCHDOG_RESET();
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100217}
218
Jagan Teki52c14ca2017-06-06 05:31:50 +0000219/* Test whether a character is in the RX buffer */
Marek Vasuta9434722012-09-14 22:37:43 +0200220static int mxc_serial_tstc(void)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100221{
222 /* If receive fifo is empty, return false */
Jagan Tekiffa8bcd2017-06-06 05:31:45 +0000223 if (readl(&mxc_base->ts) & UTS_RXEMPTY)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100224 return 0;
225 return 1;
226}
227
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100228/*
229 * Initialise the serial port with the given baudrate. The settings
230 * are always 8 data bits, no parity, 1 stop bit, no start bits.
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100231 */
Marek Vasuta9434722012-09-14 22:37:43 +0200232static int mxc_serial_init(void)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100233{
Max Krummenachera2453202019-02-01 16:04:50 +0100234 _mxc_serial_init(mxc_base, false);
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100235
236 serial_setbrg();
237
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100238 return 0;
239}
Marek Vasuta9434722012-09-14 22:37:43 +0200240
Marek Vasuta9434722012-09-14 22:37:43 +0200241static struct serial_device mxc_serial_drv = {
242 .name = "mxc_serial",
243 .start = mxc_serial_init,
244 .stop = NULL,
245 .setbrg = mxc_serial_setbrg,
246 .putc = mxc_serial_putc,
Marek Vasutec3fd682012-10-06 14:07:02 +0000247 .puts = default_serial_puts,
Marek Vasuta9434722012-09-14 22:37:43 +0200248 .getc = mxc_serial_getc,
249 .tstc = mxc_serial_tstc,
250};
251
252void mxc_serial_initialize(void)
253{
254 serial_register(&mxc_serial_drv);
255}
256
257__weak struct serial_device *default_serial_console(void)
258{
259 return &mxc_serial_drv;
260}
Simon Glassa8ba5692014-10-01 19:57:27 -0600261#endif
262
Adam Forde434b412019-02-19 22:07:22 -0600263#if CONFIG_IS_ENABLED(DM_SERIAL)
Simon Glassa8ba5692014-10-01 19:57:27 -0600264
Simon Glassa8ba5692014-10-01 19:57:27 -0600265int mxc_serial_setbrg(struct udevice *dev, int baudrate)
266{
Simon Glass0fd3d912020-12-22 19:30:28 -0700267 struct mxc_serial_plat *plat = dev_get_plat(dev);
Simon Glassa8ba5692014-10-01 19:57:27 -0600268 u32 clk = imx_get_uartclk();
269
Jagan Teki45d97512017-06-06 05:31:49 +0000270 _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
Simon Glassa8ba5692014-10-01 19:57:27 -0600271
272 return 0;
273}
274
275static int mxc_serial_probe(struct udevice *dev)
276{
Simon Glass0fd3d912020-12-22 19:30:28 -0700277 struct mxc_serial_plat *plat = dev_get_plat(dev);
Simon Glassa8ba5692014-10-01 19:57:27 -0600278
Max Krummenachera2453202019-02-01 16:04:50 +0100279 _mxc_serial_init(plat->reg, plat->use_dte);
Simon Glassa8ba5692014-10-01 19:57:27 -0600280
281 return 0;
282}
283
284static int mxc_serial_getc(struct udevice *dev)
285{
Simon Glass0fd3d912020-12-22 19:30:28 -0700286 struct mxc_serial_plat *plat = dev_get_plat(dev);
Simon Glassa8ba5692014-10-01 19:57:27 -0600287 struct mxc_uart *const uart = plat->reg;
288
289 if (readl(&uart->ts) & UTS_RXEMPTY)
290 return -EAGAIN;
291
292 return readl(&uart->rxd) & URXD_RX_DATA;
293}
294
295static int mxc_serial_putc(struct udevice *dev, const char ch)
296{
Simon Glass0fd3d912020-12-22 19:30:28 -0700297 struct mxc_serial_plat *plat = dev_get_plat(dev);
Simon Glassa8ba5692014-10-01 19:57:27 -0600298 struct mxc_uart *const uart = plat->reg;
299
300 if (!(readl(&uart->ts) & UTS_TXEMPTY))
301 return -EAGAIN;
302
303 writel(ch, &uart->txd);
304
305 return 0;
306}
307
308static int mxc_serial_pending(struct udevice *dev, bool input)
309{
Simon Glass0fd3d912020-12-22 19:30:28 -0700310 struct mxc_serial_plat *plat = dev_get_plat(dev);
Simon Glassa8ba5692014-10-01 19:57:27 -0600311 struct mxc_uart *const uart = plat->reg;
312 uint32_t sr2 = readl(&uart->sr2);
313
314 if (input)
315 return sr2 & USR2_RDR ? 1 : 0;
316 else
317 return sr2 & USR2_TXDC ? 0 : 1;
318}
319
320static const struct dm_serial_ops mxc_serial_ops = {
321 .putc = mxc_serial_putc,
322 .pending = mxc_serial_pending,
323 .getc = mxc_serial_getc,
324 .setbrg = mxc_serial_setbrg,
325};
326
Stefan Agnera99546a2016-10-05 15:27:03 -0700327#if CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glassd1998a92020-12-03 16:55:21 -0700328static int mxc_serial_of_to_plat(struct udevice *dev)
Stefan Agnera99546a2016-10-05 15:27:03 -0700329{
Simon Glass0fd3d912020-12-22 19:30:28 -0700330 struct mxc_serial_plat *plat = dev_get_plat(dev);
Stefan Agnera99546a2016-10-05 15:27:03 -0700331 fdt_addr_t addr;
332
Masahiro Yamada25484932020-07-17 14:36:48 +0900333 addr = dev_read_addr(dev);
Stefan Agnera99546a2016-10-05 15:27:03 -0700334 if (addr == FDT_ADDR_T_NONE)
335 return -EINVAL;
336
337 plat->reg = (struct mxc_uart *)addr;
338
Simon Glasse160f7d2017-01-17 16:52:55 -0700339 plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
Stefan Agnera99546a2016-10-05 15:27:03 -0700340 "fsl,dte-mode");
341 return 0;
342}
343
344static const struct udevice_id mxc_serial_ids[] = {
Lukasz Majewski2756fd12019-07-09 17:00:05 +0200345 { .compatible = "fsl,imx21-uart" },
346 { .compatible = "fsl,imx53-uart" },
Marek Vasut6757fa52019-05-17 21:56:40 +0200347 { .compatible = "fsl,imx6sx-uart" },
Sébastien Szymanski3a5d6362017-03-07 14:33:24 +0100348 { .compatible = "fsl,imx6ul-uart" },
Stefan Agnera99546a2016-10-05 15:27:03 -0700349 { .compatible = "fsl,imx7d-uart" },
Bernhard Messerklinger4684fa82018-09-03 10:17:35 +0200350 { .compatible = "fsl,imx6q-uart" },
Stefan Agnera99546a2016-10-05 15:27:03 -0700351 { }
352};
353#endif
354
Simon Glassa8ba5692014-10-01 19:57:27 -0600355U_BOOT_DRIVER(serial_mxc) = {
356 .name = "serial_mxc",
357 .id = UCLASS_SERIAL,
Stefan Agnera99546a2016-10-05 15:27:03 -0700358#if CONFIG_IS_ENABLED(OF_CONTROL)
359 .of_match = mxc_serial_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700360 .of_to_plat = mxc_serial_of_to_plat,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700361 .plat_auto = sizeof(struct mxc_serial_plat),
Stefan Agnera99546a2016-10-05 15:27:03 -0700362#endif
Simon Glassa8ba5692014-10-01 19:57:27 -0600363 .probe = mxc_serial_probe,
364 .ops = &mxc_serial_ops,
365 .flags = DM_FLAG_PRE_RELOC,
366};
367#endif
Jagan Teki61366b72017-06-06 05:31:51 +0000368
369#ifdef CONFIG_DEBUG_UART_MXC
370#include <debug_uart.h>
371
372static inline void _debug_uart_init(void)
373{
374 struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
375
Max Krummenachera2453202019-02-01 16:04:50 +0100376 _mxc_serial_init(base, false);
Jagan Teki61366b72017-06-06 05:31:51 +0000377 _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
378 CONFIG_BAUDRATE, false);
379}
380
381static inline void _debug_uart_putc(int ch)
382{
383 struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
384
385 while (!(readl(&base->ts) & UTS_TXEMPTY))
386 WATCHDOG_RESET();
387
388 writel(ch, &base->txd);
389}
390
391DEBUG_UART_FUNCS
392
393#endif